intel-gen4asm: Changes to 'master'

[Haihao Xiang]

 src/brw_defines.h |   11 ++++++++++-
 src/gram.y        |    9 ++++++---
 src/lex.l         |    9 +++++++++
 3 files changed, 25 insertions(+), 4 deletions(-)

New commits:
commit e3372020204238787f52eba38d7b8f9507da58cd
Author: Homer Hsing <homer.xing at intel.com>
Date:   Fri Sep 14 09:02:01 2012 +0800

    Supporting integer subtraction with borrow
    
    subb: subtract unsigned integer src1 from src0. store the result
    in dst and store the borrow (0 or 1) as a 32-bit value in acc.

commit c3ab9055a83c3049167b8fbbea022de18f6ff73d
Author: Homer Hsing <homer.xing at intel.com>
Date:   Fri Sep 14 08:56:36 2012 +0800

    Supporting find first bit instructions
    
    fbh: Find the first significant bit searching from the high bits
    in src0 and store the result in dst.
    
    fbl: Find the first 1 bit searching from the low bits in src0
    and store the result in dst.

commit 3d4c2d8a8ae49a1641d00cd85dd88438bf497220
Author: Homer Hsing <homer.xing at intel.com>
Date:   Fri Sep 14 08:50:18 2012 +0800

    Supporting half precision to single precision float convertion
    
    The f16to32 instruction converts the half precision float
    in src0 to single precision float and storing in dst.
    
    The f32to16 instruction converts the single precision float
    in src0 to half precision float and storing in the lower word
    of each channel in dst.

commit 09c359703347fa5db70ed85d02839d65da5e823f
Author: Homer Hsing <homer.xing at intel.com>
Date:   Fri Sep 14 08:41:16 2012 +0800

    Supporting count bit set instruction
    
    The cbit instruction counts component-wise the total bits set
    in src0 and stores the resulting counts in dst.

commit bc792a94da600f4ee64591aab4ddddb606cc10b9
Author: Homer Hsing <homer.xing at intel.com>
Date:   Fri Sep 14 08:32:12 2012 +0800

    Supporting instruction "reverse bits"
    
    The bfrev instruction component-wise reverses all the bits in src0
    and stores the results in dst.

commit 59a04d4ad2973368cf1ae182ead40676e26f4598
Author: Homer Hsing <homer.xing at intel.com>
Date:   Fri Sep 14 08:27:41 2012 +0800

    Supporting instruction Bit Field Insert 1
    
    The bfi1 instruction component-wise generates mask with control
    from src0 and src1 and stores the results in dst.

commit f98139b1389132b4cc86511f0725c0beedd23ad6
Author: Homer Hsing <homer.xing at intel.com>
Date:   Fri Sep 14 08:24:54 2012 +0800

    Delete an extra space character in brw_defines.h
    
    Now the column is aligned and the code is nicer.

commit e6728420d3af07790a495201f7995c17c29ce9cb
Author: Homer Hsing <homer.xing at intel.com>
Date:   Fri Sep 14 08:20:13 2012 +0800

    Supporting addc instruction
    
    The addc instruction performs component-wise addition of
    src0 and src1 and stores the results in dst;
    it also stores the carry into acc.