xf86-video-ati: Branch 'kms-only' - 4 commits
Dave Airlie
airlied at kemper.freedesktop.org
Fri Jun 15 08:43:59 PDT 2012
src/Makefile.am | 1
src/radeon.h | 13
src/radeon_accel.c | 793 +++++++++++++++++++++++
src/radeon_commonfuncs.c | 816 ------------------------
src/radeon_driver.c | 4
src/radeon_exa_funcs.c | 113 +--
src/radeon_exa_render.c | 83 --
src/radeon_macros.h | 14
src/radeon_textured_video.c | 17
src/radeon_textured_videofuncs.c | 1302 +++++++++++++++++++--------------------
src/radeon_video.c | 2
11 files changed, 1513 insertions(+), 1645 deletions(-)
New commits:
commit 96644f96f1a2df1d7d1ca8cbdc9a105affdb4f32
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jun 15 16:34:53 2012 +0100
radeon: make exa copy funcs static.
These are no longer used outside this area.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/radeon.h b/src/radeon.h
index 39c61a2..5d7190e 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -542,14 +542,7 @@ extern unsigned eg_tile_split(unsigned tile_split);
extern Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t);
/* radeon_exa_funcs.c */
-extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX,
- int dstY, int w, int h);
-extern Bool RADEONDrawInitCP(ScreenPtr pScreen);
-extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn,
- uint32_t src_pitch_offset,
- uint32_t dst_pitch_offset,
- uint32_t datatype, int rop,
- Pixel planemask);
+extern Bool RADEONDrawInit(ScreenPtr pScreen);
extern Bool R600DrawInit(ScreenPtr pScreen);
extern Bool R600LoadShaders(ScrnInfoPtr pScrn);
extern Bool EVERGREENDrawInit(ScreenPtr pScreen);
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 7832744..16e81f3 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -222,7 +222,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
if (!R600DrawInit(pScreen))
return FALSE;
} else {
- if (!RADEONDrawInitCP(pScreen))
+ if (!RADEONDrawInit(pScreen))
return FALSE;
}
}
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index d3dba6f..d1c7d1e 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -197,7 +197,7 @@ RADEONSolid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
FINISH_ACCEL();
}
-void
+static void
RADEONDoPrepareCopy(ScrnInfoPtr pScrn, uint32_t src_pitch_offset,
uint32_t dst_pitch_offset, uint32_t datatype, int rop,
Pixel planemask)
@@ -275,7 +275,7 @@ RADEONPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
return TRUE;
}
-void
+static void
RADEONCopy(PixmapPtr pDst,
int srcX, int srcY,
int dstX, int dstY,
commit 83904b820b81d226940ec6d663246f243f92e7ba
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jun 15 16:30:41 2012 +0100
radeon: drop FUNC_NAME macro and ONCE_ONLY stuff
Drop all the CP vs MMIO macros that name functions.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/radeon.h b/src/radeon.h
index 21ecfd9..39c61a2 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -523,8 +523,8 @@ uint32_t radeonGetPixmapOffset(PixmapPtr pPix);
extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn);
/* radeon_commonfuncs.c */
-extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix,
- xf86CrtcPtr crtc, int start, int stop);
+extern void RADEONWaitForVLine(ScrnInfoPtr pScrn, PixmapPtr pPix,
+ xf86CrtcPtr crtc, int start, int stop);
/* radeon_driver.c */
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index b21fb14..7832744 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -229,7 +229,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
return TRUE;
}
-static void RADEONInit3DEngineCP(ScrnInfoPtr pScrn)
+static void RADEONInit3DEngineInternal(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t gb_tile_config, vap_cntl;
@@ -953,8 +953,8 @@ static void RADEONInit3DEngineCP(ScrnInfoPtr pScrn)
}
/* inserts a wait for vline in the command stream */
-void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix,
- xf86CrtcPtr crtc, int start, int stop)
+void RADEONWaitForVLine(ScrnInfoPtr pScrn, PixmapPtr pPix,
+ xf86CrtcPtr crtc, int start, int stop)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
drmmode_crtc_private_ptr drmmode_crtc;
@@ -1009,7 +1009,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR (pScrn);
if (info->directRenderingEnabled) {
- RADEONInit3DEngineCP(pScrn);
+ RADEONInit3DEngineInternal(pScrn);
}
info->accel_state->XInited3D = TRUE;
}
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 39b3428..d3dba6f 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -31,14 +31,6 @@
*
*/
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-
#include <errno.h>
#include <string.h>
@@ -47,7 +39,7 @@
#include "exa.h"
static int
-FUNC_NAME(RADEONMarkSync)(ScreenPtr pScreen)
+RADEONMarkSync(ScreenPtr pScreen)
{
RINFO_FROM_SCREEN(pScreen);
@@ -57,12 +49,12 @@ FUNC_NAME(RADEONMarkSync)(ScreenPtr pScreen)
}
static void
-FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker)
+RADEONSync(ScreenPtr pScreen, int marker)
{
}
-static void FUNC_NAME(Emit2DState)(ScrnInfoPtr pScrn, int op)
+static void Emit2DState(ScrnInfoPtr pScrn, int op)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
int has_src;
@@ -98,11 +90,11 @@ static void FUNC_NAME(Emit2DState)(ScrnInfoPtr pScrn, int op)
if (op)
info->state_2d.op = op;
- info->reemit_current2d = FUNC_NAME(Emit2DState);
+ info->reemit_current2d = Emit2DState;
}
static void
-FUNC_NAME(RADEONFlush2D)(PixmapPtr pPix)
+RADEONFlush2D(PixmapPtr pPix)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
@@ -116,16 +108,16 @@ FUNC_NAME(RADEONFlush2D)(PixmapPtr pPix)
}
static void
-FUNC_NAME(RADEONDone2D)(PixmapPtr pPix)
+RADEONDone2D(PixmapPtr pPix)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
info->state_2d.op = 0;
- FUNC_NAME(RADEONFlush2D)(pPix);
+ RADEONFlush2D(pPix);
}
static Bool
-FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
+RADEONPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
uint32_t datatype, dst_pitch_offset;
@@ -176,28 +168,28 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
info->accel_state->dst_pix = pPix;
- FUNC_NAME(Emit2DState)(pScrn, RADEON_2D_EXA_SOLID);
+ Emit2DState(pScrn, RADEON_2D_EXA_SOLID);
return TRUE;
}
static void
-FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2)
+RADEONSolid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
TRACE;
if (CS_FULL(info->cs)) {
- FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix);
+ RADEONFlush2D(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
}
if (info->accel_state->vsync)
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pPix,
- radeon_pick_best_crtc(pScrn, x1, x2, y1, y2),
- y1, y2);
+ RADEONWaitForVLine(pScrn, pPix,
+ radeon_pick_best_crtc(pScrn, x1, x2, y1, y2),
+ y1, y2);
BEGIN_ACCEL(2);
OUT_ACCEL_REG(RADEON_DST_Y_X, (y1 << 16) | x1);
@@ -206,9 +198,9 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2)
}
void
-FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset,
- uint32_t dst_pitch_offset, uint32_t datatype, int rop,
- Pixel planemask)
+RADEONDoPrepareCopy(ScrnInfoPtr pScrn, uint32_t src_pitch_offset,
+ uint32_t dst_pitch_offset, uint32_t datatype, int rop,
+ Pixel planemask)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -233,14 +225,14 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset,
info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX
| RADEON_DEFAULT_SC_BOTTOM_MAX);
- FUNC_NAME(Emit2DState)(pScrn, RADEON_2D_EXA_COPY);
+ Emit2DState(pScrn, RADEON_2D_EXA_COPY);
}
static Bool
-FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst,
- int xdir, int ydir,
- int rop,
- Pixel planemask)
+RADEONPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
+ int xdir, int ydir,
+ int rop,
+ Pixel planemask)
{
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
uint32_t datatype, src_pitch_offset, dst_pitch_offset;
@@ -277,24 +269,24 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst,
info->accel_state->ydir = ydir;
info->accel_state->dst_pix = pDst;
- FUNC_NAME(RADEONDoPrepareCopy)(pScrn, src_pitch_offset, dst_pitch_offset,
- datatype, rop, planemask);
+ RADEONDoPrepareCopy(pScrn, src_pitch_offset, dst_pitch_offset,
+ datatype, rop, planemask);
return TRUE;
}
void
-FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
- int srcX, int srcY,
- int dstX, int dstY,
- int w, int h)
+RADEONCopy(PixmapPtr pDst,
+ int srcX, int srcY,
+ int dstX, int dstY,
+ int w, int h)
{
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
TRACE;
if (CS_FULL(info->cs)) {
- FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix);
+ RADEONFlush2D(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
}
@@ -308,9 +300,9 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
}
if (info->accel_state->vsync)
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst,
- radeon_pick_best_crtc(pScrn, dstX, dstX + w, dstY, dstY + h),
- dstY, dstY + h);
+ RADEONWaitForVLine(pScrn, pDst,
+ radeon_pick_best_crtc(pScrn, dstX, dstX + w, dstY, dstY + h),
+ dstY, dstY + h);
BEGIN_ACCEL(3);
@@ -578,7 +570,7 @@ out:
return r;
}
-Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
+Bool RADEONDrawInit(ScreenPtr pScreen)
{
RINFO_FROM_SCREEN(pScreen);
@@ -590,16 +582,16 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
info->accel_state->exa->exa_major = EXA_VERSION_MAJOR;
info->accel_state->exa->exa_minor = EXA_VERSION_MINOR;
- info->accel_state->exa->PrepareSolid = FUNC_NAME(RADEONPrepareSolid);
- info->accel_state->exa->Solid = FUNC_NAME(RADEONSolid);
- info->accel_state->exa->DoneSolid = FUNC_NAME(RADEONDone2D);
+ info->accel_state->exa->PrepareSolid = RADEONPrepareSolid;
+ info->accel_state->exa->Solid = RADEONSolid;
+ info->accel_state->exa->DoneSolid = RADEONDone2D;
- info->accel_state->exa->PrepareCopy = FUNC_NAME(RADEONPrepareCopy);
- info->accel_state->exa->Copy = FUNC_NAME(RADEONCopy);
- info->accel_state->exa->DoneCopy = FUNC_NAME(RADEONDone2D);
+ info->accel_state->exa->PrepareCopy = RADEONPrepareCopy;
+ info->accel_state->exa->Copy = RADEONCopy;
+ info->accel_state->exa->DoneCopy = RADEONDone2D;
- info->accel_state->exa->MarkSync = FUNC_NAME(RADEONMarkSync);
- info->accel_state->exa->WaitMarker = FUNC_NAME(RADEONSync);
+ info->accel_state->exa->MarkSync = RADEONMarkSync;
+ info->accel_state->exa->WaitMarker = RADEONSync;
info->accel_state->exa->UploadToScreen = &RADEONUploadToScreenCS;
info->accel_state->exa->DownloadFromScreen = &RADEONDownloadFromScreenCS;
@@ -632,9 +624,9 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
"enabled for R300/R400/R500 type cards.\n");
info->accel_state->exa->CheckComposite = R300CheckComposite;
info->accel_state->exa->PrepareComposite =
- FUNC_NAME(R300PrepareComposite);
- info->accel_state->exa->Composite = FUNC_NAME(RadeonComposite);
- info->accel_state->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
+ R300PrepareComposite;
+ info->accel_state->exa->Composite = RadeonComposite;
+ info->accel_state->exa->DoneComposite = RadeonDoneComposite;
} else
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA Composite requires CP on R5xx/IGP\n");
} else if (IS_R200_3D) {
@@ -642,17 +634,17 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
"enabled for R200 type cards.\n");
info->accel_state->exa->CheckComposite = R200CheckComposite;
info->accel_state->exa->PrepareComposite =
- FUNC_NAME(R200PrepareComposite);
- info->accel_state->exa->Composite = FUNC_NAME(RadeonComposite);
- info->accel_state->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
+ R200PrepareComposite;
+ info->accel_state->exa->Composite = RadeonComposite;
+ info->accel_state->exa->DoneComposite = RadeonDoneComposite;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
"enabled for R100 type cards.\n");
info->accel_state->exa->CheckComposite = R100CheckComposite;
info->accel_state->exa->PrepareComposite =
- FUNC_NAME(R100PrepareComposite);
- info->accel_state->exa->Composite = FUNC_NAME(RadeonComposite);
- info->accel_state->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
+ R100PrepareComposite;
+ info->accel_state->exa->Composite = RadeonComposite;
+ info->accel_state->exa->DoneComposite = RadeonDoneComposite;
}
}
#endif
@@ -696,4 +688,3 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
return TRUE;
}
-#undef FUNC_NAME
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index aae1d8c..fcc362c 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -30,19 +30,6 @@
*
*/
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-
-#define ONLY_ONCE
-
-/* Only include the following (generic) bits once. */
-#ifdef ONLY_ONCE
-
struct blendinfo {
Bool dst_alpha;
Bool src_alpha;
@@ -362,9 +349,7 @@ static Bool R100CheckCompositeTexture(PicturePtr pPict,
return TRUE;
}
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+static Bool R100TextureSetup(PicturePtr pPict, PixmapPtr pPix,
int unit)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
@@ -480,9 +465,6 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
return TRUE;
}
-#ifdef ONLY_ONCE
-
-
static Bool R100CheckComposite(int op, PicturePtr pSrcPicture,
PicturePtr pMaskPicture, PicturePtr pDstPicture)
{
@@ -591,9 +573,7 @@ RADEONPrepareCompositeCS(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture
return TRUE;
}
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R100PrepareComposite)(int op,
+static Bool R100PrepareComposite(int op,
PicturePtr pSrcPicture,
PicturePtr pMaskPicture,
PicturePtr pDstPicture,
@@ -650,12 +630,12 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
/* switch to 3D after doing buffer space checks as the latter may flush */
RADEON_SWITCH_TO_3D();
- if (!FUNC_NAME(R100TextureSetup)(pSrcPicture, pSrc, 0))
+ if (!R100TextureSetup(pSrcPicture, pSrc, 0))
return FALSE;
pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
if (pMask != NULL) {
- if (!FUNC_NAME(R100TextureSetup)(pMaskPicture, pMask, 1))
+ if (!R100TextureSetup(pMaskPicture, pMask, 1))
return FALSE;
pp_cntl |= RADEON_TEX_1_ENABLE;
} else {
@@ -723,8 +703,6 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
return TRUE;
}
-#ifdef ONLY_ONCE
-
static Bool R200CheckCompositeTexture(PicturePtr pPict,
PicturePtr pDstPict,
int op,
@@ -768,9 +746,7 @@ static Bool R200CheckCompositeTexture(PicturePtr pPict,
return TRUE;
}
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+static Bool R200TextureSetup(PicturePtr pPict, PixmapPtr pPix,
int unit)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
@@ -886,7 +862,6 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
return TRUE;
}
-#ifdef ONLY_ONCE
static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
PicturePtr pDstPicture)
{
@@ -963,9 +938,8 @@ static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
return TRUE;
}
-#endif /* ONLY_ONCE */
-static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
+static Bool R200PrepareComposite(int op, PicturePtr pSrcPicture,
PicturePtr pMaskPicture, PicturePtr pDstPicture,
PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
{
@@ -1018,12 +992,12 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
/* switch to 3D after doing buffer space checks as it may flush */
RADEON_SWITCH_TO_3D();
- if (!FUNC_NAME(R200TextureSetup)(pSrcPicture, pSrc, 0))
+ if (!R200TextureSetup(pSrcPicture, pSrc, 0))
return FALSE;
pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
if (pMask != NULL) {
- if (!FUNC_NAME(R200TextureSetup)(pMaskPicture, pMask, 1))
+ if (!R200TextureSetup(pMaskPicture, pMask, 1))
return FALSE;
pp_cntl |= RADEON_TEX_1_ENABLE;
} else {
@@ -1101,8 +1075,6 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
return TRUE;
}
-#ifdef ONLY_ONCE
-
static Bool R300CheckCompositeTexture(PicturePtr pPict,
PicturePtr pDstPict,
int op,
@@ -1156,9 +1128,7 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict,
return TRUE;
}
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+static Bool R300TextureSetup(PicturePtr pPict, PixmapPtr pPix,
int unit)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
@@ -1363,8 +1333,6 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
return TRUE;
}
-#ifdef ONLY_ONCE
-
static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
PicturePtr pDstPicture)
{
@@ -1460,9 +1428,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
return TRUE;
}
-#endif /* ONLY_ONCE */
-static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
PicturePtr pMaskPicture, PicturePtr pDstPicture,
PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
{
@@ -1517,12 +1484,12 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
/* have to execute switch after doing buffer sizing check as the latter flushes */
RADEON_SWITCH_TO_3D();
- if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0))
+ if (!R300TextureSetup(pSrcPicture, pSrc, 0))
return FALSE;
txenable = R300_TEX_0_ENABLE;
if (pMask != NULL) {
- if (!FUNC_NAME(R300TextureSetup)(pMaskPicture, pMask, 1))
+ if (!R300TextureSetup(pMaskPicture, pMask, 1))
return FALSE;
txenable |= R300_TEX_1_ENABLE;
} else {
@@ -2132,7 +2099,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
return TRUE;
}
-static void FUNC_NAME(RadeonFinishComposite)(PixmapPtr pDst)
+static void RadeonFinishComposite(PixmapPtr pDst)
{
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
@@ -2178,13 +2145,13 @@ static void FUNC_NAME(RadeonFinishComposite)(PixmapPtr pDst)
LEAVE_DRAW(0);
}
-static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst)
+static void RadeonDoneComposite(PixmapPtr pDst)
{
ScreenPtr pScreen = pDst->drawable.pScreen;
RINFO_FROM_SCREEN(pScreen);
struct radeon_accel_state *accel_state = info->accel_state;
- FUNC_NAME(RadeonFinishComposite)(pDst);
+ RadeonFinishComposite(pDst);
if (!accel_state->src_pic->pDrawable)
pScreen->DestroyPixmap(accel_state->src_pix);
@@ -2211,7 +2178,6 @@ do { \
OUT_RING_F(_srcY); \
} while (0)
-#ifdef ONLY_ONCE
static inline void transformPoint(PictTransform *transform, xPointFixed *point)
{
PictVector v;
@@ -2222,9 +2188,8 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point)
point->x = v.vector[0];
point->y = v.vector[1];
}
-#endif
-static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
+static void RadeonCompositeTile(ScrnInfoPtr pScrn,
RADEONInfoPtr info,
PixmapPtr pDst,
int srcX, int srcY,
@@ -2242,7 +2207,7 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
if (CS_FULL(info->cs)) {
- FUNC_NAME(RadeonFinishComposite)(info->accel_state->dst_pix);
+ RadeonFinishComposite(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
info->accel_state->exa->PrepareComposite(info->accel_state->composite_op,
info->accel_state->src_pic,
@@ -2295,9 +2260,9 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
vtx_count = 4;
if (info->accel_state->vsync)
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst,
- radeon_pick_best_crtc(pScrn, dstX, dstX + w, dstY, dstY + h),
- dstY, dstY + h);
+ RADEONWaitForVLine(pScrn, pDst,
+ radeon_pick_best_crtc(pScrn, dstX, dstX + w, dstY, dstY + h),
+ dstY, dstY + h);
if (info->ChipFamily < CHIP_FAMILY_R200) {
if (!info->accel_state->draw_header) {
@@ -2399,7 +2364,7 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
#undef VTX_OUT
#undef VTX_OUT_MASK
-static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
+static void RadeonComposite(PixmapPtr pDst,
int srcX, int srcY,
int maskX, int maskY,
int dstX, int dstY,
@@ -2410,7 +2375,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
if (!info->accel_state->need_src_tile_x && !info->accel_state->need_src_tile_y) {
- FUNC_NAME(RadeonCompositeTile)(pScrn,
+ RadeonCompositeTile(pScrn,
info,
pDst,
srcX, srcY,
@@ -2446,7 +2411,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
w = remainingWidth;
remainingWidth -= w;
- FUNC_NAME(RadeonCompositeTile)(pScrn,
+ RadeonCompositeTile(pScrn,
info,
pDst,
tileSrcX, tileSrcY,
@@ -2464,5 +2429,3 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
}
}
-#undef ONLY_ONCE
-#undef FUNC_NAME
diff --git a/src/radeon_macros.h b/src/radeon_macros.h
index 25a51ce..ecc9110 100644
--- a/src/radeon_macros.h
+++ b/src/radeon_macros.h
@@ -55,27 +55,27 @@
#define BEGIN_ACCEL_RELOC(n, r) do { \
int _nqw = (n) + (r); \
- BEGIN_ACCEL(_nqw); \
+ BEGIN_RING(2*_nqw); \
} while (0)
#define EMIT_OFFSET(reg, value, pPix, rd, wd) do { \
driver_priv = exaGetPixmapDriverPrivate(pPix); \
- OUT_ACCEL_REG((reg), (value)); \
- OUT_RELOC(driver_priv->bo, (rd), (wd)); \
+ OUT_RING_REG((reg), (value)); \
+ OUT_RING_RELOC(driver_priv->bo, (rd), (wd)); \
} while(0)
#define EMIT_READ_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, (RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT), 0)
#define EMIT_WRITE_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, 0, RADEON_GEM_DOMAIN_VRAM)
#define OUT_TEXTURE_REG(reg, offset, bo) do { \
- OUT_ACCEL_REG((reg), (offset)); \
- OUT_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \
+ OUT_RING_REG((reg), (offset)); \
+ OUT_RING_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \
} while(0)
#define EMIT_COLORPITCH(reg, value, pPix) do { \
driver_priv = exaGetPixmapDriverPrivate(pPix); \
- OUT_ACCEL_REG((reg), value); \
- OUT_RELOC(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); \
+ OUT_RING_REG((reg), value); \
+ OUT_RING_RELOC(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); \
}while(0)
#endif
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index a7402aa..06fda09 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -123,19 +123,12 @@ static REF_TRANSFORM trans[2] =
};
-#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
-#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
-#define OUT_ACCEL_REG_F(reg, val) OUT_ACCEL_REG(reg, F_TO_DW(val))
-#define FINISH_ACCEL() ADVANCE_RING()
+#define OUT_ACCEL_REG_F(reg, val) OUT_RING_REG(reg, F_TO_DW(val))
#define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
-#define OUT_RELOC(x, read, write) OUT_RING_RELOC(x, read, write)
#include "radeon_textured_videofuncs.c"
-#undef BEGIN_ACCEL
-#undef OUT_ACCEL_REG
#undef OUT_ACCEL_REG_F
-#undef FINISH_ACCEL
#undef OUT_RING_F
static void
@@ -402,13 +395,13 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
else if (IS_R600_3D)
R600DisplayTexturedVideo(pScrn, pPriv);
else if (IS_R500_3D)
- R500DisplayTexturedVideoCP(pScrn, pPriv);
+ R500DisplayTexturedVideo(pScrn, pPriv);
else if (IS_R300_3D)
- R300DisplayTexturedVideoCP(pScrn, pPriv);
+ R300DisplayTexturedVideo(pScrn, pPriv);
else if (IS_R200_3D)
- R200DisplayTexturedVideoCP(pScrn, pPriv);
+ R200DisplayTexturedVideo(pScrn, pPriv);
else
- RADEONDisplayTexturedVideoCP(pScrn, pPriv);
+ RADEONDisplayTexturedVideo(pScrn, pPriv);
}
return Success;
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 815448c..0580848 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -25,15 +25,6 @@
*
*/
-
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-
#define VTX_OUT_6(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
do { \
OUT_RING_F(_dstX); \
@@ -54,7 +45,7 @@ do { \
static Bool
-FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+RADEONPrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
@@ -125,13 +116,13 @@ FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
BEGIN_ACCEL_RELOC(4,2);
- OUT_ACCEL_REG(RADEON_RB3D_CNTL, dst_format);
+ OUT_RING_REG(RADEON_RB3D_CNTL, dst_format);
EMIT_WRITE_OFFSET(RADEON_RB3D_COLOROFFSET, 0, pPixmap);
EMIT_COLORPITCH(RADEON_RB3D_COLORPITCH, colorpitch, pPixmap);
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
+ OUT_RING_REG(RADEON_RB3D_BLENDCNTL,
RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
- FINISH_ACCEL();
+ ADVANCE_RING();
if (pPriv->is_planar) {
/* need 2 texcoord sets (even though they are identical) due
@@ -146,134 +137,134 @@ FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
BEGIN_ACCEL_RELOC(23, 3);
- OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
+ OUT_RING_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
RADEON_SE_VTX_FMT_ST0 |
RADEON_SE_VTX_FMT_ST1));
- OUT_ACCEL_REG(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE |
+ OUT_RING_REG(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE |
RADEON_TEX_1_ENABLE | RADEON_TEX_BLEND_1_ENABLE |
RADEON_TEX_2_ENABLE | RADEON_TEX_BLEND_2_ENABLE |
RADEON_PLANAR_YUV_ENABLE));
/* Y */
- OUT_ACCEL_REG(RADEON_PP_TXFILTER_0,
+ OUT_RING_REG(RADEON_PP_TXFILTER_0,
RADEON_MAG_FILTER_LINEAR |
RADEON_MIN_FILTER_LINEAR |
RADEON_CLAMP_S_CLAMP_LAST |
RADEON_CLAMP_T_CLAMP_LAST |
RADEON_YUV_TO_RGB);
- OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0);
+ OUT_RING_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0);
OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, txoffset, src_bo);
- OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0,
+ OUT_RING_REG(RADEON_PP_TXCBLEND_0,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
RADEON_COLOR_ARG_C_T0_COLOR |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_ACCEL_REG(RADEON_PP_TXABLEND_0,
+ OUT_RING_REG(RADEON_PP_TXABLEND_0,
RADEON_ALPHA_ARG_A_ZERO |
RADEON_ALPHA_ARG_B_ZERO |
RADEON_ALPHA_ARG_C_T0_ALPHA |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0,
+ OUT_RING_REG(RADEON_PP_TEX_SIZE_0,
(pPriv->w - 1) |
((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0,
+ OUT_RING_REG(RADEON_PP_TEX_PITCH_0,
pPriv->src_pitch - 32);
/* U */
- OUT_ACCEL_REG(RADEON_PP_TXFILTER_1,
+ OUT_RING_REG(RADEON_PP_TXFILTER_1,
RADEON_MAG_FILTER_LINEAR |
RADEON_MIN_FILTER_LINEAR |
RADEON_CLAMP_S_CLAMP_LAST |
RADEON_CLAMP_T_CLAMP_LAST);
- OUT_ACCEL_REG(RADEON_PP_TXFORMAT_1, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ1);
+ OUT_RING_REG(RADEON_PP_TXFORMAT_1, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ1);
OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_1, txoffset + pPriv->planeu_offset, src_bo);
- OUT_ACCEL_REG(RADEON_PP_TXCBLEND_1,
+ OUT_RING_REG(RADEON_PP_TXCBLEND_1,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
RADEON_COLOR_ARG_C_T0_COLOR |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_ACCEL_REG(RADEON_PP_TXABLEND_1,
+ OUT_RING_REG(RADEON_PP_TXABLEND_1,
RADEON_ALPHA_ARG_A_ZERO |
RADEON_ALPHA_ARG_B_ZERO |
RADEON_ALPHA_ARG_C_T0_ALPHA |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_1, txsize);
- OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_1, txpitch);
+ OUT_RING_REG(RADEON_PP_TEX_SIZE_1, txsize);
+ OUT_RING_REG(RADEON_PP_TEX_PITCH_1, txpitch);
/* V */
- OUT_ACCEL_REG(RADEON_PP_TXFILTER_2,
+ OUT_RING_REG(RADEON_PP_TXFILTER_2,
RADEON_MAG_FILTER_LINEAR |
RADEON_MIN_FILTER_LINEAR |
RADEON_CLAMP_S_CLAMP_LAST |
RADEON_CLAMP_T_CLAMP_LAST);
- OUT_ACCEL_REG(RADEON_PP_TXFORMAT_2, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ1);
+ OUT_RING_REG(RADEON_PP_TXFORMAT_2, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ1);
OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_2, txoffset + pPriv->planev_offset, src_bo);
- OUT_ACCEL_REG(RADEON_PP_TXCBLEND_2,
+ OUT_RING_REG(RADEON_PP_TXCBLEND_2,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
RADEON_COLOR_ARG_C_T0_COLOR |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_ACCEL_REG(RADEON_PP_TXABLEND_2,
+ OUT_RING_REG(RADEON_PP_TXABLEND_2,
RADEON_ALPHA_ARG_A_ZERO |
RADEON_ALPHA_ARG_B_ZERO |
RADEON_ALPHA_ARG_C_T0_ALPHA |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_2, txsize);
- OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_2, txpitch);
- FINISH_ACCEL();
+ OUT_RING_REG(RADEON_PP_TEX_SIZE_2, txsize);
+ OUT_RING_REG(RADEON_PP_TEX_PITCH_2, txpitch);
+ ADVANCE_RING();
} else {
pPriv->vtx_count = 4;
BEGIN_ACCEL_RELOC(9, 1);
- OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
+ OUT_RING_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
RADEON_SE_VTX_FMT_ST0));
- OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
+ OUT_RING_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
- OUT_ACCEL_REG(RADEON_PP_TXFILTER_0,
+ OUT_RING_REG(RADEON_PP_TXFILTER_0,
RADEON_MAG_FILTER_LINEAR |
RADEON_MIN_FILTER_LINEAR |
RADEON_CLAMP_S_CLAMP_LAST |
RADEON_CLAMP_T_CLAMP_LAST |
RADEON_YUV_TO_RGB);
- OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0);
+ OUT_RING_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0);
OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, txoffset, src_bo);
- OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0,
+ OUT_RING_REG(RADEON_PP_TXCBLEND_0,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
RADEON_COLOR_ARG_C_T0_COLOR |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_ACCEL_REG(RADEON_PP_TXABLEND_0,
+ OUT_RING_REG(RADEON_PP_TXABLEND_0,
RADEON_ALPHA_ARG_A_ZERO |
RADEON_ALPHA_ARG_B_ZERO |
RADEON_ALPHA_ARG_C_T0_ALPHA |
RADEON_BLEND_CTL_ADD |
RADEON_CLAMP_TX);
- OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0,
+ OUT_RING_REG(RADEON_PP_TEX_SIZE_0,
(pPriv->w - 1) |
((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0,
+ OUT_RING_REG(RADEON_PP_TEX_PITCH_0,
pPriv->src_pitch - 32);
- FINISH_ACCEL();
+ ADVANCE_RING();
}
- BEGIN_ACCEL(2);
- OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
- OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, ((scissor_w << RADEON_RE_WIDTH_SHIFT) |
+ BEGIN_RING(2*2);
+ OUT_RING_REG(RADEON_RE_TOP_LEFT, 0);
+ OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, ((scissor_w << RADEON_RE_WIDTH_SHIFT) |
(scissor_h << RADEON_RE_HEIGHT_SHIFT)));
- FINISH_ACCEL();
+ ADVANCE_RING();
if (pPriv->vsync) {
xf86CrtcPtr crtc;
@@ -286,17 +277,17 @@ FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
if (crtc)
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
- crtc,
- pPriv->drw_y - crtc->y,
- (pPriv->drw_y - crtc->y) + pPriv->dst_h);
+ RADEONWaitForVLine(pScrn, pPixmap,
+ crtc,
+ pPriv->drw_y - crtc->y,
+ (pPriv->drw_y - crtc->y) + pPriv->dst_h);
}
return TRUE;
}
static void
-FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+RADEONDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
@@ -312,7 +303,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
dstyoff = 0;
#endif
- if (!FUNC_NAME(RADEONPrepareTexturedVideo)(pScrn, pPriv))
+ if (!RADEONPrepareTexturedVideo(pScrn, pPriv))
return;
/*
@@ -340,7 +331,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (draw_size > radeon_cs_space_remaining(pScrn)) {
radeon_cs_flush_indirect(pScrn);
- if (!FUNC_NAME(RADEONPrepareTexturedVideo)(pScrn, pPriv))
+ if (!RADEONPrepareTexturedVideo(pScrn, pPriv))
return;
}
loop_boxes = MIN(radeon_cs_space_remaining(pScrn) / draw_size, nBox);
@@ -409,14 +400,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
pBox++;
}
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+ OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
ADVANCE_RING();
}
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
}
static Bool
-FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+R200PrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
@@ -496,14 +487,14 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
BEGIN_ACCEL_RELOC(4,2);
- OUT_ACCEL_REG(RADEON_RB3D_CNTL, dst_format);
+ OUT_RING_REG(RADEON_RB3D_CNTL, dst_format);
EMIT_WRITE_OFFSET(RADEON_RB3D_COLOROFFSET, 0, pPixmap);
EMIT_COLORPITCH(RADEON_RB3D_COLORPITCH, colorpitch, pPixmap);
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
+ OUT_RING_REG(RADEON_RB3D_BLENDCNTL,
RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
- FINISH_ACCEL();
+ ADVANCE_RING();
txfilter = R200_MAG_FILTER_LINEAR |
R200_MIN_FILTER_LINEAR |
@@ -556,38 +547,38 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
BEGIN_ACCEL_RELOC(36, 3);
- OUT_ACCEL_REG(RADEON_PP_CNTL,
+ OUT_RING_REG(RADEON_PP_CNTL,
RADEON_TEX_0_ENABLE | RADEON_TEX_1_ENABLE | RADEON_TEX_2_ENABLE |
RADEON_TEX_BLEND_0_ENABLE |
RADEON_TEX_BLEND_1_ENABLE |
RADEON_TEX_BLEND_2_ENABLE);
- OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
- OUT_ACCEL_REG(R200_SE_VTX_FMT_1,
+ OUT_RING_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
+ OUT_RING_REG(R200_SE_VTX_FMT_1,
(2 << R200_VTX_TEX0_COMP_CNT_SHIFT) |
(2 << R200_VTX_TEX1_COMP_CNT_SHIFT));
- OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
- OUT_ACCEL_REG(R200_PP_TXSIZE_0,
+ OUT_RING_REG(R200_PP_TXFILTER_0, txfilter);
+ OUT_RING_REG(R200_PP_TXFORMAT_0, txformat);
+ OUT_RING_REG(R200_PP_TXFORMAT_X_0, 0);
+ OUT_RING_REG(R200_PP_TXSIZE_0,
(pPriv->w - 1) |
((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
+ OUT_RING_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, src_bo);
- OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat | R200_TXFORMAT_ST_ROUTE_STQ1);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_X_1, 0);
- OUT_ACCEL_REG(R200_PP_TXSIZE_1, txsize);
- OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch);
+ OUT_RING_REG(R200_PP_TXFILTER_1, txfilter);
+ OUT_RING_REG(R200_PP_TXFORMAT_1, txformat | R200_TXFORMAT_ST_ROUTE_STQ1);
+ OUT_RING_REG(R200_PP_TXFORMAT_X_1, 0);
+ OUT_RING_REG(R200_PP_TXSIZE_1, txsize);
+ OUT_RING_REG(R200_PP_TXPITCH_1, txpitch);
OUT_TEXTURE_REG(R200_PP_TXOFFSET_1, txoffset + pPriv->planeu_offset, src_bo);
- OUT_ACCEL_REG(R200_PP_TXFILTER_2, txfilter);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_2, txformat | R200_TXFORMAT_ST_ROUTE_STQ1);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_X_2, 0);
- OUT_ACCEL_REG(R200_PP_TXSIZE_2, txsize);
- OUT_ACCEL_REG(R200_PP_TXPITCH_2, txpitch);
+ OUT_RING_REG(R200_PP_TXFILTER_2, txfilter);
+ OUT_RING_REG(R200_PP_TXFORMAT_2, txformat | R200_TXFORMAT_ST_ROUTE_STQ1);
+ OUT_RING_REG(R200_PP_TXFORMAT_X_2, 0);
+ OUT_RING_REG(R200_PP_TXSIZE_2, txsize);
+ OUT_RING_REG(R200_PP_TXPITCH_2, txpitch);
OUT_TEXTURE_REG(R200_PP_TXOFFSET_2, txoffset + pPriv->planev_offset, src_bo);
/* similar to r300 code. Note the big problem is that hardware constants
@@ -632,26 +623,26 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
*/
/* MAD temp0 / 2, const0.a * 2, temp0, -const0.rgb */
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
+ OUT_RING_REG(R200_PP_TXCBLEND_0,
R200_TXC_ARG_A_TFACTOR_COLOR |
R200_TXC_ARG_B_R0_COLOR |
R200_TXC_ARG_C_TFACTOR_COLOR |
(yoff < 0 ? R200_TXC_NEG_ARG_C : 0) |
R200_TXC_OP_DOT2_ADD);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
+ OUT_RING_REG(R200_PP_TXCBLEND2_0,
(0 << R200_TXC_TFACTOR_SEL_SHIFT) |
R200_TXC_SCALE_INV2 |
R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_0,
+ OUT_RING_REG(R200_PP_TXABLEND_0,
R200_TXA_ARG_A_ZERO |
R200_TXA_ARG_B_ZERO |
R200_TXA_ARG_C_ZERO |
R200_TXA_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_0,
+ OUT_RING_REG(R200_PP_TXABLEND2_0,
R200_TXA_OUTPUT_REG_NONE);
/* MAD temp0, (const1 - 0.5) * 2, (temp1 - 0.5) * 2, temp0 */
- OUT_ACCEL_REG(R200_PP_TXCBLEND_1,
+ OUT_RING_REG(R200_PP_TXCBLEND_1,
R200_TXC_ARG_A_TFACTOR_COLOR |
R200_TXC_BIAS_ARG_A |
R200_TXC_SCALE_ARG_A |
@@ -660,19 +651,19 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
(needux8 ? R200_TXC_SCALE_ARG_B : 0) |
R200_TXC_ARG_C_R0_COLOR |
R200_TXC_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_1,
+ OUT_RING_REG(R200_PP_TXCBLEND2_1,
(1 << R200_TXC_TFACTOR_SEL_SHIFT) |
R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_1,
+ OUT_RING_REG(R200_PP_TXABLEND_1,
R200_TXA_ARG_A_ZERO |
R200_TXA_ARG_B_ZERO |
R200_TXA_ARG_C_ZERO |
R200_TXA_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_1,
+ OUT_RING_REG(R200_PP_TXABLEND2_1,
R200_TXA_OUTPUT_REG_NONE);
/* MAD temp0 x 2, (const2 - 0.5) * 2, (temp2 - 0.5), temp0 */
- OUT_ACCEL_REG(R200_PP_TXCBLEND_2,
+ OUT_RING_REG(R200_PP_TXCBLEND_2,
R200_TXC_ARG_A_TFACTOR_COLOR |
R200_TXC_BIAS_ARG_A |
R200_TXC_SCALE_ARG_A |
@@ -681,79 +672,79 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
(needvx8 ? R200_TXC_SCALE_ARG_B : 0) |
R200_TXC_ARG_C_R0_COLOR |
R200_TXC_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_2,
+ OUT_RING_REG(R200_PP_TXCBLEND2_2,
(2 << R200_TXC_TFACTOR_SEL_SHIFT) |
R200_TXC_SCALE_2X |
R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_2,
+ OUT_RING_REG(R200_PP_TXABLEND_2,
R200_TXA_ARG_A_ZERO |
R200_TXA_ARG_B_ZERO |
R200_TXA_ARG_C_ZERO |
R200_TXA_COMP_ARG_C |
R200_TXA_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_2,
+ OUT_RING_REG(R200_PP_TXABLEND2_2,
R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
/* shader constants */
- OUT_ACCEL_REG(R200_PP_TFACTOR_0, float4touint(yco > 1.0 ? 1.0 : 0.0, /* range special [0, 2] */
+ OUT_RING_REG(R200_PP_TFACTOR_0, float4touint(yco > 1.0 ? 1.0 : 0.0, /* range special [0, 2] */
yco > 1.0 ? yco - 1.0: yco,
yoff < 0 ? -yoff : yoff, /* range special [-1, 1] */
0.0));
- OUT_ACCEL_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * ucscale + 0.5, /* range [-4, 4] */
+ OUT_RING_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * ucscale + 0.5, /* range [-4, 4] */
uco[1] * ucscale + 0.5, /* or [-2, 2] */
uco[2] * ucscale + 0.5,
0.0));
- OUT_ACCEL_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * vcscale + 0.5, /* range [-2, 2] */
+ OUT_RING_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * vcscale + 0.5, /* range [-2, 2] */
vco[1] * vcscale + 0.5, /* or [-4, 4] */
vco[2] * vcscale + 0.5,
0.0));
- FINISH_ACCEL();
+ ADVANCE_RING();
} else {
pPriv->vtx_count = 4;
BEGIN_ACCEL_RELOC(24, 1);
- OUT_ACCEL_REG(RADEON_PP_CNTL,
+ OUT_RING_REG(RADEON_PP_CNTL,
RADEON_TEX_0_ENABLE |
RADEON_TEX_BLEND_0_ENABLE | RADEON_TEX_BLEND_1_ENABLE |
RADEON_TEX_BLEND_2_ENABLE);
- OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
- OUT_ACCEL_REG(R200_SE_VTX_FMT_1,
+ OUT_RING_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
+ OUT_RING_REG(R200_SE_VTX_FMT_1,
(2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
- OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
- OUT_ACCEL_REG(R200_PP_TXSIZE_0,
+ OUT_RING_REG(R200_PP_TXFILTER_0, txfilter);
+ OUT_RING_REG(R200_PP_TXFORMAT_0, txformat);
+ OUT_RING_REG(R200_PP_TXFORMAT_X_0, 0);
+ OUT_RING_REG(R200_PP_TXSIZE_0,
(pPriv->w - 1) |
((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
+ OUT_RING_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, src_bo);
/* MAD temp1 / 2, const0.a * 2, temp0.ggg, -const0.rgb */
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
+ OUT_RING_REG(R200_PP_TXCBLEND_0,
R200_TXC_ARG_A_TFACTOR_COLOR |
R200_TXC_ARG_B_R0_COLOR |
R200_TXC_ARG_C_TFACTOR_COLOR |
(yoff < 0 ? R200_TXC_NEG_ARG_C : 0) |
R200_TXC_OP_DOT2_ADD);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
+ OUT_RING_REG(R200_PP_TXCBLEND2_0,
(0 << R200_TXC_TFACTOR_SEL_SHIFT) |
R200_TXC_SCALE_INV2 |
(R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_B_SHIFT) |
R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R1);
- OUT_ACCEL_REG(R200_PP_TXABLEND_0,
+ OUT_RING_REG(R200_PP_TXABLEND_0,
R200_TXA_ARG_A_ZERO |
R200_TXA_ARG_B_ZERO |
R200_TXA_ARG_C_ZERO |
R200_TXA_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_0,
+ OUT_RING_REG(R200_PP_TXABLEND2_0,
R200_TXA_OUTPUT_REG_NONE);
/* MAD temp1, (const1 - 0.5) * 2, (temp0.rrr - 0.5) * 2, temp1 */
- OUT_ACCEL_REG(R200_PP_TXCBLEND_1,
+ OUT_RING_REG(R200_PP_TXCBLEND_1,
R200_TXC_ARG_A_TFACTOR_COLOR |
R200_TXC_BIAS_ARG_A |
R200_TXC_SCALE_ARG_A |
@@ -762,20 +753,20 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
(needux8 ? R200_TXC_SCALE_ARG_B : 0) |
R200_TXC_ARG_C_R1_COLOR |
R200_TXC_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_1,
+ OUT_RING_REG(R200_PP_TXCBLEND2_1,
(1 << R200_TXC_TFACTOR_SEL_SHIFT) |
(R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_B_SHIFT) |
R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R1);
- OUT_ACCEL_REG(R200_PP_TXABLEND_1,
+ OUT_RING_REG(R200_PP_TXABLEND_1,
R200_TXA_ARG_A_ZERO |
R200_TXA_ARG_B_ZERO |
R200_TXA_ARG_C_ZERO |
R200_TXA_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_1,
+ OUT_RING_REG(R200_PP_TXABLEND2_1,
R200_TXA_OUTPUT_REG_NONE);
/* MAD temp0 x 2, (const2 - 0.5) * 2, (temp0.bbb - 0.5), temp1 */
- OUT_ACCEL_REG(R200_PP_TXCBLEND_2,
+ OUT_RING_REG(R200_PP_TXCBLEND_2,
R200_TXC_ARG_A_TFACTOR_COLOR |
R200_TXC_BIAS_ARG_A |
R200_TXC_SCALE_ARG_A |
@@ -784,42 +775,42 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
(needvx8 ? R200_TXC_SCALE_ARG_B : 0) |
R200_TXC_ARG_C_R1_COLOR |
R200_TXC_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_2,
+ OUT_RING_REG(R200_PP_TXCBLEND2_2,
(2 << R200_TXC_TFACTOR_SEL_SHIFT) |
R200_TXC_SCALE_2X |
(R200_TXC_REPL_RED << R200_TXC_REPL_ARG_B_SHIFT) |
R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_2,
+ OUT_RING_REG(R200_PP_TXABLEND_2,
R200_TXA_ARG_A_ZERO |
R200_TXA_ARG_B_ZERO |
R200_TXA_ARG_C_ZERO |
R200_TXA_COMP_ARG_C |
R200_TXA_OP_MADD);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_2,
+ OUT_RING_REG(R200_PP_TXABLEND2_2,
R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
/* shader constants */
- OUT_ACCEL_REG(R200_PP_TFACTOR_0, float4touint(yco > 1.0 ? 1.0 : 0.0, /* range special [0, 2] */
+ OUT_RING_REG(R200_PP_TFACTOR_0, float4touint(yco > 1.0 ? 1.0 : 0.0, /* range special [0, 2] */
yco > 1.0 ? yco - 1.0: yco,
yoff < 0 ? -yoff : yoff, /* range special [-1, 1] */
0.0));
- OUT_ACCEL_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * ucscale + 0.5, /* range [-4, 4] */
+ OUT_RING_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * ucscale + 0.5, /* range [-4, 4] */
uco[1] * ucscale + 0.5, /* or [-2, 2] */
uco[2] * ucscale + 0.5,
0.0));
- OUT_ACCEL_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * vcscale + 0.5, /* range [-2, 2] */
+ OUT_RING_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * vcscale + 0.5, /* range [-2, 2] */
vco[1] * vcscale + 0.5, /* or [-4, 4] */
vco[2] * vcscale + 0.5,
0.0));
- FINISH_ACCEL();
+ ADVANCE_RING();
}
- BEGIN_ACCEL(2);
- OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
- OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, ((scissor_w << RADEON_RE_WIDTH_SHIFT) |
+ BEGIN_RING(2*2);
+ OUT_RING_REG(RADEON_RE_TOP_LEFT, 0);
+ OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, ((scissor_w << RADEON_RE_WIDTH_SHIFT) |
(scissor_h << RADEON_RE_HEIGHT_SHIFT)));
- FINISH_ACCEL();
+ ADVANCE_RING();
if (pPriv->vsync) {
xf86CrtcPtr crtc;
@@ -832,17 +823,17 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
if (crtc)
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
- crtc,
- pPriv->drw_y - crtc->y,
- (pPriv->drw_y - crtc->y) + pPriv->dst_h);
+ RADEONWaitForVLine(pScrn, pPixmap,
+ crtc,
+ pPriv->drw_y - crtc->y,
+ (pPriv->drw_y - crtc->y) + pPriv->dst_h);
}
return TRUE;
}
static void
-FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+R200DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
@@ -858,7 +849,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
dstyoff = 0;
#endif
- if (!FUNC_NAME(R200PrepareTexturedVideo)(pScrn, pPriv))
+ if (!R200PrepareTexturedVideo(pScrn, pPriv))
return;
/*
@@ -887,7 +878,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
if (draw_size > radeon_cs_space_remaining(pScrn)) {
radeon_cs_flush_indirect(pScrn);
- if (!FUNC_NAME(R200PrepareTexturedVideo)(pScrn, pPriv))
+ if (!R200PrepareTexturedVideo(pScrn, pPriv))
return;
}
loop_boxes = MIN(radeon_cs_space_remaining(pScrn) / draw_size, nBox);
@@ -946,7 +937,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pBox++;
}
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+ OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
ADVANCE_RING();
}
@@ -954,7 +945,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
}
static Bool
-FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+R300PrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
@@ -1055,16 +1046,16 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
txoffset = 0;
BEGIN_ACCEL_RELOC(6, 1);
- OUT_ACCEL_REG(R300_TX_FILTER0_0, txfilter);
- OUT_ACCEL_REG(R300_TX_FILTER1_0, 0);
- OUT_ACCEL_REG(R300_TX_FORMAT0_0, txformat0);
+ OUT_RING_REG(R300_TX_FILTER0_0, txfilter);
+ OUT_RING_REG(R300_TX_FILTER1_0, 0);
+ OUT_RING_REG(R300_TX_FORMAT0_0, txformat0);
if (pPriv->is_planar)
- OUT_ACCEL_REG(R300_TX_FORMAT1_0, txformat1 | R300_TX_FORMAT_CACHE_HALF_REGION_0);
+ OUT_RING_REG(R300_TX_FORMAT1_0, txformat1 | R300_TX_FORMAT_CACHE_HALF_REGION_0);
else
- OUT_ACCEL_REG(R300_TX_FORMAT1_0, txformat1);
- OUT_ACCEL_REG(R300_TX_FORMAT2_0, txpitch);
+ OUT_RING_REG(R300_TX_FORMAT1_0, txformat1);
+ OUT_RING_REG(R300_TX_FORMAT2_0, txpitch);
OUT_TEXTURE_REG(R300_TX_OFFSET_0, txoffset, src_bo);
- FINISH_ACCEL();
+ ADVANCE_RING();
txenable = R300_TEX_0_ENABLE;
@@ -1080,19 +1071,19 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_TX_MAG_FILTER_LINEAR);
BEGIN_ACCEL_RELOC(12, 2);
- OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT));
- OUT_ACCEL_REG(R300_TX_FILTER1_1, 0);
- OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0);
- OUT_ACCEL_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_2);
- OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch);
+ OUT_RING_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT));
+ OUT_RING_REG(R300_TX_FILTER1_1, 0);
+ OUT_RING_REG(R300_TX_FORMAT0_1, txformat0);
+ OUT_RING_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_2);
+ OUT_RING_REG(R300_TX_FORMAT2_1, txpitch);
OUT_TEXTURE_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset, src_bo);
- OUT_ACCEL_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT));
- OUT_ACCEL_REG(R300_TX_FILTER1_2, 0);
- OUT_ACCEL_REG(R300_TX_FORMAT0_2, txformat0);
- OUT_ACCEL_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_3);
- OUT_ACCEL_REG(R300_TX_FORMAT2_2, txpitch);
+ OUT_RING_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT));
+ OUT_RING_REG(R300_TX_FILTER1_2, 0);
+ OUT_RING_REG(R300_TX_FORMAT0_2, txformat0);
+ OUT_RING_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_3);
+ OUT_RING_REG(R300_TX_FORMAT2_2, txpitch);
OUT_TEXTURE_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset, src_bo);
- FINISH_ACCEL();
+ ADVANCE_RING();
txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE;
}
@@ -1115,13 +1106,13 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
bicubic_offset = 0;
BEGIN_ACCEL_RELOC(6, 1);
- OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter);
- OUT_ACCEL_REG(R300_TX_FILTER1_1, 0);
- OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0);
- OUT_ACCEL_REG(R300_TX_FORMAT1_1, txformat1);
- OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch);
+ OUT_RING_REG(R300_TX_FILTER0_1, txfilter);
+ OUT_RING_REG(R300_TX_FILTER1_1, 0);
+ OUT_RING_REG(R300_TX_FORMAT0_1, txformat0);
+ OUT_RING_REG(R300_TX_FORMAT1_1, txformat1);
+ OUT_RING_REG(R300_TX_FORMAT2_1, txpitch);
OUT_TEXTURE_REG(R300_TX_OFFSET_1, bicubic_offset, info->bicubic_bo);
- FINISH_ACCEL();
+ ADVANCE_RING();
/* Enable tex 1 */
txenable |= R300_TEX_1_ENABLE;
@@ -1130,14 +1121,14 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* setup the VAP */
if (info->accel_state->has_tcl) {
if (pPriv->bicubic_enabled)
- BEGIN_ACCEL(7);
+ BEGIN_RING(2*7);
else
- BEGIN_ACCEL(6);
+ BEGIN_RING(2*6);
} else {
if (pPriv->bicubic_enabled)
- BEGIN_ACCEL(5);
+ BEGIN_RING(2*5);
else
- BEGIN_ACCEL(4);
+ BEGIN_RING(2*4);
}
/* These registers define the number, type, and location of data submitted
@@ -1154,7 +1145,7 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
* Fog
*/
if (pPriv->bicubic_enabled) {
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
(0 << R300_SKIP_DWORDS_0_SHIFT) |
(0 << R300_DST_VEC_LOC_0_SHIFT) |
@@ -1163,14 +1154,14 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
(0 << R300_SKIP_DWORDS_1_SHIFT) |
(6 << R300_DST_VEC_LOC_1_SHIFT) |
R300_SIGNED_1));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
+ OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_1,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
(0 << R300_SKIP_DWORDS_2_SHIFT) |
(7 << R300_DST_VEC_LOC_2_SHIFT) |
R300_LAST_VEC_2 |
R300_SIGNED_2));
} else {
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
(0 << R300_SKIP_DWORDS_0_SHIFT) |
(0 << R300_DST_VEC_LOC_0_SHIFT) |
@@ -1191,69 +1182,69 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
*/
if (info->accel_state->has_tcl) {
if (pPriv->bicubic_enabled) {
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0,
((11 << R300_PVS_FIRST_INST_SHIFT) |
(13 << R300_PVS_XYZW_VALID_INST_SHIFT) |
(13 << R300_PVS_LAST_INST_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1,
(13 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
} else {
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0,
((9 << R300_PVS_FIRST_INST_SHIFT) |
(10 << R300_PVS_XYZW_VALID_INST_SHIFT) |
(10 << R300_PVS_LAST_INST_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1,
(10 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
}
}
/* Position and one set of 2 texture coordinates */
- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
+ OUT_RING_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
if (pPriv->bicubic_enabled)
- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
+ OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
(2 << R300_TEX_1_COMP_CNT_SHIFT)));
else
- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
+ OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
- OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
- FINISH_ACCEL();
+ OUT_RING_REG(R300_US_OUT_FMT_0, output_fmt);
+ ADVANCE_RING();
/* setup pixel shader */
if (pPriv->bicubic_state != BICUBIC_OFF) {
if (pPriv->bicubic_enabled) {
- BEGIN_ACCEL(79);
+ BEGIN_RING(2*79);
/* 4 components: 2 for tex0 and 2 for tex1 */
- OUT_ACCEL_REG(R300_RS_COUNT, ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ OUT_RING_REG(R300_RS_COUNT, ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1));
+ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1));
/* Pixel stack frame size. */
- OUT_ACCEL_REG(R300_US_PIXSIZE, 5);
+ OUT_RING_REG(R300_US_PIXSIZE, 5);
/* Indirection levels */
- OUT_ACCEL_REG(R300_US_CONFIG, ((2 << R300_NLEVEL_SHIFT) |
+ OUT_RING_REG(R300_US_CONFIG, ((2 << R300_NLEVEL_SHIFT) |
R300_FIRST_TEX));
/* Set nodes. */
- OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(14) |
R300_TEX_CODE_OFFSET(0) |
R300_TEX_CODE_SIZE(6)));
/* Nodes are allocated highest first, but executed lowest first */
- OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0);
- OUT_ACCEL_REG(R300_US_CODE_ADDR_1, (R300_ALU_START(0) |
+ OUT_RING_REG(R300_US_CODE_ADDR_0, 0);
+ OUT_RING_REG(R300_US_CODE_ADDR_1, (R300_ALU_START(0) |
R300_ALU_SIZE(0) |
R300_TEX_START(0) |
R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_2, (R300_ALU_START(1) |
+ OUT_RING_REG(R300_US_CODE_ADDR_2, (R300_ALU_START(1) |
R300_ALU_SIZE(9) |
R300_TEX_START(1) |
R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(11) |
+ OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(11) |
R300_ALU_SIZE(2) |
R300_TEX_START(2) |
R300_TEX_SIZE(3) |
@@ -1266,221 +1257,221 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
// first node
/* TEX temp2, temp1.rrr0, tex1, 1D */
- OUT_ACCEL_REG(R300_US_TEX_INST(0), (R300_TEX_INST(R300_TEX_INST_LD) |
+ OUT_RING_REG(R300_US_TEX_INST(0), (R300_TEX_INST(R300_TEX_INST_LD) |
R300_TEX_ID(1) |
R300_TEX_SRC_ADDR(1) |
R300_TEX_DST_ADDR(2)));
/* MOV temp1.r, temp1.ggg0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(1) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(1) |
R300_ALU_RGB_ADDRD(1) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDRD(1) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDRD(1) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
// second node
/* TEX temp1, temp1, tex1, 1D */
- OUT_ACCEL_REG(R300_US_TEX_INST(1), (R300_TEX_INST(R300_TEX_INST_LD) |
+ OUT_RING_REG(R300_US_TEX_INST(1), (R300_TEX_INST(R300_TEX_INST_LD) |
R300_TEX_ID(1) |
R300_TEX_SRC_ADDR(1) |
R300_TEX_DST_ADDR(1)));
/* MUL temp3.rg, temp2.ggg0, const0.rgb0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(2) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(2) |
R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) |
R300_ALU_RGB_ADDRD(3) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(3) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(3) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
/* MUL temp2.rg, temp2.rrr0, const0.rgb */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(2) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(2) |
R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) |
R300_ALU_RGB_ADDRD(2) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(2) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
/* MAD temp4.rg, temp1.ggg0, const1.rgb, temp3.rgb0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(3), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(3), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(1) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(1) |
R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
R300_ALU_RGB_ADDR2(3) |
R300_ALU_RGB_ADDRD(4) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(4) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(4) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
/* MAD temp5.rg, temp1.ggg0, const1.rgb, temp2.rgb0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(4), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(4), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(1) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(1) |
R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
R300_ALU_RGB_ADDR2(2) |
R300_ALU_RGB_ADDRD(5) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(5) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(5) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
/* MAD temp3.rg, temp1.rrr0, const1.rgb, temp3.rgb0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(5), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(5), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(1) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(1) |
R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
R300_ALU_RGB_ADDR2(3) |
R300_ALU_RGB_ADDRD(3) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(3) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(3) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
/* MAD temp1.rg, temp1.rrr0, const1.rgb, temp2.rgb0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(1) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(1) |
R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
R300_ALU_RGB_ADDR2(2) |
R300_ALU_RGB_ADDRD(1) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(1) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(1) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
/* ADD temp1.rg, temp0.rgb0, temp1.rgb0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(7), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(7), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR2(1) |
R300_ALU_RGB_ADDRD(1) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(1) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(1) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
/* ADD temp2.rg, temp0.rgb0, temp3.rgb0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(8), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(8), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR2(3) |
R300_ALU_RGB_ADDRD(2) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(2) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
/* ADD temp3.rg, temp0.rgb0, temp5.rgb0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(9), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(9), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR2(5) |
R300_ALU_RGB_ADDRD(3) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(3) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(3) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
/* ADD temp0.rg, temp0.rgb0, temp4.rgb0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(10), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(10), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(10), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(10), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR2(4) |
R300_ALU_RGB_ADDRD(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(10), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(10), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(10), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(10), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
// third node
/* TEX temp4, temp1.rg--, tex0, 1D */
- OUT_ACCEL_REG(R300_US_TEX_INST(2), (R300_TEX_INST(R300_TEX_INST_LD) |
+ OUT_RING_REG(R300_US_TEX_INST(2), (R300_TEX_INST(R300_TEX_INST_LD) |
R300_TEX_ID(0) |
R300_TEX_SRC_ADDR(1) |
R300_TEX_DST_ADDR(4)));
/* TEX temp3, temp3.rg--, tex0, 1D */
- OUT_ACCEL_REG(R300_US_TEX_INST(3), (R300_TEX_INST(R300_TEX_INST_LD) |
+ OUT_RING_REG(R300_US_TEX_INST(3), (R300_TEX_INST(R300_TEX_INST_LD) |
R300_TEX_ID(0) |
R300_TEX_SRC_ADDR(3) |
R300_TEX_DST_ADDR(3)));
/* TEX temp5, temp2.rg--, tex0, 1D */
- OUT_ACCEL_REG(R300_US_TEX_INST(4), (R300_TEX_INST(R300_TEX_INST_LD) |
+ OUT_RING_REG(R300_US_TEX_INST(4), (R300_TEX_INST(R300_TEX_INST_LD) |
R300_TEX_ID(0) |
R300_TEX_SRC_ADDR(2) |
R300_TEX_DST_ADDR(5)));
/* TEX temp0, temp0.rg--, tex0, 1D */
- OUT_ACCEL_REG(R300_US_TEX_INST(5), (R300_TEX_INST(R300_TEX_INST_LD) |
+ OUT_RING_REG(R300_US_TEX_INST(5), (R300_TEX_INST(R300_TEX_INST_LD) |
R300_TEX_ID(0) |
R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(0)));
@@ -1488,21 +1479,21 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* LRP temp3, temp1.bbbb, temp4, temp3 ->
* - PRESUB temps, temp4 - temp3
* - MAD temp3, temp1.bbbb, temps, temp3 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(11), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(11), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(11), (R300_ALU_RGB_ADDR0(3) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(11), (R300_ALU_RGB_ADDR0(3) |
R300_ALU_RGB_ADDR1(4) |
R300_ALU_RGB_ADDR2(1) |
R300_ALU_RGB_ADDRD(3) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(11), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(11), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(11), (R300_ALU_ALPHA_ADDR0(3) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(11), (R300_ALU_ALPHA_ADDR0(3) |
R300_ALU_ALPHA_ADDR1(4) |
R300_ALU_ALPHA_ADDR2(1) |
R300_ALU_ALPHA_ADDRD(3) |
@@ -1511,22 +1502,22 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* LRP temp0, temp1.bbbb, temp5, temp0 ->
* - PRESUB temps, temp5 - temp0
* - MAD temp0, temp1.bbbb, temps, temp0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(12), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(12), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0) |
R300_ALU_RGB_INSERT_NOP));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(12), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(12), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(5) |
R300_ALU_RGB_ADDR2(1) |
R300_ALU_RGB_ADDRD(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(12), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(12), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(12), (R300_ALU_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(12), (R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(5) |
R300_ALU_ALPHA_ADDR2(1) |
R300_ALU_ALPHA_ADDRD(0) |
@@ -1535,71 +1526,71 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* LRP output, temp2.bbbb, temp3, temp0 ->
* - PRESUB temps, temp3 - temp0
* - MAD output, temp2.bbbb, temps, temp0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(13), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(13), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(13), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(13), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(3) |
R300_ALU_RGB_ADDR2(2) |
R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(13), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(13), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(13), (R300_ALU_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(13), (R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(3) |
R300_ALU_ALPHA_ADDR2(2) |
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A)));
/* Shader constants. */
- OUT_ACCEL_REG(R300_US_ALU_CONST_R(0), F_TO_24(1.0/(float)pPriv->w));
- OUT_ACCEL_REG(R300_US_ALU_CONST_G(0), 0);
- OUT_ACCEL_REG(R300_US_ALU_CONST_B(0), 0);
- OUT_ACCEL_REG(R300_US_ALU_CONST_A(0), 0);
+ OUT_RING_REG(R300_US_ALU_CONST_R(0), F_TO_24(1.0/(float)pPriv->w));
+ OUT_RING_REG(R300_US_ALU_CONST_G(0), 0);
+ OUT_RING_REG(R300_US_ALU_CONST_B(0), 0);
+ OUT_RING_REG(R300_US_ALU_CONST_A(0), 0);
- OUT_ACCEL_REG(R300_US_ALU_CONST_R(1), 0);
- OUT_ACCEL_REG(R300_US_ALU_CONST_G(1), F_TO_24(1.0/(float)pPriv->h));
- OUT_ACCEL_REG(R300_US_ALU_CONST_B(1), 0);
- OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0);
+ OUT_RING_REG(R300_US_ALU_CONST_R(1), 0);
+ OUT_RING_REG(R300_US_ALU_CONST_G(1), F_TO_24(1.0/(float)pPriv->h));
+ OUT_RING_REG(R300_US_ALU_CONST_B(1), 0);
+ OUT_RING_REG(R300_US_ALU_CONST_A(1), 0);
- FINISH_ACCEL();
+ ADVANCE_RING();
} else {
- BEGIN_ACCEL(11);
+ BEGIN_RING(2*11);
/* 2 components: 2 for tex0 */
- OUT_ACCEL_REG(R300_RS_COUNT,
+ OUT_RING_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
+ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
+ OUT_RING_REG(R300_US_PIXSIZE, 0); /* highest temp used */
/* Indirection levels */
- OUT_ACCEL_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) |
+ OUT_RING_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) |
R300_FIRST_TEX));
- OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(1) |
R300_TEX_CODE_OFFSET(0) |
R300_TEX_CODE_SIZE(1)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
+ OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
R300_ALU_SIZE(0) |
R300_TEX_START(0) |
R300_TEX_SIZE(0) |
R300_RGBA_OUT));
/* tex inst */
- OUT_ACCEL_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(0) |
R300_TEX_ID(0) |
R300_TEX_INST(R300_TEX_INST_LD)));
/* ALU inst */
/* RGB */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR_0, (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(0) |
R300_ALU_RGB_ADDR2(0) |
R300_ALU_RGB_ADDRD(0) |
@@ -1607,7 +1598,7 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_MASK_G |
R300_ALU_RGB_MASK_B)) |
R300_ALU_RGB_TARGET_A));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST_0, (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -1617,14 +1608,14 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
R300_ALU_RGB_CLAMP));
/* Alpha */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, (R300_ALU_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR_0, (R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(0) |
R300_ALU_ALPHA_ADDR2(0) |
R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
R300_ALU_ALPHA_TARGET_A |
R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST_0, (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) |
R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) |
R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
@@ -1633,7 +1624,7 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
R300_ALU_ALPHA_CLAMP));
- FINISH_ACCEL();
+ ADVANCE_RING();
}
} else {
/*
@@ -1703,53 +1694,53 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
}
if (pPriv->is_planar) {
- BEGIN_ACCEL(needgamma ? 28 + 33 : 33);
+ BEGIN_RING(2*needgamma ? 28 + 33 : 33);
/* 2 components: same 2 for tex0/1/2 */
- OUT_ACCEL_REG(R300_RS_COUNT,
+ OUT_RING_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
+ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
- OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* highest temp used */
+ OUT_RING_REG(R300_US_PIXSIZE, 2); /* highest temp used */
/* Indirection levels */
- OUT_ACCEL_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) |
+ OUT_RING_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) |
R300_FIRST_TEX));
- OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(needgamma ? 7 + 3 : 3) |
R300_TEX_CODE_OFFSET(0) |
R300_TEX_CODE_SIZE(3)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
+ OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
R300_ALU_SIZE(needgamma ? 7 + 2 : 2) |
R300_TEX_START(0) |
R300_TEX_SIZE(2) |
R300_RGBA_OUT));
/* tex inst */
- OUT_ACCEL_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(2) |
R300_TEX_ID(0) |
R300_TEX_INST(R300_TEX_INST_LD)));
- OUT_ACCEL_REG(R300_US_TEX_INST_1, (R300_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R300_US_TEX_INST_1, (R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(1) |
R300_TEX_ID(1) |
R300_TEX_INST(R300_TEX_INST_LD)));
- OUT_ACCEL_REG(R300_US_TEX_INST_2, (R300_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R300_US_TEX_INST_2, (R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(0) |
R300_TEX_ID(2) |
R300_TEX_INST(R300_TEX_INST_LD)));
/* ALU inst */
/* MAD temp2.rgb, const0.aaa, temp2.rgb, const0.rgb */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(0)) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(0)) |
R300_ALU_RGB_ADDR1(2) |
R300_ALU_RGB_ADDR2(0) |
R300_ALU_RGB_ADDRD(2) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_AAA) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_AAA) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -1758,23 +1749,23 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
/* alpha nop, but need to set up alpha source for rgb usage */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(0)) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(0)) |
R300_ALU_ALPHA_ADDR1(2) |
R300_ALU_ALPHA_ADDR2(0) |
R300_ALU_ALPHA_ADDRD(2) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* MAD temp2.rgb, const1.rgb, temp1.rgb, temp2.rgb */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(1)) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(1)) |
R300_ALU_RGB_ADDR1(1) |
R300_ALU_RGB_ADDR2(2) |
R300_ALU_RGB_ADDRD(2) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -1783,21 +1774,21 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
/* alpha nop */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(2) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* MAD result.rgb, const2.rgb, temp0.rgb, temp2.rgb */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(2)) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(2)) |
R300_ALU_RGB_ADDR1(0) |
R300_ALU_RGB_ADDR2(2) |
R300_ALU_RGB_ADDRD(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB) |
(needgamma ? 0 : R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB))));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -1807,64 +1798,64 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
R300_ALU_RGB_CLAMP));
/* write alpha 1 */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
R300_ALU_ALPHA_TARGET_A));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_1_0)));
if (needgamma) {
/* rgb temp0.r = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(3),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(3),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha lg2 temp0, temp0.r */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_R) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb temp0.g = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(4),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(4),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha lg2 temp0, temp0.g */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_G) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb temp0.b = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_B)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(5),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(5),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha lg2 temp0, temp0.b */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_B) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* MUL const1, temp1, temp0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(0) |
R300_ALU_RGB_ADDR2(0) |
R300_ALU_RGB_ADDRD(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC0_AAA) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -1873,99 +1864,99 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
/* alpha nop, but set up const1 */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(1)) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb out0.r = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R) |
R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_R)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(7),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(7),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha ex2 temp0, temp0.r */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_R) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb out0.g = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_G) |
R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(8),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(8),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha ex2 temp0, temp0.g */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_G) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb out0.b = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_B) |
R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_B)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(9),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(9),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha ex2 temp0, temp0.b */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_B) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
}
} else {
- BEGIN_ACCEL(needgamma ? 28 + 31 : 31);
+ BEGIN_RING(2*needgamma ? 28 + 31 : 31);
/* 2 components */
- OUT_ACCEL_REG(R300_RS_COUNT,
+ OUT_RING_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
+ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
- OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
+ OUT_RING_REG(R300_US_PIXSIZE, 1); /* highest temp used */
/* Indirection levels */
- OUT_ACCEL_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) |
+ OUT_RING_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) |
R300_FIRST_TEX));
- OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ OUT_RING_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(needgamma ? 7 + 3 : 3) |
R300_TEX_CODE_OFFSET(0) |
R300_TEX_CODE_SIZE(1)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
+ OUT_RING_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
R300_ALU_SIZE(needgamma ? 7 + 2 : 2) |
R300_TEX_START(0) |
R300_TEX_SIZE(0) |
R300_RGBA_OUT));
/* tex inst */
- OUT_ACCEL_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(0) |
R300_TEX_ID(0) |
R300_TEX_INST(R300_TEX_INST_LD)));
/* ALU inst */
/* MAD temp1.rgb, const0.aaa, temp0.ggg, const0.rgb */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(0)) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(0)) |
R300_ALU_RGB_ADDR1(0) |
R300_ALU_RGB_ADDR2(0) |
R300_ALU_RGB_ADDRD(1) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_AAA) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_AAA) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_GGG) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -1974,23 +1965,23 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
/* alpha nop, but need to set up alpha source for rgb usage */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(0)) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(0)) |
R300_ALU_ALPHA_ADDR1(0) |
R300_ALU_ALPHA_ADDR2(0) |
R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* MAD temp1.rgb, const1.rgb, temp0.bbb, temp1.rgb */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(1)) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(1)) |
R300_ALU_RGB_ADDR1(0) |
R300_ALU_RGB_ADDR2(1) |
R300_ALU_RGB_ADDRD(1) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_BBB) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -1999,21 +1990,21 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
/* alpha nop */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* MAD result.rgb, const2.rgb, temp0.rrr, temp1.rgb */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(2)) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(2)) |
R300_ALU_RGB_ADDR1(0) |
R300_ALU_RGB_ADDR2(1) |
R300_ALU_RGB_ADDRD(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB) |
(needgamma ? 0 : R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB))));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RRR) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -2023,64 +2014,64 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
R300_ALU_RGB_CLAMP));
/* write alpha 1 */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
R300_ALU_ALPHA_TARGET_A));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_1_0)));
if (needgamma) {
/* rgb temp0.r = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(3),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(3),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha lg2 temp0, temp0.r */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_R) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb temp0.g = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(4),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(4),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha lg2 temp0, temp0.g */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_G) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb temp0.b = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_B)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(5),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(5),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha lg2 temp0, temp0.b */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_LN2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_B) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* MUL const1, temp1, temp0 */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(0) |
R300_ALU_RGB_ADDR2(0) |
R300_ALU_RGB_ADDRD(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ OUT_RING_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC0_AAA) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -2089,55 +2080,55 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
/* alpha nop, but set up const1 */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(1)) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb out0.r = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R) |
R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_R)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(7),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(7),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha ex2 temp0, temp0.r */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_R) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb out0.g = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_G) |
R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_G)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(8),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(8),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha ex2 temp0, temp0.g */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_G) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
/* rgb out0.b = op_sop, set up src0 reg */
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) |
+ OUT_RING_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_B) |
R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_B)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST(9),
+ OUT_RING_REG(R300_US_ALU_RGB_INST(9),
R300_ALU_RGB_OP(R300_ALU_RGB_OP_SOP) |
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE));
/* alpha ex2 temp0, temp0.b */
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
+ OUT_RING_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_EX2) |
R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_B) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
@@ -2146,36 +2137,36 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* Shader constants. */
/* constant 0: off, yco */
- OUT_ACCEL_REG(R300_US_ALU_CONST_R(0), F_TO_24(off[0]));
- OUT_ACCEL_REG(R300_US_ALU_CONST_G(0), F_TO_24(off[1]));
- OUT_ACCEL_REG(R300_US_ALU_CONST_B(0), F_TO_24(off[2]));
- OUT_ACCEL_REG(R300_US_ALU_CONST_A(0), F_TO_24(yco));
+ OUT_RING_REG(R300_US_ALU_CONST_R(0), F_TO_24(off[0]));
+ OUT_RING_REG(R300_US_ALU_CONST_G(0), F_TO_24(off[1]));
+ OUT_RING_REG(R300_US_ALU_CONST_B(0), F_TO_24(off[2]));
+ OUT_RING_REG(R300_US_ALU_CONST_A(0), F_TO_24(yco));
/* constant 1: uco */
- OUT_ACCEL_REG(R300_US_ALU_CONST_R(1), F_TO_24(uco[0]));
- OUT_ACCEL_REG(R300_US_ALU_CONST_G(1), F_TO_24(uco[1]));
- OUT_ACCEL_REG(R300_US_ALU_CONST_B(1), F_TO_24(uco[2]));
- OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), F_TO_24(gamma));
+ OUT_RING_REG(R300_US_ALU_CONST_R(1), F_TO_24(uco[0]));
+ OUT_RING_REG(R300_US_ALU_CONST_G(1), F_TO_24(uco[1]));
+ OUT_RING_REG(R300_US_ALU_CONST_B(1), F_TO_24(uco[2]));
+ OUT_RING_REG(R300_US_ALU_CONST_A(1), F_TO_24(gamma));
/* constant 2: vco */
- OUT_ACCEL_REG(R300_US_ALU_CONST_R(2), F_TO_24(vco[0]));
- OUT_ACCEL_REG(R300_US_ALU_CONST_G(2), F_TO_24(vco[1]));
- OUT_ACCEL_REG(R300_US_ALU_CONST_B(2), F_TO_24(vco[2]));
- OUT_ACCEL_REG(R300_US_ALU_CONST_A(2), F_TO_24(0.0));
+ OUT_RING_REG(R300_US_ALU_CONST_R(2), F_TO_24(vco[0]));
+ OUT_RING_REG(R300_US_ALU_CONST_G(2), F_TO_24(vco[1]));
+ OUT_RING_REG(R300_US_ALU_CONST_B(2), F_TO_24(vco[2]));
+ OUT_RING_REG(R300_US_ALU_CONST_A(2), F_TO_24(0.0));
- FINISH_ACCEL();
+ ADVANCE_RING();
}
BEGIN_ACCEL_RELOC(6, 2);
- OUT_ACCEL_REG(R300_TX_INVALTAGS, 0);
- OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
+ OUT_RING_REG(R300_TX_INVALTAGS, 0);
+ OUT_RING_REG(R300_TX_ENABLE, txenable);
EMIT_WRITE_OFFSET(R300_RB3D_COLOROFFSET0, 0, pPixmap);
EMIT_COLORPITCH(R300_RB3D_COLORPITCH0, colorpitch, pPixmap);
/* no need to enable blending */
- OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
+ OUT_RING_REG(R300_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
- OUT_ACCEL_REG(R300_VAP_VTX_SIZE, pPriv->vtx_count);
- FINISH_ACCEL();
+ OUT_RING_REG(R300_VAP_VTX_SIZE, pPriv->vtx_count);
+ ADVANCE_RING();
if (pPriv->vsync) {
xf86CrtcPtr crtc;
@@ -2188,17 +2179,17 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
if (crtc)
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
- crtc,
- pPriv->drw_y - crtc->y,
- (pPriv->drw_y - crtc->y) + pPriv->dst_h);
+ RADEONWaitForVLine(pScrn, pPixmap,
+ crtc,
+ pPriv->drw_y - crtc->y,
+ (pPriv->drw_y - crtc->y) + pPriv->dst_h);
}
return TRUE;
}
static void
-FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+R300DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
@@ -2214,7 +2205,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
dstyoff = 0;
#endif
- if (!FUNC_NAME(R300PrepareTexturedVideo)(pScrn, pPriv))
+ if (!R300PrepareTexturedVideo(pScrn, pPriv))
return;
/*
@@ -2245,7 +2236,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
if (draw_size > radeon_cs_space_remaining(pScrn)) {
radeon_cs_flush_indirect(pScrn);
- if (!FUNC_NAME(R300PrepareTexturedVideo)(pScrn, pPriv))
+ if (!R300PrepareTexturedVideo(pScrn, pPriv))
return;
}
@@ -2274,13 +2265,13 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/*
* Set up the scissor area to that of the output size.
*/
- BEGIN_ACCEL(2);
+ BEGIN_RING(2*2);
/* R300 has an offset */
- OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX + 1440) << R300_SCISSOR_X_SHIFT) |
+ OUT_RING_REG(R300_SC_SCISSOR0, (((dstX + 1440) << R300_SCISSOR_X_SHIFT) |
((dstY + 1440) << R300_SCISSOR_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_SCISSOR1, (((dstX + dstw + 1440 - 1) << R300_SCISSOR_X_SHIFT) |
+ OUT_RING_REG(R300_SC_SCISSOR1, (((dstX + dstw + 1440 - 1) << R300_SCISSOR_X_SHIFT) |
((dstY + dsth + 1440 - 1) << R300_SCISSOR_Y_SHIFT)));
- FINISH_ACCEL();
+ ADVANCE_RING();
if (use_quad) {
BEGIN_RING(4 * pPriv->vtx_count + 4);
@@ -2359,24 +2350,24 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
}
/* flushing is pipelined, free/finish is not */
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
ADVANCE_RING();
pBox++;
}
- BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL);
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
- FINISH_ACCEL();
+ BEGIN_RING(2*3);
+ OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA);
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL);
+ OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+ ADVANCE_RING();
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
}
static Bool
-FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+R500PrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
@@ -2502,15 +2493,15 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
txoffset = 0;
BEGIN_ACCEL_RELOC(out_size, 1);
- OUT_ACCEL_REG(R300_TX_FILTER0_0, txfilter);
- OUT_ACCEL_REG(R300_TX_FILTER1_0, 0);
- OUT_ACCEL_REG(R300_TX_FORMAT0_0, txformat0);
- OUT_ACCEL_REG(R300_TX_FORMAT1_0, txformat1);
- OUT_ACCEL_REG(R300_TX_FORMAT2_0, txpitch);
+ OUT_RING_REG(R300_TX_FILTER0_0, txfilter);
+ OUT_RING_REG(R300_TX_FILTER1_0, 0);
+ OUT_RING_REG(R300_TX_FORMAT0_0, txformat0);
+ OUT_RING_REG(R300_TX_FORMAT1_0, txformat1);
+ OUT_RING_REG(R300_TX_FORMAT2_0, txpitch);
OUT_TEXTURE_REG(R300_TX_OFFSET_0, txoffset, src_bo);
if (info->ChipFamily == CHIP_FAMILY_R520)
- OUT_ACCEL_REG(R500_US_FORMAT0_0, us_format);
- FINISH_ACCEL();
+ OUT_RING_REG(R500_US_FORMAT0_0, us_format);
+ ADVANCE_RING();
txenable = R300_TEX_0_ENABLE;
@@ -2526,19 +2517,19 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R300_TX_MAG_FILTER_LINEAR);
BEGIN_ACCEL_RELOC(12, 2);
- OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT));
- OUT_ACCEL_REG(R300_TX_FILTER1_1, 0);
- OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0);
- OUT_ACCEL_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8);
- OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch);
+ OUT_RING_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT));
+ OUT_RING_REG(R300_TX_FILTER1_1, 0);
+ OUT_RING_REG(R300_TX_FORMAT0_1, txformat0);
+ OUT_RING_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8);
+ OUT_RING_REG(R300_TX_FORMAT2_1, txpitch);
OUT_TEXTURE_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset, src_bo);
- OUT_ACCEL_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT));
- OUT_ACCEL_REG(R300_TX_FILTER1_2, 0);
- OUT_ACCEL_REG(R300_TX_FORMAT0_2, txformat0);
- OUT_ACCEL_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8);
- OUT_ACCEL_REG(R300_TX_FORMAT2_2, txpitch);
+ OUT_RING_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT));
+ OUT_RING_REG(R300_TX_FILTER1_2, 0);
+ OUT_RING_REG(R300_TX_FORMAT0_2, txformat0);
+ OUT_RING_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8);
+ OUT_RING_REG(R300_TX_FORMAT2_2, txpitch);
OUT_TEXTURE_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset, src_bo);
- FINISH_ACCEL();
+ ADVANCE_RING();
txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE;
}
@@ -2561,13 +2552,13 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
bicubic_offset = 0;
BEGIN_ACCEL_RELOC(6, 1);
- OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter);
- OUT_ACCEL_REG(R300_TX_FILTER1_1, 0);
- OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0);
- OUT_ACCEL_REG(R300_TX_FORMAT1_1, txformat1);
- OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch);
+ OUT_RING_REG(R300_TX_FILTER0_1, txfilter);
+ OUT_RING_REG(R300_TX_FILTER1_1, 0);
+ OUT_RING_REG(R300_TX_FORMAT0_1, txformat0);
+ OUT_RING_REG(R300_TX_FORMAT1_1, txformat1);
+ OUT_RING_REG(R300_TX_FORMAT2_1, txpitch);
OUT_TEXTURE_REG(R300_TX_OFFSET_1, bicubic_offset, info->bicubic_bo);
- FINISH_ACCEL();
+ ADVANCE_RING();
/* Enable tex 1 */
txenable |= R300_TEX_1_ENABLE;
@@ -2576,14 +2567,14 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* setup the VAP */
if (info->accel_state->has_tcl) {
if (pPriv->bicubic_enabled)
- BEGIN_ACCEL(7);
+ BEGIN_RING(2*7);
else
- BEGIN_ACCEL(6);
+ BEGIN_RING(2*6);
} else {
if (pPriv->bicubic_enabled)
- BEGIN_ACCEL(5);
+ BEGIN_RING(2*5);
else
- BEGIN_ACCEL(4);
+ BEGIN_RING(2*4);
}
/* These registers define the number, type, and location of data submitted
@@ -2600,7 +2591,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
* Fog
*/
if (pPriv->bicubic_enabled) {
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
(0 << R300_SKIP_DWORDS_0_SHIFT) |
(0 << R300_DST_VEC_LOC_0_SHIFT) |
@@ -2609,14 +2600,14 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
(0 << R300_SKIP_DWORDS_1_SHIFT) |
(6 << R300_DST_VEC_LOC_1_SHIFT) |
R300_SIGNED_1));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
+ OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_1,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
(0 << R300_SKIP_DWORDS_2_SHIFT) |
(7 << R300_DST_VEC_LOC_2_SHIFT) |
R300_LAST_VEC_2 |
R300_SIGNED_2));
} else {
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
(0 << R300_SKIP_DWORDS_0_SHIFT) |
(0 << R300_DST_VEC_LOC_0_SHIFT) |
@@ -2637,61 +2628,61 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
*/
if (info->accel_state->has_tcl) {
if (pPriv->bicubic_enabled) {
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0,
((11 << R300_PVS_FIRST_INST_SHIFT) |
(13 << R300_PVS_XYZW_VALID_INST_SHIFT) |
(13 << R300_PVS_LAST_INST_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1,
(13 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
} else {
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_0,
((9 << R300_PVS_FIRST_INST_SHIFT) |
(10 << R300_PVS_XYZW_VALID_INST_SHIFT) |
(10 << R300_PVS_LAST_INST_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ OUT_RING_REG(R300_VAP_PVS_CODE_CNTL_1,
(10 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
}
}
/* Position and one set of 2 texture coordinates */
- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
+ OUT_RING_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
if (pPriv->bicubic_enabled)
- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
+ OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
(2 << R300_TEX_1_COMP_CNT_SHIFT)));
else
- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
+ OUT_RING_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
- OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
- FINISH_ACCEL();
+ OUT_RING_REG(R300_US_OUT_FMT_0, output_fmt);
+ ADVANCE_RING();
/* setup pixel shader */
if (pPriv->bicubic_state != BICUBIC_OFF) {
if (pPriv->bicubic_enabled) {
- BEGIN_ACCEL(7);
+ BEGIN_RING(2*7);
/* 4 components: 2 for tex0 and 2 for tex1 */
- OUT_ACCEL_REG(R300_RS_COUNT,
+ OUT_RING_REG(R300_RS_COUNT,
((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1));
+ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1));
/* Pixel stack frame size. */
- OUT_ACCEL_REG(R300_US_PIXSIZE, 5);
+ OUT_RING_REG(R300_US_PIXSIZE, 5);
/* FP length. */
- OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(13)));
- OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
R500_US_CODE_RANGE_SIZE(13)));
/* Prepare for FP emission. */
- OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
- FINISH_ACCEL();
+ OUT_RING_REG(R500_US_CODE_OFFSET, 0);
+ OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
+ ADVANCE_RING();
- BEGIN_ACCEL(89);
+ BEGIN_RING(2*89);
/* Pixel shader.
* I've gone ahead and annotated each instruction, since this
* thing is MASSIVE. :3
@@ -2699,14 +2690,14 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
* inputs, all temps are offset by 2. temp0 -> register2. */
/* TEX temp2, input1.xxxx, tex1, 1D */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_R |
R500_TEX_SRC_R_SWIZ_R |
@@ -2716,21 +2707,21 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* TEX temp5, input1.yyyy, tex1, 1D */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
R500_TEX_SRC_S_SWIZ_G |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_G |
@@ -2740,24 +2731,24 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* MUL temp4, const0.x0x0, temp2.yyxx */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_0 |
R500_ALU_RGB_B_SWIZ_A_R |
@@ -2765,13 +2756,13 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_0 |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
@@ -2779,20 +2770,20 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_0));
/* MAD temp3, const0.0y0y, temp5.xxxx, temp4 */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(5) |
R500_RGB_ADDR2(4)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(5) |
R500_ALPHA_ADDR2(4)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_0 |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_0 |
@@ -2800,13 +2791,13 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_G |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -2815,28 +2806,28 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_A));
/* ADD temp3, temp3, input0.xyxy */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(3) |
R500_RGB_ADDR2(0)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(3) |
R500_ALPHA_ADDR2(0)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
R500_ALU_RGB_G_SWIZ_A_1 |
R500_ALU_RGB_B_SWIZ_A_1 |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -2845,15 +2836,15 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_G));
/* TEX temp1, temp3.zwxy, tex0, 2D */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
R500_TEX_SRC_S_SWIZ_B |
R500_TEX_SRC_T_SWIZ_A |
R500_TEX_SRC_R_SWIZ_R |
@@ -2863,22 +2854,22 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* TEX temp3, temp3.xyzw, tex0, 2D */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_B |
@@ -2888,25 +2879,25 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* MAD temp4, const0.0y0y, temp5.yyyy, temp4 */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(5) |
R500_RGB_ADDR2(4)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(5) |
R500_ALPHA_ADDR2(4)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_0 |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_0 |
@@ -2914,13 +2905,13 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_G));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC0 |
R500_ALPHA_SWIZ_A_G |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_G));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -2929,28 +2920,28 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_A));
/* ADD temp0, temp4, input0.xyxy */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) |
R500_RGB_ADDR2(0)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) |
R500_ALPHA_ADDR2(0)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 |
R500_ALU_RGB_G_SWIZ_A_1 |
R500_ALU_RGB_B_SWIZ_A_1 |
R500_ALU_RGB_SEL_B_SRC1 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_1 |
R500_ALPHA_SEL_B_SRC1 |
R500_ALPHA_SWIZ_B_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -2959,16 +2950,16 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_G));
/* TEX temp4, temp0.zwzw, tex0, 2D */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_B |
R500_TEX_SRC_T_SWIZ_A |
R500_TEX_SRC_R_SWIZ_B |
@@ -2978,22 +2969,22 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* TEX temp0, temp0.xyzw, tex0, 2D */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_SRC_R_SWIZ_B |
@@ -3003,27 +2994,27 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* LRP temp3, temp2.zzzz, temp1, temp3 ->
* - PRESUB temps, temp1 - temp3
* - MAD temp2.zzzz, temps, temp3 */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR2(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -3031,13 +3022,13 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -3048,21 +3039,21 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* LRP temp0, temp2.zzzz, temp4, temp0 ->
* - PRESUB temps, temp4 - temp1
* - MAD temp2.zzzz, temps, temp0 */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(4) |
R500_RGB_ADDR2(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(4) |
R500_ALPHA_ADDR2(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -3070,13 +3061,13 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -3087,7 +3078,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
/* LRP output, temp5.zzzz, temp3, temp0 ->
* - PRESUB temps, temp3 - temp0
* - MAD temp5.zzzz, temps, temp0 */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_LAST |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -3098,15 +3089,15 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
R500_INST_ALPHA_OMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 |
R500_RGB_ADDR1(3) |
R500_RGB_ADDR2(5)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_SRCP_OP_A1_MINUS_A0 |
R500_ALPHA_ADDR1(3) |
R500_ALPHA_ADDR2(5)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 |
R500_ALU_RGB_R_SWIZ_A_B |
R500_ALU_RGB_G_SWIZ_A_B |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -3114,13 +3105,13 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) |
R500_ALPHA_OP_MAD |
R500_ALPHA_SEL_A_SRC2 |
R500_ALPHA_SWIZ_A_B |
R500_ALPHA_SEL_B_SRCP |
R500_ALPHA_SWIZ_B_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -3129,7 +3120,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_A));
/* Shader constants. */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0));
+ OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0));
/* const0 = {1 / texture[0].width, 1 / texture[0].height, 0, 0} */
OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w));
@@ -3137,32 +3128,32 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0x0);
- FINISH_ACCEL();
+ ADVANCE_RING();
} else {
- BEGIN_ACCEL(19);
+ BEGIN_RING(2*19);
/* 2 components: 2 for tex0 */
- OUT_ACCEL_REG(R300_RS_COUNT,
+ OUT_RING_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
+ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
/* Pixel stack frame size. */
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
+ OUT_RING_REG(R300_US_PIXSIZE, 0); /* highest temp used */
/* FP length. */
- OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(1)));
- OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
R500_US_CODE_RANGE_SIZE(1)));
/* Prepare for FP emission. */
- OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
+ OUT_RING_REG(R500_US_CODE_OFFSET, 0);
+ OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
/* tex inst */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -3170,11 +3161,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_INST_ALPHA_WMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_DST_ADDR(0) |
@@ -3182,7 +3173,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
R500_DX_S_SWIZ_R |
R500_DX_T_SWIZ_R |
R500_DX_R_SWIZ_R |
@@ -3192,11 +3183,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
R500_DY_Q_SWIZ_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* ALU inst */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
R500_INST_RGB_OMASK_R |
@@ -3205,17 +3196,17 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_INST_ALPHA_OMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR1(0) |
R500_RGB_ADDR1_CONST |
R500_RGB_ADDR2(0) |
R500_RGB_ADDR2_CONST));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR1_CONST |
R500_ALPHA_ADDR2(0) |
R500_ALPHA_ADDR2_CONST));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -3223,15 +3214,15 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1 |
R500_ALU_RGB_G_SWIZ_B_1));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_A |
R500_ALPHA_SWIZ_B_1));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0));
- FINISH_ACCEL();
+ ADVANCE_RING();
}
} else {
/*
@@ -3303,30 +3294,30 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
}
if (pPriv->is_planar) {
- BEGIN_ACCEL(56);
+ BEGIN_RING(2*56);
/* 2 components: 2 for tex0 */
- OUT_ACCEL_REG(R300_RS_COUNT,
+ OUT_RING_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
+ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
/* Pixel stack frame size. */
- OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* highest temp used */
+ OUT_RING_REG(R300_US_PIXSIZE, 2); /* highest temp used */
/* FP length. */
- OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(5)));
- OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
R500_US_CODE_RANGE_SIZE(5)));
/* Prepare for FP emission. */
- OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
+ OUT_RING_REG(R500_US_CODE_OFFSET, 0);
+ OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
/* tex inst */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -3334,10 +3325,10 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_INST_ALPHA_WMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_DST_ADDR(2) |
@@ -3345,7 +3336,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
R500_DX_S_SWIZ_R |
R500_DX_T_SWIZ_R |
R500_DX_R_SWIZ_R |
@@ -3355,11 +3346,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
R500_DY_Q_SWIZ_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* tex inst */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -3367,10 +3358,10 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_INST_ALPHA_WMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_DST_ADDR(1) |
@@ -3378,7 +3369,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
R500_DX_S_SWIZ_R |
R500_DX_T_SWIZ_R |
R500_DX_R_SWIZ_R |
@@ -3388,11 +3379,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
R500_DY_Q_SWIZ_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* tex inst */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -3400,11 +3391,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_INST_ALPHA_WMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(2) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(2) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_DST_ADDR(0) |
@@ -3412,7 +3403,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
R500_DX_S_SWIZ_R |
R500_DX_T_SWIZ_R |
R500_DX_R_SWIZ_R |
@@ -3422,28 +3413,28 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
R500_DY_Q_SWIZ_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* ALU inst */
/* MAD temp2.rgb, const0.aaa, temp2.rgb, const0.rgb */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(2) |
R500_RGB_ADDR2(0) |
R500_RGB_ADDR2_CONST));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(2) |
R500_ALPHA_ADDR2(0) |
R500_ALPHA_ADDR2_CONST));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_A |
R500_ALU_RGB_G_SWIZ_A_A |
R500_ALU_RGB_B_SWIZ_A_A |
@@ -3451,11 +3442,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_ADDRD(2) |
R500_ALPHA_SWIZ_A_0 |
R500_ALPHA_SWIZ_B_0));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_ADDRD(2) |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -3465,21 +3456,21 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_0));
/* MAD temp2.rgb, const1.rgb, temp1.rgb, temp2.rgb */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR2(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -3487,11 +3478,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_ADDRD(2) |
R500_ALPHA_SWIZ_A_0 |
R500_ALPHA_SWIZ_B_0));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_ADDRD(2) |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -3501,7 +3492,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_0));
/* MAD result.rgb, const2.rgb, temp0.rgb, temp2.rgb */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
R500_INST_RGB_OMASK_R |
@@ -3510,15 +3501,15 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_INST_ALPHA_OMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(0) |
R500_RGB_ADDR2(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(2) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(2) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR2(2)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -3526,11 +3517,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_ADDRD(0) |
R500_ALPHA_SWIZ_A_0 |
R500_ALPHA_SWIZ_B_0));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -3540,30 +3531,30 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_1));
} else {
- BEGIN_ACCEL(44);
+ BEGIN_RING(2*44);
/* 2 components: 2 for tex0/1/2 */
- OUT_ACCEL_REG(R300_RS_COUNT,
+ OUT_RING_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
+ OUT_RING_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
/* Pixel stack frame size. */
- OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
+ OUT_RING_REG(R300_US_PIXSIZE, 1); /* highest temp used */
/* FP length. */
- OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ OUT_RING_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(3)));
- OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ OUT_RING_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
R500_US_CODE_RANGE_SIZE(3)));
/* Prepare for FP emission. */
- OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
+ OUT_RING_REG(R500_US_CODE_OFFSET, 0);
+ OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0));
/* tex inst */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
@@ -3571,11 +3562,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_INST_ALPHA_WMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_DST_ADDR(0) |
@@ -3583,7 +3574,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
R500_DX_S_SWIZ_R |
R500_DX_T_SWIZ_R |
R500_DX_R_SWIZ_R |
@@ -3593,28 +3584,28 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
R500_DY_Q_SWIZ_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* ALU inst */
/* MAD temp1.rgb, const0.aaa, temp0.ggg, const0.rgb */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(0) |
R500_RGB_ADDR2(0) |
R500_RGB_ADDR2_CONST));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR2(0) |
R500_ALPHA_ADDR2_CONST));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_A |
R500_ALU_RGB_G_SWIZ_A_A |
R500_ALU_RGB_B_SWIZ_A_A |
@@ -3622,11 +3613,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_G));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_ADDRD(1) |
R500_ALPHA_SWIZ_A_0 |
R500_ALPHA_SWIZ_B_0));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_ADDRD(1) |
R500_ALU_RGBA_SEL_C_SRC0 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -3636,21 +3627,21 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_0));
/* MAD temp1.rgb, const1.rgb, temp0.bbb, temp1.rgb */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(1) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(0) |
R500_RGB_ADDR2(1)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR2(1)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -3658,11 +3649,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_B |
R500_ALU_RGB_B_SWIZ_B_B |
R500_ALU_RGB_G_SWIZ_B_B));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_ADDRD(1) |
R500_ALPHA_SWIZ_A_0 |
R500_ALPHA_SWIZ_B_0));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_ADDRD(1) |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -3672,7 +3663,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGBA_A_SWIZ_0));
/* MAD result.rgb, const2.rgb, temp0.rrr, temp1.rgb */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
R500_INST_RGB_OMASK_R |
@@ -3681,15 +3672,15 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_INST_ALPHA_OMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(2) |
R500_RGB_ADDR0_CONST |
R500_RGB_ADDR1(0) |
R500_RGB_ADDR2(1)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(1) |
R500_ALPHA_ADDR0_CONST |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR2(1)));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B |
@@ -3697,11 +3688,11 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_ADDRD(1) |
R500_ALPHA_SWIZ_A_0 |
R500_ALPHA_SWIZ_B_0));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ OUT_RING_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_ADDRD(1) |
R500_ALU_RGBA_SEL_C_SRC2 |
R500_ALU_RGBA_R_SWIZ_R |
@@ -3712,7 +3703,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
}
/* Shader constants. */
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0));
+ OUT_RING_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0));
/* constant 0: off, yco */
OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, off[0]);
@@ -3730,21 +3721,21 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, vco[2]);
OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0.0);
- FINISH_ACCEL();
+ ADVANCE_RING();
}
BEGIN_ACCEL_RELOC(6, 2);
- OUT_ACCEL_REG(R300_TX_INVALTAGS, 0);
- OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
+ OUT_RING_REG(R300_TX_INVALTAGS, 0);
+ OUT_RING_REG(R300_TX_ENABLE, txenable);
EMIT_WRITE_OFFSET(R300_RB3D_COLOROFFSET0, 0, pPixmap);
EMIT_COLORPITCH(R300_RB3D_COLORPITCH0, colorpitch, pPixmap);
/* no need to enable blending */
- OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
+ OUT_RING_REG(R300_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
- OUT_ACCEL_REG(R300_VAP_VTX_SIZE, pPriv->vtx_count);
- FINISH_ACCEL();
+ OUT_RING_REG(R300_VAP_VTX_SIZE, pPriv->vtx_count);
+ ADVANCE_RING();
if (pPriv->vsync) {
xf86CrtcPtr crtc;
@@ -3757,17 +3748,17 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
if (crtc)
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
- crtc,
- pPriv->drw_y - crtc->y,
- (pPriv->drw_y - crtc->y) + pPriv->dst_h);
+ RADEONWaitForVLine(pScrn, pPixmap,
+ crtc,
+ pPriv->drw_y - crtc->y,
+ (pPriv->drw_y - crtc->y) + pPriv->dst_h);
}
return TRUE;
}
static void
-FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+R500DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
@@ -3783,7 +3774,7 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
dstyoff = 0;
#endif
- if (!FUNC_NAME(R500PrepareTexturedVideo)(pScrn, pPriv))
+ if (!R500PrepareTexturedVideo(pScrn, pPriv))
return;
/*
@@ -3813,7 +3804,7 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
if (draw_size > radeon_cs_space_remaining(pScrn)) {
radeon_cs_flush_indirect(pScrn);
- if (!FUNC_NAME(R500PrepareTexturedVideo)(pScrn, pPriv))
+ if (!R500PrepareTexturedVideo(pScrn, pPriv))
return;
}
@@ -3832,12 +3823,12 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
- BEGIN_ACCEL(2);
- OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX) << R300_SCISSOR_X_SHIFT) |
+ BEGIN_RING(2*2);
+ OUT_RING_REG(R300_SC_SCISSOR0, (((dstX) << R300_SCISSOR_X_SHIFT) |
((dstY) << R300_SCISSOR_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_SCISSOR1, (((dstX + dstw - 1) << R300_SCISSOR_X_SHIFT) |
+ OUT_RING_REG(R300_SC_SCISSOR1, (((dstX + dstw - 1) << R300_SCISSOR_X_SHIFT) |
((dstY + dsth - 1) << R300_SCISSOR_Y_SHIFT)));
- FINISH_ACCEL();
+ ADVANCE_RING();
BEGIN_RING(3 * pPriv->vtx_count + 4);
OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
@@ -3874,22 +3865,21 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
}
/* flushing is pipelined, free/finish is not */
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
ADVANCE_RING();
pBox++;
}
- BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL);
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
- FINISH_ACCEL();
+ BEGIN_RING(2*3);
+ OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA);
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL);
+ OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+ ADVANCE_RING();
DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
}
#undef VTX_OUT_4
#undef VTX_OUT_6
-#undef FUNC_NAME
commit b422d8085aab4e01a1ac4ffb247c73fe51aafa0d
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jun 15 16:14:54 2012 +0100
radeon: drop radeon_commonfuncs.
modify all the macros and drop it into radeon_accel.c
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/Makefile.am b/src/Makefile.am
index 20d6551..a32fe8d 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -83,7 +83,6 @@ EXTRA_DIST = \
ati.h \
ativersion.h \
bicubic_table.h \
- radeon_commonfuncs.c \
radeon_drm.h \
radeon_exa_render.c \
radeon_exa_funcs.c \
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 4e24053..b21fb14 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -159,17 +159,6 @@ int radeon_cs_space_remaining(ScrnInfoPtr pScrn)
return (info->cs->ndw - info->cs->cdw);
}
-#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
-#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
-#define FINISH_ACCEL() ADVANCE_RING()
-
-
-#include "radeon_commonfuncs.c"
-
-#undef BEGIN_ACCEL
-#undef OUT_ACCEL_REG
-#undef FINISH_ACCEL
-
void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap)
{
switch(swap) {
@@ -240,6 +229,781 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
return TRUE;
}
+static void RADEONInit3DEngineCP(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ uint32_t gb_tile_config, vap_cntl;
+
+ info->accel_state->texW[0] = info->accel_state->texH[0] =
+ info->accel_state->texW[1] = info->accel_state->texH[1] = 1;
+
+ if (IS_R300_3D || IS_R500_3D) {
+
+ gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
+
+ switch(info->accel_state->num_gb_pipes) {
+ case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
+ case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
+ case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
+ default:
+ case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
+ }
+
+ BEGIN_RING(2*3);
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
+ OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
+ OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
+ ADVANCE_RING();
+
+ BEGIN_RING(2*3);
+ OUT_RING_REG(R300_GB_AA_CONFIG, 0);
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
+ OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
+ ADVANCE_RING();
+
+ BEGIN_RING(2*4);
+ OUT_RING_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
+ OUT_RING_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
+ R300_COLOR_ROUND_NEAREST));
+ OUT_RING_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
+ R300_ALPHA0_SHADING_GOURAUD |
+ R300_RGB1_SHADING_GOURAUD |
+ R300_ALPHA1_SHADING_GOURAUD |
+ R300_RGB2_SHADING_GOURAUD |
+ R300_ALPHA2_SHADING_GOURAUD |
+ R300_RGB3_SHADING_GOURAUD |
+ R300_ALPHA3_SHADING_GOURAUD));
+ OUT_RING_REG(R300_GA_OFFSET, 0);
+ ADVANCE_RING();
+
+ BEGIN_RING(2*5);
+ OUT_RING_REG(R300_SU_TEX_WRAP, 0);
+ OUT_RING_REG(R300_SU_POLY_OFFSET_ENABLE, 0);
+ OUT_RING_REG(R300_SU_CULL_MODE, R300_FACE_NEG);
+ OUT_RING_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
+ OUT_RING_REG(R300_SU_DEPTH_OFFSET, 0);
+ ADVANCE_RING();
+
+ /* setup the VAP */
+ if (info->accel_state->has_tcl)
+ vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (9 << R300_VF_MAX_VTX_NUM_SHIFT));
+ else
+ vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (5 << R300_VF_MAX_VTX_NUM_SHIFT));
+
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350))
+ vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
+ else if (info->ChipFamily == CHIP_FAMILY_RV530)
+ vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
+ else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
+ (info->ChipFamily == CHIP_FAMILY_R420))
+ vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
+ else if ((info->ChipFamily == CHIP_FAMILY_R520) ||
+ (info->ChipFamily == CHIP_FAMILY_R580) ||
+ (info->ChipFamily == CHIP_FAMILY_RV560) ||
+ (info->ChipFamily == CHIP_FAMILY_RV570))
+ vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
+ else
+ vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
+
+ if (info->accel_state->has_tcl)
+ BEGIN_RING(2*15);
+ else
+ BEGIN_RING(2*9);
+ OUT_RING_REG(R300_VAP_VTX_STATE_CNTL, 0);
+ OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+
+ if (info->accel_state->has_tcl)
+ OUT_RING_REG(R300_VAP_CNTL_STATUS, 0);
+ else
+ OUT_RING_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
+ OUT_RING_REG(R300_VAP_CNTL, vap_cntl);
+ OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+ OUT_RING_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
+ OUT_RING_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
+
+ OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_1_SHIFT)));
+ OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_2_SHIFT)));
+
+ if (info->accel_state->has_tcl) {
+ OUT_RING_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
+ OUT_RING_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
+ OUT_RING_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
+ OUT_RING_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
+ OUT_RING_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
+ OUT_RING_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
+ }
+ ADVANCE_RING();
+
+ /* pre-load the vertex shaders */
+ if (info->accel_state->has_tcl) {
+ BEGIN_RING(2*37);
+ /* exa composite shader program */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0));
+ /* PVS inst 0 - dst X,Y */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 1 - src X */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 2 - src Y */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_Y));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+ R300_PVS_SRC_OFFSET(1) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 3 - src X / w */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_X));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 4 - src y / h */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_Y));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+ R300_PVS_SRC_OFFSET(1) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 5 - mask X */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_Z));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(7) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+ R300_PVS_SRC_OFFSET(2) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(7) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 6 - mask Y */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_W));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(7) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+ R300_PVS_SRC_OFFSET(3) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(7) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 7 - mask X / w */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(2) |
+ R300_PVS_DST_WE_X));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+ R300_PVS_SRC_OFFSET(2) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 8 - mask y / h */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(2) |
+ R300_PVS_DST_WE_Y));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+ R300_PVS_SRC_OFFSET(3) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ ADVANCE_RING();
+
+ /* Xv shader program */
+ BEGIN_RING(2*9);
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(9));
+
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ ADVANCE_RING();
+
+ /* Xv bicubic shader program */
+ BEGIN_RING(2*13);
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(11));
+ /* PVS inst 0 */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 1 */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(6) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 2 */
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(2) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(7) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(7) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(7) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ ADVANCE_RING();
+ }
+
+ /* pre-load the RS instructions */
+ BEGIN_RING(2*4);
+ if (IS_R300_3D) {
+ /* rasterizer source table
+ * R300_RS_TEX_PTR is the offset into the input RS stream
+ * 0,1 are tex0
+ * 2,3 are tex1
+ */
+ OUT_RING_REG(R300_RS_IP_0,
+ (R300_RS_TEX_PTR(0) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+ OUT_RING_REG(R300_RS_IP_1,
+ (R300_RS_TEX_PTR(2) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+ /* src tex */
+ /* R300_INST_TEX_ID - select the RS source table entry
+ * R300_INST_TEX_ADDR - the FS temp register for the texture data
+ */
+ OUT_RING_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(0)));
+ /* mask tex */
+ OUT_RING_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(1)));
+
+ } else {
+ /* rasterizer source table
+ * R300_RS_TEX_PTR is the offset into the input RS stream
+ * 0,1 are tex0
+ * 2,3 are tex1
+ */
+ OUT_RING_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+
+ OUT_RING_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+ /* src tex */
+ /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry
+ * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data
+ */
+ OUT_RING_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
+ R500_RS_INST_TEX_CN_WRITE |
+ (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
+ /* mask tex */
+ OUT_RING_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
+ R500_RS_INST_TEX_CN_WRITE |
+ (1 << R500_RS_INST_TEX_ADDR_SHIFT)));
+ }
+ ADVANCE_RING();
+
+ if (IS_R300_3D)
+ BEGIN_RING(2*4);
+ else {
+ BEGIN_RING(2*6);
+ OUT_RING_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+ OUT_RING_REG(R500_US_FC_CTRL, 0);
+ }
+ OUT_RING_REG(R300_US_W_FMT, 0);
+ OUT_RING_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA));
+ OUT_RING_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA));
+ OUT_RING_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA));
+ ADVANCE_RING();
+
+
+ BEGIN_RING(2*3);
+ OUT_RING_REG(R300_FG_DEPTH_SRC, 0);
+ OUT_RING_REG(R300_FG_FOG_BLEND, 0);
+ OUT_RING_REG(R300_FG_ALPHA_FUNC, 0);
+ ADVANCE_RING();
+
+ BEGIN_RING(2*13);
+ OUT_RING_REG(R300_RB3D_ABLENDCNTL, 0);
+ OUT_RING_REG(R300_RB3D_ZSTENCILCNTL, 0);
+ OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
+ OUT_RING_REG(R300_RB3D_BW_CNTL, 0);
+ OUT_RING_REG(R300_RB3D_ZCNTL, 0);
+ OUT_RING_REG(R300_RB3D_ZTOP, 0);
+ OUT_RING_REG(R300_RB3D_ROPCNTL, 0);
+
+ OUT_RING_REG(R300_RB3D_AARESOLVE_CTL, 0);
+ OUT_RING_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN |
+ R300_GREEN_MASK_EN |
+ R300_RED_MASK_EN |
+ R300_ALPHA_MASK_EN));
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
+ OUT_RING_REG(R300_RB3D_CCTL, 0);
+ OUT_RING_REG(R300_RB3D_DITHER_CTL, 0);
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
+ ADVANCE_RING();
+
+ BEGIN_RING(2*5);
+ OUT_RING_REG(R300_SC_EDGERULE, 0xA5294A5);
+ if (IS_R300_3D) {
+ /* clip has offset 1440 */
+ OUT_RING_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) |
+ (1440 << R300_CLIP_Y_SHIFT)));
+ OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
+ (4080 << R300_CLIP_Y_SHIFT)));
+ } else {
+ OUT_RING_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
+ (0 << R300_CLIP_Y_SHIFT)));
+ OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
+ (4080 << R300_CLIP_Y_SHIFT)));
+ }
+ OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA);
+ OUT_RING_REG(R300_SC_SCREENDOOR, 0xffffff);
+ ADVANCE_RING();
+ } else if (IS_R200_3D) {
+
+ BEGIN_RING(2*6);
+ if (info->ChipFamily == CHIP_FAMILY_RS300) {
+ OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
+ } else {
+ OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, 0);
+ }
+ OUT_RING_REG(R200_PP_CNTL_X, 0);
+ OUT_RING_REG(R200_PP_TXMULTI_CTL_0, 0);
+ OUT_RING_REG(R200_SE_VTX_STATE_CNTL, 0);
+ OUT_RING_REG(R200_SE_VTE_CNTL, 0);
+ OUT_RING_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
+ R200_VAP_VF_MAX_VTX_NUM);
+ ADVANCE_RING();
+
+ BEGIN_RING(2*4);
+ OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, 0);
+ OUT_RING_REG(R200_RE_CNTL, 0);
+ OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
+ OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
+ RADEON_BFACE_SOLID |
+ RADEON_FFACE_SOLID |
+ RADEON_VTX_PIX_CENTER_OGL |
+ RADEON_ROUND_MODE_ROUND |
+ RADEON_ROUND_PREC_4TH_PIX));
+ ADVANCE_RING();
+ } else {
+ BEGIN_RING(2*2);
+ if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
+ (info->ChipFamily == CHIP_FAMILY_RV200))
+ OUT_RING_REG(RADEON_SE_CNTL_STATUS, 0);
+ else
+ OUT_RING_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
+ OUT_RING_REG(RADEON_SE_COORD_FMT,
+ RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
+ RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 |
+ RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 |
+ RADEON_TEX1_W_ROUTING_USE_W0);
+ ADVANCE_RING();
+
+ BEGIN_RING(2*2);
+ OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
+ OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
+ RADEON_BFACE_SOLID |
+ RADEON_FFACE_SOLID |
+ RADEON_VTX_PIX_CENTER_OGL |
+ RADEON_ROUND_MODE_ROUND |
+ RADEON_ROUND_PREC_4TH_PIX));
+ ADVANCE_RING();
+ }
+
+}
+
+/* inserts a wait for vline in the command stream */
+void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix,
+ xf86CrtcPtr crtc, int start, int stop)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ drmmode_crtc_private_ptr drmmode_crtc;
+
+ if (!crtc)
+ return;
+
+ if (!crtc->enabled)
+ return;
+
+ if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen))
+ return;
+
+ start = max(start, crtc->y);
+ stop = min(stop, crtc->y + crtc->mode.VDisplay);
+
+ if (start >= stop)
+ return;
+
+ if (!IS_AVIVO_VARIANT) {
+ /* on pre-r5xx vline starts at CRTC scanout */
+ start -= crtc->y;
+ stop -= crtc->y;
+ }
+
+ drmmode_crtc = crtc->driver_private;
+
+ BEGIN_RING(2*3);
+ if (IS_AVIVO_VARIANT) {
+ OUT_RING_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
+ ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
+ (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
+ AVIVO_D1MODE_VLINE_INV));
+ } else {
+ OUT_RING_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */
+ ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
+ (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
+ RADEON_CRTC_GUI_TRIG_VLINE_INV |
+ RADEON_CRTC_GUI_TRIG_VLINE_STALL));
+ }
+ OUT_RING_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
+ RADEON_ENG_DISPLAY_SELECT_CRTC0));
+
+ OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0));
+ OUT_RING(drmmode_crtc->mode_crtc->crtc_id);
+ ADVANCE_RING();
+}
+
+
void RADEONInit3DEngine(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
@@ -249,4 +1013,3 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn)
}
info->accel_state->XInited3D = TRUE;
}
-
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
deleted file mode 100644
index 6fa741f..0000000
--- a/src/radeon_commonfuncs.c
+++ /dev/null
@@ -1,816 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "ati_pciids_gen.h"
-
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-
-static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- uint32_t gb_tile_config, vap_cntl;
-
- info->accel_state->texW[0] = info->accel_state->texH[0] =
- info->accel_state->texW[1] = info->accel_state->texH[1] = 1;
-
- if (IS_R300_3D || IS_R500_3D) {
-
- gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
-
- switch(info->accel_state->num_gb_pipes) {
- case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
- case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
- case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
- default:
- case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
- }
-
- BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(4);
- OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
- OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
- R300_COLOR_ROUND_NEAREST));
- OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
- R300_ALPHA0_SHADING_GOURAUD |
- R300_RGB1_SHADING_GOURAUD |
- R300_ALPHA1_SHADING_GOURAUD |
- R300_RGB2_SHADING_GOURAUD |
- R300_ALPHA2_SHADING_GOURAUD |
- R300_RGB3_SHADING_GOURAUD |
- R300_ALPHA3_SHADING_GOURAUD));
- OUT_ACCEL_REG(R300_GA_OFFSET, 0);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(5);
- OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0);
- OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0);
- OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG);
- OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
- OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0);
- FINISH_ACCEL();
-
- /* setup the VAP */
- if (info->accel_state->has_tcl)
- vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (9 << R300_VF_MAX_VTX_NUM_SHIFT));
- else
- vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (5 << R300_VF_MAX_VTX_NUM_SHIFT));
-
- if ((info->ChipFamily == CHIP_FAMILY_R300) ||
- (info->ChipFamily == CHIP_FAMILY_R350))
- vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
- else if (info->ChipFamily == CHIP_FAMILY_RV530)
- vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
- else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
- (info->ChipFamily == CHIP_FAMILY_R420))
- vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
- else if ((info->ChipFamily == CHIP_FAMILY_R520) ||
- (info->ChipFamily == CHIP_FAMILY_R580) ||
- (info->ChipFamily == CHIP_FAMILY_RV560) ||
- (info->ChipFamily == CHIP_FAMILY_RV570))
- vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
- else
- vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
-
- if (info->accel_state->has_tcl)
- BEGIN_ACCEL(15);
- else
- BEGIN_ACCEL(9);
- OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0);
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
-
- if (info->accel_state->has_tcl)
- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
- else
- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
- OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl);
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
- OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
-
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_1_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_2_SHIFT)));
-
- if (info->accel_state->has_tcl) {
- OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
- OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
- }
- FINISH_ACCEL();
-
- /* pre-load the vertex shaders */
- if (info->accel_state->has_tcl) {
- BEGIN_ACCEL(37);
- /* exa composite shader program */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0));
- /* PVS inst 0 - dst X,Y */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(0) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 1 - src X */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
- R300_PVS_DST_OFFSET(0) |
- R300_PVS_DST_WE_X));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 2 - src Y */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
- R300_PVS_DST_OFFSET(0) |
- R300_PVS_DST_WE_Y));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
- R300_PVS_SRC_OFFSET(1) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 3 - src X / w */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(1) |
- R300_PVS_DST_WE_X));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 4 - src y / h */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(1) |
- R300_PVS_DST_WE_Y));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
- R300_PVS_SRC_OFFSET(1) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 5 - mask X */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
- R300_PVS_DST_OFFSET(0) |
- R300_PVS_DST_WE_Z));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(7) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
- R300_PVS_SRC_OFFSET(2) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(7) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 6 - mask Y */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
- R300_PVS_DST_OFFSET(0) |
- R300_PVS_DST_WE_W));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(7) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
- R300_PVS_SRC_OFFSET(3) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(7) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 7 - mask X / w */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(2) |
- R300_PVS_DST_WE_X));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
- R300_PVS_SRC_OFFSET(2) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 8 - mask y / h */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(2) |
- R300_PVS_DST_WE_Y));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
- R300_PVS_SRC_OFFSET(3) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- FINISH_ACCEL();
-
- /* Xv shader program */
- BEGIN_ACCEL(9);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(9));
-
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(0) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(1) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- FINISH_ACCEL();
-
- /* Xv bicubic shader program */
- BEGIN_ACCEL(13);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(11));
- /* PVS inst 0 */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(0) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 1 */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(1) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(6) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 2 */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(2) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(7) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(7) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(7) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- FINISH_ACCEL();
- }
-
- /* pre-load the RS instructions */
- BEGIN_ACCEL(4);
- if (IS_R300_3D) {
- /* rasterizer source table
- * R300_RS_TEX_PTR is the offset into the input RS stream
- * 0,1 are tex0
- * 2,3 are tex1
- */
- OUT_ACCEL_REG(R300_RS_IP_0,
- (R300_RS_TEX_PTR(0) |
- R300_RS_SEL_S(R300_RS_SEL_C0) |
- R300_RS_SEL_T(R300_RS_SEL_C1) |
- R300_RS_SEL_R(R300_RS_SEL_K0) |
- R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_ACCEL_REG(R300_RS_IP_1,
- (R300_RS_TEX_PTR(2) |
- R300_RS_SEL_S(R300_RS_SEL_C0) |
- R300_RS_SEL_T(R300_RS_SEL_C1) |
- R300_RS_SEL_R(R300_RS_SEL_K0) |
- R300_RS_SEL_Q(R300_RS_SEL_K1)));
- /* src tex */
- /* R300_INST_TEX_ID - select the RS source table entry
- * R300_INST_TEX_ADDR - the FS temp register for the texture data
- */
- OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
- R300_RS_INST_TEX_CN_WRITE |
- R300_INST_TEX_ADDR(0)));
- /* mask tex */
- OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
- R300_RS_INST_TEX_CN_WRITE |
- R300_INST_TEX_ADDR(1)));
-
- } else {
- /* rasterizer source table
- * R300_RS_TEX_PTR is the offset into the input RS stream
- * 0,1 are tex0
- * 2,3 are tex1
- */
- OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
- (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
- (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
- (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
-
- OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
- (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
- (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
- (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
- /* src tex */
- /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry
- * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data
- */
- OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
- R500_RS_INST_TEX_CN_WRITE |
- (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
- /* mask tex */
- OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
- R500_RS_INST_TEX_CN_WRITE |
- (1 << R500_RS_INST_TEX_ADDR_SHIFT)));
- }
- FINISH_ACCEL();
-
- if (IS_R300_3D)
- BEGIN_ACCEL(4);
- else {
- BEGIN_ACCEL(6);
- OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
- OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
- }
- OUT_ACCEL_REG(R300_US_W_FMT, 0);
- OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
- R300_OUT_FMT_C0_SEL_BLUE |
- R300_OUT_FMT_C1_SEL_GREEN |
- R300_OUT_FMT_C2_SEL_RED |
- R300_OUT_FMT_C3_SEL_ALPHA));
- OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED |
- R300_OUT_FMT_C0_SEL_BLUE |
- R300_OUT_FMT_C1_SEL_GREEN |
- R300_OUT_FMT_C2_SEL_RED |
- R300_OUT_FMT_C3_SEL_ALPHA));
- OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED |
- R300_OUT_FMT_C0_SEL_BLUE |
- R300_OUT_FMT_C1_SEL_GREEN |
- R300_OUT_FMT_C2_SEL_RED |
- R300_OUT_FMT_C3_SEL_ALPHA));
- FINISH_ACCEL();
-
-
- BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0);
- OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0);
- OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(13);
- OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
- OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0);
- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
- OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0);
- OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0);
- OUT_ACCEL_REG(R300_RB3D_ZTOP, 0);
- OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0);
-
- OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0);
- OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN |
- R300_GREEN_MASK_EN |
- R300_RED_MASK_EN |
- R300_ALPHA_MASK_EN));
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- OUT_ACCEL_REG(R300_RB3D_CCTL, 0);
- OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(5);
- OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
- if (IS_R300_3D) {
- /* clip has offset 1440 */
- OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) |
- (1440 << R300_CLIP_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
- (4080 << R300_CLIP_Y_SHIFT)));
- } else {
- OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
- (0 << R300_CLIP_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
- (4080 << R300_CLIP_Y_SHIFT)));
- }
- OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
- OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
- FINISH_ACCEL();
- } else if (IS_R200_3D) {
-
- BEGIN_ACCEL(6);
- if (info->ChipFamily == CHIP_FAMILY_RS300) {
- OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
- } else {
- OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
- }
- OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
- OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
- OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
- OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0);
- OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
- R200_VAP_VF_MAX_VTX_NUM);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(4);
- OUT_ACCEL_REG(R200_RE_AUX_SCISSOR_CNTL, 0);
- OUT_ACCEL_REG(R200_RE_CNTL, 0);
- OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
- OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
- RADEON_BFACE_SOLID |
- RADEON_FFACE_SOLID |
- RADEON_VTX_PIX_CENTER_OGL |
- RADEON_ROUND_MODE_ROUND |
- RADEON_ROUND_PREC_4TH_PIX));
- FINISH_ACCEL();
- } else {
- BEGIN_ACCEL(2);
- if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
- (info->ChipFamily == CHIP_FAMILY_RV200))
- OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
- else
- OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
- OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
- RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
- RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 |
- RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 |
- RADEON_TEX1_W_ROUTING_USE_W0);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(2);
- OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
- OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
- RADEON_BFACE_SOLID |
- RADEON_FFACE_SOLID |
- RADEON_VTX_PIX_CENTER_OGL |
- RADEON_ROUND_MODE_ROUND |
- RADEON_ROUND_PREC_4TH_PIX));
- FINISH_ACCEL();
- }
-
-}
-
-/* inserts a wait for vline in the command stream */
-void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
- xf86CrtcPtr crtc, int start, int stop)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- drmmode_crtc_private_ptr drmmode_crtc;
-
- if (!crtc)
- return;
-
- if (!crtc->enabled)
- return;
-
- if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen))
- return;
-
- start = max(start, crtc->y);
- stop = min(stop, crtc->y + crtc->mode.VDisplay);
-
- if (start >= stop)
- return;
-
- if (!IS_AVIVO_VARIANT) {
- /* on pre-r5xx vline starts at CRTC scanout */
- start -= crtc->y;
- stop -= crtc->y;
- }
-
- drmmode_crtc = crtc->driver_private;
-
- BEGIN_ACCEL(3);
- if (IS_AVIVO_VARIANT) {
- OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
- ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
- (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
- AVIVO_D1MODE_VLINE_INV));
- } else {
- OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */
- ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
- (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
- RADEON_CRTC_GUI_TRIG_VLINE_INV |
- RADEON_CRTC_GUI_TRIG_VLINE_STALL));
- }
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
- RADEON_ENG_DISPLAY_SELECT_CRTC0));
-
- OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0));
- OUT_RING(drmmode_crtc->mode_crtc->crtc_id);
- FINISH_ACCEL();
-}
-
commit 29dd3f84eecd2892a438f004403521de8986a91d
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jun 15 16:11:03 2012 +0100
radeon: misc cleanups.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 6adb518..4e24053 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -170,8 +170,6 @@ int radeon_cs_space_remaining(ScrnInfoPtr pScrn)
#undef OUT_ACCEL_REG
#undef FINISH_ACCEL
-#define RADEON_IB_RESERVE (16 * sizeof(uint32_t))
-
void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap)
{
switch(swap) {
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 49865ac..548aced 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -94,10 +94,6 @@
#include "shadow.h"
/* vgaHW definitions */
-#ifdef WITH_VGAHW
-#include "vgaHW.h"
-#endif
-
#ifdef HAVE_XEXTPROTO_71
#include <X11/extensions/dpmsconst.h>
#else
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 52f78a4..cdd962b 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -16,8 +16,6 @@
#include "xf86.h"
#include "dixstruct.h"
-#include "atipciids.h"
-#include "xf86fbman.h"
/* DPMS */
#ifdef HAVE_XEXTPROTO_71
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