xf86-video-intel: 2 commits - src/sna/sna_accel.c src/sna/sna_dri.c

[Chris Wilson]

 src/sna/sna_accel.c |    2 +-
 src/sna/sna_dri.c   |   19 -------------------
 2 files changed, 1 insertion(+), 20 deletions(-)

New commits:
commit 40e0cf32a25e43e16184b2af87a1e1abeb8e4052
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Sat Jul 21 19:43:23 2012 +0100

    sna/dri: We fail at predicting the flip frame
    
    Simply report the values from the kernel, and transfer the blame...
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/sna_dri.c b/src/sna/sna_dri.c
index cfb9d98..9698247 100644
--- a/src/sna/sna_dri.c
+++ b/src/sna/sna_dri.c
@@ -71,7 +71,6 @@ struct sna_dri_frame_event {
 	DrawablePtr draw;
 	ClientPtr client;
 	enum frame_event_type type;
-	unsigned frame;
 	int pipe;
 	int count;
 
@@ -1300,18 +1299,6 @@ static void sna_dri_flip_event(struct sna *sna,
 	/* We assume our flips arrive in order, so we don't check the frame */
 	switch (flip->type) {
 	case DRI2_FLIP:
-		/* Deliver cached msc, ust from reference crtc */
-		/* Check for too small vblank count of pageflip completion,
-		 * taking wraparound * into account. This usually means some
-		 * defective kms pageflip completion, causing wrong (msc, ust)
-		 * return values and possible visual corruption.
-		 */
-		if (flip->fe_frame < flip->frame &&
-		    flip->frame - flip->fe_frame < 5) {
-			/* All-0 values signal timestamping failure. */
-			flip->fe_frame = flip->fe_tv_sec = flip->fe_tv_usec = 0;
-		}
-
 		DBG(("%s: flip complete\n", __FUNCTION__));
 		DRI2SwapComplete(flip->client, draw,
 				 flip->fe_frame,
@@ -1596,8 +1583,6 @@ sna_dri_schedule_flip(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
 			sna_dri_frame_event_info_free(sna, draw, info);
 			return false;
 		}
-
-		info->frame = *target_msc;
 	}
 
 	return true;
@@ -1812,7 +1797,6 @@ sna_dri_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
 		     (int)*target_msc,
 		     (int)divisor));
 
-		info->frame = *target_msc;
 		info->type = DRI2_SWAP;
 
 		vbl.request.type =
@@ -1861,7 +1845,6 @@ sna_dri_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
 		goto blit_fallback;
 
 	*target_msc = vbl.reply.sequence;
-	info->frame = *target_msc;
 	return TRUE;
 
 blit_fallback:
@@ -2102,7 +2085,6 @@ sna_dri_schedule_wait_msc(ClientPtr client, DrawablePtr draw, CARD64 target_msc,
 		if (sna_wait_vblank(sna, &vbl))
 			goto out_free_info;
 
-		info->frame = vbl.reply.sequence;
 		DRI2BlockClient(client, draw);
 		return TRUE;
 	}
@@ -2130,7 +2112,6 @@ sna_dri_schedule_wait_msc(ClientPtr client, DrawablePtr draw, CARD64 target_msc,
 	if (sna_wait_vblank(sna, &vbl))
 		goto out_free_info;
 
-	info->frame = vbl.reply.sequence;
 	DRI2BlockClient(client, draw);
 	return TRUE;
 
commit c6e316eeba3008b351f2cd63829154f4672c5417
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Sat Jul 21 18:18:32 2012 +0100

    sna: Adjust hints to prefer rendering convex polygon with the GPU
    
    Keep the general polygons as only using the GPU if necessary, until the
    cost of the routines is analysed.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 5bec59a..0b0a304 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -9274,7 +9274,7 @@ sna_poly_fill_polygon(DrawablePtr draw, GCPtr gc,
 		goto fallback;
 
 	if ((data.bo = sna_drawable_use_bo(draw,
-					   use_wide_spans(draw, gc, &data.region.extents),
+					   (shape == Convex ? use_zero_spans : use_wide_spans)(draw, gc, &data.region.extents),
 					   &data.region.extents,
 					   &data.damage))) {
 		uint32_t color;