intel-gen4asm: Changes to 'master'

[Haihao Xiang]

 src/brw_structs.h |   20 +++++++++--------
 src/disasm.c      |    6 ++---
 src/gen4asm.h     |    3 +-
 src/gram.y        |   63 +++++++++++++++++++++++++++++++++++++++++++-----------
 src/lex.l         |   14 +++---------
 5 files changed, 71 insertions(+), 35 deletions(-)

New commits:
commit e51e9599a7933e6ffd6070aca5a92124ec879280
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Tue Jul 17 16:16:11 2012 +0800

    Waring if both predication and conditional modifier are enabled but use different flag registers
    
    Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>

commit a7f56c6fe170d6cc9b003efb038230e0c19779bb
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Tue Jul 17 15:05:31 2012 +0800

    Add support for flag register f1 on Ivy bridge
    
    Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>

commit 0bcd6be950acddee3aa1847d861c5f492a5c5382
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Tue Jul 17 14:18:54 2012 +0800

    s/flag_reg_nr/flag_subreg_nr for an instruction
    s/flagreg/flag_subreg_nr for a condition
    
    They are flag subregister number indeed
    
    Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>

commit 1abb2733843ddc173b8892c31b55670bbd69a349
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Tue Jul 17 14:01:54 2012 +0800

    Remove flag_reg_nr from the DW3 of an instruction
    
    Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>

commit 2e66e2f932b85f71d257165aebcd9abac80bd4f1
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Tue Jul 17 13:46:59 2012 +0800

    Change the rule for flag register
    
    The shift/reduce conflict mentioned in the comment has been fixed, so
    flagreg can return the reg number in the lvalue now. In addition, it will
    be easy to add support for flag register f1 on Ivy bridge
    
    Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>