xf86-video-intel: src/sna/kgem.c src/sna/kgem.h src/sna/sna_io.c src/sna/sna_tiling.c

[Chris Wilson]

 src/sna/kgem.c       |   14 +++++++++-----
 src/sna/kgem.h       |    3 ++-
 src/sna/sna_io.c     |    6 +++---
 src/sna/sna_tiling.c |    6 +++---
 4 files changed, 17 insertions(+), 12 deletions(-)

New commits:
commit 0a748fc49d60dc2bc9494f95c4934592b111831a
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Jan 31 10:51:02 2012 +0000

    sna: Split the tiling limits between upload and copying
    
    The kernel has a bug that prevents pwriting buffers large than the
    aperture. Whilst waiting for the fix, limit the upload where possible to
    fit within that constraint.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index 311bac4..cccdd59 100644
--- a/src/sna/kgem.c
+++ b/src/sna/kgem.c
@@ -692,9 +692,13 @@ void kgem_init(struct kgem *kgem, int fd, struct pci_device *dev, int gen)
 	if (kgem->max_gpu_size > kgem->max_cpu_size)
 		kgem->max_gpu_size = kgem->max_cpu_size;
 
-	kgem->max_tile_size = MAX_CACHE_SIZE;
-	if (kgem->max_tile_size > kgem->max_gpu_size / 2)
-		kgem->max_tile_size = kgem->max_gpu_size / 2;
+	kgem->max_upload_tile_size = kgem->aperture_mappable / 2;
+	if (kgem->max_upload_tile_size > kgem->max_gpu_size / 2)
+		kgem->max_upload_tile_size = kgem->max_gpu_size / 2;
+
+	kgem->max_copy_tile_size = (MAX_CACHE_SIZE + 1)/2;
+	if (kgem->max_copy_tile_size > kgem->max_gpu_size / 2)
+		kgem->max_copy_tile_size = kgem->max_gpu_size / 2;
 
 	totalram = total_ram_size();
 	if (totalram == 0) {
@@ -3197,9 +3201,9 @@ struct kgem_bo *kgem_create_buffer(struct kgem *kgem,
 #if !DBG_NO_MAP_UPLOAD
 	/* Be a little more generous and hope to hold fewer mmappings */
 	alloc = ALIGN(2*size, kgem->partial_buffer_size);
-	if (alloc > kgem->max_tile_size)
+	if (alloc > MAX_CACHE_SIZE)
 		alloc = ALIGN(size, kgem->partial_buffer_size);
-	if (alloc > kgem->max_tile_size)
+	if (alloc > MAX_CACHE_SIZE)
 		alloc = PAGE_ALIGN(size);
 	alloc /= PAGE_SIZE;
 	if (kgem->has_cpu_bo) {
diff --git a/src/sna/kgem.h b/src/sna/kgem.h
index 87dc386..974a716 100644
--- a/src/sna/kgem.h
+++ b/src/sna/kgem.h
@@ -161,7 +161,8 @@ struct kgem {
 	uint32_t aperture_total, aperture_high, aperture_low, aperture_mappable;
 	uint32_t aperture, aperture_fenced;
 	uint32_t min_alignment;
-	uint32_t max_tile_size, max_gpu_size, max_cpu_size;
+	uint32_t max_upload_tile_size, max_copy_tile_size;
+	uint32_t max_gpu_size, max_cpu_size;
 	uint32_t large_object_size, max_object_size;
 	uint32_t partial_buffer_size;
 
diff --git a/src/sna/sna_io.c b/src/sna/sna_io.c
index f4278be..eb5df9d 100644
--- a/src/sna/sna_io.c
+++ b/src/sna/sna_io.c
@@ -61,7 +61,7 @@ box_intersect(BoxPtr a, const BoxRec *b)
 
 static inline bool upload_too_large(struct sna *sna, int width, int height)
 {
-	return width * height * 4 > sna->kgem.max_tile_size;
+	return width * height * 4 > sna->kgem.max_upload_tile_size;
 }
 
 static inline bool must_tile(struct sna *sna, int width, int height)
@@ -209,7 +209,7 @@ fallback:
 
 			step = MIN(sna->render.max_3d_size,
 				   8*(MAXSHORT&~63) / dst->drawable.bitsPerPixel);
-			while (step * step * 4 > sna->kgem.max_tile_size)
+			while (step * step * 4 > sna->kgem.max_upload_tile_size)
 				step /= 2;
 
 			DBG(("%s: tiling download, using %dx%d tiles\n",
@@ -595,7 +595,7 @@ fallback:
 tile:
 			step = MIN(sna->render.max_3d_size,
 				   8*(MAXSHORT&~63) / dst->drawable.bitsPerPixel);
-			while (step * step * 4 > sna->kgem.max_tile_size)
+			while (step * step * 4 > sna->kgem.max_upload_tile_size)
 				step /= 2;
 
 			DBG(("%s: tiling upload, using %dx%d tiles\n",
diff --git a/src/sna/sna_tiling.c b/src/sna/sna_tiling.c
index a3bf19d..702192a 100644
--- a/src/sna/sna_tiling.c
+++ b/src/sna/sna_tiling.c
@@ -144,7 +144,7 @@ sna_tiling_composite_done(struct sna *sna,
 	step = sna->render.max_3d_size;
 	if (tile->dst_x & (8*512 / tile->dst->pDrawable->bitsPerPixel - 1))
 		step /= 2;
-	while (step * step * 4 > sna->kgem.max_tile_size)
+	while (step * step * 4 > sna->kgem.max_copy_tile_size)
 		step /= 2;
 
 	DBG(("%s -- %dx%d, count=%d, step size=%d\n", __FUNCTION__,
@@ -331,7 +331,7 @@ sna_tiling_fill_boxes(struct sna *sna,
 	pixman_region_init_rects(&region, box, n);
 
 	step = sna->render.max_3d_size;
-	while (step * step * 4 > sna->kgem.max_tile_size)
+	while (step * step * 4 > sna->kgem.max_copy_tile_size)
 		step /= 2;
 
 	DBG(("%s (op=%d, format=%x, color=(%04x,%04x,%04x, %04x), tile.size=%d, box=%dx[(%d, %d), (%d, %d)])\n",
@@ -444,7 +444,7 @@ Bool sna_tiling_copy_boxes(struct sna *sna, uint8_t alu,
 	pixman_region_init_rects(&region, box, nbox);
 
 	step = sna->render.max_3d_size;
-	while (step * step * 4 > sna->kgem.max_tile_size)
+	while (step * step * 4 > sna->kgem.max_copy_tile_size)
 		step /= 2;
 
 	DBG(("%s (alu=%d), tile.size=%d, box=%dx[(%d, %d), (%d, %d)])\n",