xf86-video-intel: src/intel_uxa.c

[Chris Wilson]

 src/intel_uxa.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

New commits:
commit 736b89504a32239a0c7dfb5961c1b8292dd744bd
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Sun Dec 30 10:32:18 2012 +0000

    uxa: Align surface allocations to even tile rows
    
    Align surface sizes to an even number of tile rows to cater for sampler
    prefetch. If we read beyond the last page we may catch the PTE in a
    state of flux and trigger a GPU hang. Also detected by enabling invalid
    PTE access checking.
    
    References: https://bugs.freedesktop.org/show_bug.cgi?id=56916
    References: https://bugs.freedesktop.org/show_bug.cgi?id=55984
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/intel_uxa.c b/src/intel_uxa.c
index f5ac0a6..2f14173 100644
--- a/src/intel_uxa.c
+++ b/src/intel_uxa.c
@@ -209,7 +209,7 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap,
 			tile_height = 8;
 		else
 			tile_height = 32;
-		aligned_h = ALIGN(h, tile_height);
+		aligned_h = ALIGN(h, 2*tile_height);
 
 		*stride = intel_get_fence_pitch(intel,
 						ALIGN(pitch, 512),