xf86-video-intel: src/intel_uxa.c

[Daniel Vetter]

 src/intel_uxa.c |    7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

New commits:
commit f660df2cb44b310740ed850037ff37891b671f28
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date:   Tue Mar 29 18:02:24 2011 +0200

    Cleanup gen2 tiling confusion
    
    A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.
    
    Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
    Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

diff --git a/src/intel_uxa.c b/src/intel_uxa.c
index 13d8cf9..662bcc7 100644
--- a/src/intel_uxa.c
+++ b/src/intel_uxa.c
@@ -197,13 +197,12 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap,
 	if (*tiling != I915_TILING_NONE) {
 		int aligned_h, tile_height;
 
-		if (*tiling == I915_TILING_X)
+		if (IS_GEN2(intel))
+			tile_height = 16;
+		else if (*tiling == I915_TILING_X)
 			tile_height = 8;
 		else
 			tile_height = 32;
-		/* i8xx has a 2-row interleaved tile layout */
-		if (IS_GEN2(intel))
-			tile_height *= 2;
 		aligned_h = ALIGN(h, tile_height);
 
 		*stride = intel_get_fence_pitch(intel,