xf86-video-intel: 5 commits - configure.ac src/brw_structs.h src/i965_reg.h src/i965_video.c src/render_program/exa_wm_affine.g6i src/render_program/exa_wm_mask_affine.g6a src/render_program/exa_wm_sample_planar.g4i src/render_program/exa_wm_src_affine.g6a src/render_program/exa_wm_src_affine.g7a src/render_program/exa_wm_src_affine.g7b src/render_program/exa_wm_src_sample_argb.g4a src/render_program/exa_wm_src_sample_argb.g4i src/render_program/exa_wm_src_sample_argb.g7a src/render_program/exa_wm_src_sample_argb.g7b src/render_program/exa_wm_src_sample_planar.g4a src/render_program/exa_wm_src_sample_planar.g7a src/render_program/exa_wm_src_sample_planar.g7b src/render_program/exa_wm_write.g6a src/render_program/exa_wm_write.g6i src/render_program/exa_wm_write.g7a src/render_program/exa_wm_write.g7b src/render_program/exa_wm_yuv_rgb.g7a src/render_program/exa_wm_yuv_rgb.g7b src/render_program/Makefile.am
Haihao Xiang
haihao at kemper.freedesktop.org
Thu Jun 23 19:43:30 PDT 2011
configure.ac | 2
src/brw_structs.h | 124 ++++
src/i965_reg.h | 132 +++++
src/i965_video.c | 632 ++++++++++++++++++++++--
src/render_program/Makefile.am | 38 +
src/render_program/exa_wm_affine.g6i | 35 +
src/render_program/exa_wm_mask_affine.g6a | 8
src/render_program/exa_wm_sample_planar.g4i | 64 ++
src/render_program/exa_wm_src_affine.g6a | 8
src/render_program/exa_wm_src_affine.g7a | 41 +
src/render_program/exa_wm_src_affine.g7b | 4
src/render_program/exa_wm_src_sample_argb.g4a | 18
src/render_program/exa_wm_src_sample_argb.g4i | 44 +
src/render_program/exa_wm_src_sample_argb.g7a | 38 +
src/render_program/exa_wm_src_sample_argb.g7b | 3
src/render_program/exa_wm_src_sample_planar.g4a | 36 -
src/render_program/exa_wm_src_sample_planar.g7a | 38 +
src/render_program/exa_wm_src_sample_planar.g7b | 5
src/render_program/exa_wm_write.g6a | 38 -
src/render_program/exa_wm_write.g6i | 61 ++
src/render_program/exa_wm_write.g7a | 41 +
src/render_program/exa_wm_write.g7b | 17
src/render_program/exa_wm_yuv_rgb.g7a | 1
src/render_program/exa_wm_yuv_rgb.g7b | 12
24 files changed, 1292 insertions(+), 148 deletions(-)
New commits:
commit 312460ea69792594fe9acca8591ead55baea7d99
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Thu Jun 23 00:20:03 2011 +0800
Xv: set up pipeline for Xv on Ivybridge
The configuration is same as that on Sandybridge, but
many state commands are changed
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/src/i965_reg.h b/src/i965_reg.h
index df41fba..ab6c020 100644
--- a/src/i965_reg.h
+++ b/src/i965_reg.h
@@ -136,6 +136,138 @@
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1)
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1)
+/* on GEN7+ */
+/* _3DSTATE_VERTEX_BUFFERS on GEN7*/
+/* DW1 */
+#define GEN7_VB0_ADDRESS_MODIFYENABLE (1 << 14)
+
+/* _3DPRIMITIVE on GEN7 */
+/* DW1 */
+# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8)
+# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 8)
+
+/* 3DSTATE_WM on GEN7 */
+/* DW1 */
+# define GEN7_WM_STATISTICS_ENABLE (1 << 31)
+# define GEN7_WM_DEPTH_CLEAR (1 << 30)
+# define GEN7_WM_DISPATCH_ENABLE (1 << 29)
+# define GEN6_WM_DEPTH_RESOLVE (1 << 28)
+# define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27)
+# define GEN7_WM_KILL_ENABLE (1 << 25)
+# define GEN7_WM_PSCDEPTH_OFF (0 << 23)
+# define GEN7_WM_PSCDEPTH_ON (1 << 23)
+# define GEN7_WM_PSCDEPTH_ON_GE (2 << 23)
+# define GEN7_WM_PSCDEPTH_ON_LE (3 << 23)
+# define GEN7_WM_USES_SOURCE_DEPTH (1 << 20)
+# define GEN7_WM_USES_SOURCE_W (1 << 19)
+# define GEN7_WM_POSITION_ZW_PIXEL (0 << 17)
+# define GEN7_WM_POSITION_ZW_CENTROID (2 << 17)
+# define GEN7_WM_POSITION_ZW_SAMPLE (3 << 17)
+# define GEN7_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 16)
+# define GEN7_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 15)
+# define GEN7_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 14)
+# define GEN7_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 13)
+# define GEN7_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 12)
+# define GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 11)
+# define GEN7_WM_USES_INPUT_COVERAGE_MASK (1 << 10)
+# define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 8)
+# define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 8)
+# define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 8)
+# define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 8)
+# define GEN7_WM_LINE_AA_WIDTH_0_5 (0 << 6)
+# define GEN7_WM_LINE_AA_WIDTH_1_0 (1 << 6)
+# define GEN7_WM_LINE_AA_WIDTH_2_0 (2 << 6)
+# define GEN7_WM_LINE_AA_WIDTH_4_0 (3 << 6)
+# define GEN7_WM_POLYGON_STIPPLE_ENABLE (1 << 4)
+# define GEN7_WM_LINE_STIPPLE_ENABLE (1 << 3)
+# define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 2)
+# define GEN7_WM_MSRAST_OFF_PIXEL (0 << 0)
+# define GEN7_WM_MSRAST_OFF_PATTERN (1 << 0)
+# define GEN7_WM_MSRAST_ON_PIXEL (2 << 0)
+# define GEN7_WM_MSRAST_ON_PATTERN (3 << 0)
+/* DW2 */
+# define GEN7_WM_MSDISPMODE_PERPIXEL (1 << 31)
+
+#define GEN7_3DSTATE_CLEAR_PARAMS BRW_3D(3, 0, 0x04)
+#define GEN7_3DSTATE_DEPTH_BUFFER BRW_3D(3, 0, 0x05)
+
+#define GEN7_3DSTATE_CONSTANT_HS BRW_3D(3, 0, 0x19)
+#define GEN7_3DSTATE_CONSTANT_DS BRW_3D(3, 0, 0x1a)
+
+#define GEN7_3DSTATE_HS BRW_3D(3, 0, 0x1b)
+#define GEN7_3DSTATE_TE BRW_3D(3, 0, 0x1c)
+#define GEN7_3DSTATE_DS BRW_3D(3, 0, 0x1d)
+#define GEN7_3DSTATE_STREAMOUT BRW_3D(3, 0, 0x1e)
+#define GEN7_3DSTATE_SBE BRW_3D(3, 0, 0x1f)
+
+/* DW1 */
+# define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28)
+# define GEN7_SBE_NUM_OUTPUTS_SHIFT 22
+# define GEN7_SBE_SWIZZLE_ENABLE (1 << 21)
+# define GEN7_SBE_POINT_SPRITE_LOWERLEFT (1 << 20)
+# define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11
+# define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4
+
+#define GEN7_3DSTATE_PS BRW_3D(3, 0, 0x20)
+/* DW1: kernel pointer */
+/* DW2 */
+# define GEN7_PS_SPF_MODE (1 << 31)
+# define GEN7_PS_VECTOR_MASK_ENABLE (1 << 30)
+# define GEN7_PS_SAMPLER_COUNT_SHIFT 27
+# define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
+# define GEN7_PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16)
+# define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16)
+/* DW3: scratch space */
+/* DW4 */
+# define GEN7_PS_MAX_THREADS_SHIFT 23
+# define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11)
+# define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10)
+# define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9)
+# define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE (1 << 7)
+# define GEN7_PS_POSOFFSET_NONE (0 << 3)
+# define GEN7_PS_POSOFFSET_CENTROID (2 << 3)
+# define GEN7_PS_POSOFFSET_SAMPLE (3 << 3)
+# define GEN7_PS_32_DISPATCH_ENABLE (1 << 2)
+# define GEN7_PS_16_DISPATCH_ENABLE (1 << 1)
+# define GEN7_PS_8_DISPATCH_ENABLE (1 << 0)
+/* DW5 */
+# define GEN7_PS_DISPATCH_START_GRF_SHIFT_0 16
+# define GEN7_PS_DISPATCH_START_GRF_SHIFT_1 8
+# define GEN7_PS_DISPATCH_START_GRF_SHIFT_2 0
+/* DW6: kernel 1 pointer */
+/* DW7: kernel 2 pointer */
+
+#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL BRW_3D(3, 0, 0x21)
+#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC BRW_3D(3, 0, 0x23)
+
+#define GEN7_3DSTATE_BLEND_STATE_POINTERS BRW_3D(3, 0, 0x24)
+#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS BRW_3D(3, 0, 0x25)
+
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS BRW_3D(3, 0, 0x26)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS BRW_3D(3, 0, 0x27)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS BRW_3D(3, 0, 0x28)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS BRW_3D(3, 0, 0x29)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS BRW_3D(3, 0, 0x2a)
+
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS BRW_3D(3, 0, 0x2b)
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS BRW_3D(3, 0, 0x2e)
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS BRW_3D(3, 0, 0x2f)
+
+#define GEN7_3DSTATE_URB_VS BRW_3D(3, 0, 0x30)
+#define GEN7_3DSTATE_URB_HS BRW_3D(3, 0, 0x31)
+#define GEN7_3DSTATE_URB_DS BRW_3D(3, 0, 0x32)
+#define GEN7_3DSTATE_URB_GS BRW_3D(3, 0, 0x33)
+/* DW1 */
+# define GEN7_URB_ENTRY_NUMBER_SHIFT 0
+# define GEN7_URB_ENTRY_SIZE_SHIFT 16
+# define GEN7_URB_STARTING_ADDRESS_SHIFT 25
+
+#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS BRW_3D(3, 1, 0x12)
+#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS BRW_3D(3, 1, 0x16)
+/* DW1 */
+# define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16
+
+
#define PIPELINE_SELECT_3D 0
#define PIPELINE_SELECT_MEDIA 1
diff --git a/src/i965_video.c b/src/i965_video.c
index 84230a1..1054914 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -1445,6 +1445,7 @@ gen6_create_blend_state(ScrnInfoPtr scrn)
blend_state->blend1.logic_op_enable = 1;
blend_state->blend1.logic_op_func = 0xc;
+ blend_state->blend1.pre_blend_clamp_enable = 1;
drm_intel_bo_unmap(blend_bo);
return blend_bo;
@@ -1811,8 +1812,44 @@ gen6_upload_vertex_element_state(ScrnInfoPtr scrn)
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
}
+static void
+gen6_upload_vertex_buffer(ScrnInfoPtr scrn, drm_intel_bo *vertex_bo, uint32_t end_address_offset)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ /* Set up the pointer to our vertex buffer */
+ OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+ /* four 32-bit floats per vertex */
+ OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
+ GEN6_VB0_VERTEXDATA |
+ ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
+ OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
+ OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, end_address_offset);
+ OUT_BATCH(0); /* reserved */
+}
+
static void
-gen6_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_table_bo, int n_src_surf, PixmapPtr pixmap)
+gen6_upload_primitive(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(BRW_3DPRIMITIVE |
+ BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL |
+ (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) |
+ (0 << 9) | /* Internal Vertex Count */
+ (6 - 2));
+ OUT_BATCH(3); /* vertex count per instance */
+ OUT_BATCH(0); /* start vertex offset */
+ OUT_BATCH(1); /* single instance */
+ OUT_BATCH(0); /* start instance location */
+ OUT_BATCH(0); /* index buffer offset, ignored */
+}
+
+static void
+gen6_emit_video_setup(ScrnInfoPtr scrn,
+ drm_intel_bo *surface_state_binding_table_bo, int n_src_surf,
+ PixmapPtr pixmap,
+ drm_intel_bo *vertex_bo, uint32_t end_address_offset)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
@@ -1835,6 +1872,382 @@ gen6_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_tabl
gen6_upload_depth_buffer_state(scrn);
gen6_upload_drawing_rectangle(scrn, pixmap);
gen6_upload_vertex_element_state(scrn);
+ gen6_upload_vertex_buffer(scrn, vertex_bo, end_address_offset);
+ gen6_upload_primitive(scrn);
+}
+
+static void
+gen7_upload_invarient_states(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
+ OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
+ BRW_PIPE_CONTROL_WC_FLUSH |
+ BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ BRW_PIPE_CONTROL_NOWRITE);
+ OUT_BATCH(0); /* write address */
+ OUT_BATCH(0); /* write data */
+
+ OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
+ GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
+ OUT_BATCH(1);
+
+ /* Set system instruction pointer */
+ OUT_BATCH(BRW_STATE_SIP | 0);
+ OUT_BATCH(0);
+}
+
+static void
+gen7_upload_viewport_state_pointers(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
+ OUT_RELOC(intel->video.gen4_cc_vp_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+
+ OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
+ OUT_BATCH(0);
+}
+
+/*
+ * URB layout for Xv on GEN7
+ * ----------------------------------------
+ * | PS Push Constants (8KB) | VS entries |
+ * ----------------------------------------
+ */
+static void
+gen7_upload_urb(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
+ OUT_BATCH(8); /* in 1KBs */
+
+ OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
+ OUT_BATCH(
+ (32 << GEN7_URB_ENTRY_NUMBER_SHIFT) | /* at least 32 */
+ (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
+ (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+ OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
+ OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+ (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+ OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
+ OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+ (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+ OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
+ OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+ (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+}
+
+static void
+gen7_upload_cc_state_pointers(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
+ OUT_RELOC(intel->video.gen4_cc_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 1);
+
+ OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
+ OUT_RELOC(intel->video.gen6_blend_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 1);
+
+ OUT_BATCH(GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
+ OUT_RELOC(intel->video.gen6_depth_stencil_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 1);
+}
+
+static void
+gen7_upload_sampler_state_pointers(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
+ OUT_RELOC(intel->video.gen4_sampler_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+}
+
+static void
+gen7_upload_bypass_states(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ /* bypass GS */
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
+ OUT_BATCH(0); /* without GS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
+ OUT_BATCH(0);
+
+ /* disable HS */
+ OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
+ OUT_BATCH(0);
+
+ /* Disable TE */
+ OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ /* Disable DS */
+ OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
+ OUT_BATCH(0);
+
+ /* Disable STREAMOUT */
+ OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+static void
+gen7_upload_vs_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ /* disable VS constant buffer */
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
+ OUT_BATCH(0); /* without VS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+}
+
+static void
+gen7_upload_sf_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
+ OUT_BATCH((1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
+ (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
+ (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW4 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW9 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
+ OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+static void
+gen7_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ /* disable WM constant buffer */
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2));
+ OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
+ GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2));
+
+ if (is_packed) {
+ OUT_RELOC(intel->video.wm_prog_packed_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+ OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
+ (2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+ } else {
+ OUT_RELOC(intel->video.wm_prog_planar_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+ OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
+ (7 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+ }
+
+ OUT_BATCH(0); /* scratch space base offset */
+ OUT_BATCH(
+ ((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
+ GEN7_PS_ATTRIBUTE_ENABLE |
+ GEN7_PS_16_DISPATCH_ENABLE);
+ OUT_BATCH(
+ (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
+ OUT_BATCH(0); /* kernel 1 pointer */
+ OUT_BATCH(0); /* kernel 2 pointer */
+}
+
+static void
+gen7_upload_binding_table(ScrnInfoPtr scrn, uint32_t ps_binding_table_offset)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
+ OUT_BATCH(ps_binding_table_offset);
+}
+
+static void
+gen7_upload_depth_buffer_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
+ OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
+ (BRW_SURFACE_NULL << 29));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+static void
+gen7_upload_vertex_buffer(ScrnInfoPtr scrn, drm_intel_bo *vertex_bo, uint32_t end_address_offset)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ /* Set up the pointer to our vertex buffer */
+ OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+ /* four 32-bit floats per vertex */
+ OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
+ GEN6_VB0_VERTEXDATA |
+ GEN7_VB0_ADDRESS_MODIFYENABLE |
+ ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
+ OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
+ OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, end_address_offset);
+ OUT_BATCH(0); /* reserved */
+}
+
+static void
+gen7_upload_primitive(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(BRW_3DPRIMITIVE | (7 - 2));
+ OUT_BATCH(_3DPRIM_RECTLIST |
+ GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
+ OUT_BATCH(3); /* vertex count per instance */
+ OUT_BATCH(0); /* start vertex offset */
+ OUT_BATCH(1); /* single instance */
+ OUT_BATCH(0); /* start instance location */
+ OUT_BATCH(0);
+}
+
+static void
+gen7_emit_video_setup(ScrnInfoPtr scrn,
+ drm_intel_bo *surface_state_binding_table_bo, int n_src_surf,
+ PixmapPtr pixmap,
+ drm_intel_bo *vertex_bo, uint32_t end_address_offset)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ assert(n_src_surf == 1 || n_src_surf == 6);
+ IntelEmitInvarientState(scrn);
+ intel->last_3d = LAST_3D_VIDEO;
+
+ gen7_upload_invarient_states(scrn);
+ gen6_upload_state_base_address(scrn, surface_state_binding_table_bo);
+ gen7_upload_viewport_state_pointers(scrn);
+ gen7_upload_urb(scrn);
+ gen7_upload_cc_state_pointers(scrn);
+ gen7_upload_sampler_state_pointers(scrn);
+ gen7_upload_bypass_states(scrn);
+ gen7_upload_vs_state(scrn);
+ gen6_upload_clip_state(scrn);
+ gen7_upload_sf_state(scrn);
+ gen7_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE);
+ gen7_upload_binding_table(scrn, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
+ gen7_upload_depth_buffer_state(scrn);
+ gen6_upload_drawing_rectangle(scrn, pixmap);
+ gen6_upload_vertex_element_state(scrn);
+ gen7_upload_vertex_buffer(scrn, vertex_bo, end_address_offset);
+ gen7_upload_primitive(scrn);
}
void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
@@ -1866,13 +2279,19 @@ void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
uint32_t, int,
int, int, uint32_t,
drm_intel_bo *, uint32_t);
+ void (*emit_video_setup)(ScrnInfoPtr,
+ drm_intel_bo *, int,
+ PixmapPtr,
+ drm_intel_bo *, uint32_t);
if (INTEL_INFO(intel)->gen >= 70) {
create_dst_surface_state = gen7_create_dst_surface_state;
create_src_surface_state = gen7_create_src_surface_state;
+ emit_video_setup = gen7_emit_video_setup;
} else {
create_dst_surface_state = i965_create_dst_surface_state;
create_src_surface_state = i965_create_src_surface_state;
+ emit_video_setup = gen6_emit_video_setup;
}
src_surf_base[0] = adaptor_priv->YBufOffset;
@@ -2009,30 +2428,9 @@ void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
intel_batch_submit(scrn);
intel_batch_start_atomic(scrn, 200);
- gen6_emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap);
-
- /* Set up the pointer to our vertex buffer */
- OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2));
- /* four 32-bit floats per vertex */
- OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
- GEN6_VB0_VERTEXDATA |
- ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
- OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
- OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, i * 4);
- OUT_BATCH(0); /* reserved */
-
- OUT_BATCH(BRW_3DPRIMITIVE |
- BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL |
- (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) |
- (0 << 9) | /* Internal Vertex Count */
- (6 - 2));
- OUT_BATCH(3); /* vertex count per instance */
- OUT_BATCH(0); /* start vertex offset */
- OUT_BATCH(1); /* single instance */
- OUT_BATCH(0); /* start instance location */
- OUT_BATCH(0); /* index buffer offset, ignored */
-
+ emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap, vb_bo, i * 4);
intel_batch_end_atomic(scrn);
+
drm_intel_bo_unreference(vb_bo);
}
commit 90a0800588f83d78254136b94bca656c4c24215d
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Tue Jun 21 14:14:38 2011 +0800
Xv: upload new shaders to GEM objects for Xv on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/src/i965_video.c b/src/i965_video.c
index 9fbba40..84230a1 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -149,6 +149,21 @@ static const uint32_t ps_kernel_planar_static_gen6[][4] = {
#include "exa_wm_write.g6b"
};
+/* programs for Ivybridge */
+static const uint32_t ps_kernel_packed_static_gen7[][4] = {
+#include "exa_wm_src_affine.g7b"
+#include "exa_wm_src_sample_argb.g7b"
+#include "exa_wm_yuv_rgb.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_planar_static_gen7[][4] = {
+#include "exa_wm_src_affine.g7b"
+#include "exa_wm_src_sample_planar.g7b"
+#include "exa_wm_yuv_rgb.g7b"
+#include "exa_wm_write.g7b"
+};
+
#ifndef MAX2
#define MAX2(a,b) ((a) > (b) ? (a) : (b))
#endif
@@ -1459,28 +1474,37 @@ gen6_create_vidoe_objects(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *(*create_sampler_state)(ScrnInfoPtr);
-
+ const uint32_t *packed_ps_kernel, *planar_ps_kernel;
+ unsigned int packed_ps_size, planar_ps_size;
+
if (INTEL_INFO(intel)->gen >= 70) {
create_sampler_state = gen7_create_sampler_state;
+ packed_ps_kernel = &ps_kernel_packed_static_gen7[0][0];
+ packed_ps_size = sizeof(ps_kernel_packed_static_gen7);
+ planar_ps_kernel = &ps_kernel_planar_static_gen7[0][0];
+ planar_ps_size = sizeof(ps_kernel_planar_static_gen7);
} else {
create_sampler_state = i965_create_sampler_state;
+ packed_ps_kernel = &ps_kernel_packed_static_gen6[0][0];
+ packed_ps_size = sizeof(ps_kernel_packed_static_gen6);
+ planar_ps_kernel = &ps_kernel_planar_static_gen6[0][0];
+ planar_ps_size = sizeof(ps_kernel_planar_static_gen6);
}
-
if (intel->video.gen4_sampler_bo == NULL)
intel->video.gen4_sampler_bo = create_sampler_state(scrn);
if (intel->video.wm_prog_packed_bo == NULL)
intel->video.wm_prog_packed_bo =
i965_create_program(scrn,
- &ps_kernel_packed_static_gen6[0][0],
- sizeof(ps_kernel_packed_static_gen6));
+ packed_ps_kernel,
+ packed_ps_size);
if (intel->video.wm_prog_planar_bo == NULL)
intel->video.wm_prog_planar_bo =
i965_create_program(scrn,
- &ps_kernel_planar_static_gen6[0][0],
- sizeof(ps_kernel_planar_static_gen6));
+ planar_ps_kernel,
+ planar_ps_size);
if (intel->video.gen4_cc_vp_bo == NULL)
intel->video.gen4_cc_vp_bo = i965_create_cc_vp_state(scrn);
commit 00614f712b243a7724cf919f94d204a123d2789a
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Thu Jun 23 00:09:21 2011 +0800
Xv: update SURFACE_STATE & SAMPLER_STATE for Xv on Ivybridge
SURFACE_STATE & SAMPLER_STATE are changed since Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/src/brw_structs.h b/src/brw_structs.h
index fa7b58b..f4dc927 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
@@ -1592,4 +1592,128 @@ struct gen6_depth_stencil_state
} ds2;
};
+struct gen7_surface_state
+{
+ struct {
+ unsigned int cube_pos_z:1;
+ unsigned int cube_neg_z:1;
+ unsigned int cube_pos_y:1;
+ unsigned int cube_neg_y:1;
+ unsigned int cube_pos_x:1;
+ unsigned int cube_neg_x:1;
+ unsigned int pad2:2;
+ unsigned int render_cache_read_write:1;
+ unsigned int pad1:1;
+ unsigned int surface_array_spacing:1;
+ unsigned int vert_line_stride_ofs:1;
+ unsigned int vert_line_stride:1;
+ unsigned int tile_walk:1;
+ unsigned int tiled_surface:1;
+ unsigned int horizontal_alignment:1;
+ unsigned int vertical_alignment:2;
+ unsigned int surface_format:9; /**< BRW_SURFACEFORMAT_x */
+ unsigned int pad0:1;
+ unsigned int is_array:1;
+ unsigned int surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */
+ } ss0;
+
+ struct {
+ unsigned int base_addr;
+ } ss1;
+
+ struct {
+ unsigned int width:14;
+ unsigned int pad1:2;
+ unsigned int height:14;
+ unsigned int pad0:2;
+ } ss2;
+
+ struct {
+ unsigned int pitch:18;
+ unsigned int pad:3;
+ unsigned int depth:11;
+ } ss3;
+
+ struct {
+ unsigned int multisample_position_palette_index:3;
+ unsigned int num_multisamples:3;
+ unsigned int multisampled_surface_storage_format:1;
+ unsigned int render_target_view_extent:11;
+ unsigned int min_array_elt:11;
+ unsigned int rotation:2;
+ unsigned int pad0:1;
+ } ss4;
+
+ struct {
+ unsigned int mip_count:4;
+ unsigned int min_lod:4;
+ unsigned int pad1:12;
+ unsigned int y_offset:4;
+ unsigned int pad0:1;
+ unsigned int x_offset:7;
+ } ss5;
+
+ struct {
+ unsigned int pad; /* Multisample Control Surface stuff */
+ } ss6;
+
+ struct {
+ unsigned int resource_min_lod:12;
+ unsigned int pad0:16;
+ unsigned int alpha_clear_color:1;
+ unsigned int blue_clear_color:1;
+ unsigned int green_clear_color:1;
+ unsigned int red_clear_color:1;
+ } ss7;
+};
+
+struct gen7_sampler_state
+{
+ struct
+ {
+ unsigned int aniso_algorithm:1;
+ unsigned int lod_bias:13;
+ unsigned int min_filter:3;
+ unsigned int mag_filter:3;
+ unsigned int mip_filter:2;
+ unsigned int base_level:5;
+ unsigned int pad1:1;
+ unsigned int lod_preclamp:1;
+ unsigned int default_color_mode:1;
+ unsigned int pad0:1;
+ unsigned int disable:1;
+ } ss0;
+
+ struct
+ {
+ unsigned int cube_control_mode:1;
+ unsigned int shadow_function:3;
+ unsigned int pad:4;
+ unsigned int max_lod:12;
+ unsigned int min_lod:12;
+ } ss1;
+
+ struct
+ {
+ unsigned int pad:5;
+ unsigned int default_color_pointer:27;
+ } ss2;
+
+ struct
+ {
+ unsigned int r_wrap_mode:3;
+ unsigned int t_wrap_mode:3;
+ unsigned int s_wrap_mode:3;
+ unsigned int pad:1;
+ unsigned int non_normalized_coord:1;
+ unsigned int trilinear_quality:2;
+ unsigned int address_round:6;
+ unsigned int max_aniso:3;
+ unsigned int chroma_key_mode:1;
+ unsigned int chroma_key_index:2;
+ unsigned int chroma_key_enable:1;
+ unsigned int pad0:6;
+ } ss3;
+};
+
#endif
diff --git a/src/i965_video.c b/src/i965_video.c
index 53a9394..9fbba40 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -149,6 +149,15 @@ static const uint32_t ps_kernel_planar_static_gen6[][4] = {
#include "exa_wm_write.g6b"
};
+#ifndef MAX2
+#define MAX2(a,b) ((a) > (b) ? (a) : (b))
+#endif
+
+#define SURFACE_STATE_PADDED_SIZE_I965 ALIGN(sizeof(struct brw_surface_state), 32)
+#define SURFACE_STATE_PADDED_SIZE_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
+#define SURFACE_STATE_PADDED_SIZE MAX2(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
+#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
+
static uint32_t float_to_uint(float f)
{
union {
@@ -475,6 +484,84 @@ static void i965_create_src_surface_state(ScrnInfoPtr scrn,
drm_intel_bo_unmap(surface_bo);
}
+static void gen7_create_dst_surface_state(ScrnInfoPtr scrn,
+ PixmapPtr pixmap,
+ drm_intel_bo *surf_bo,
+ uint32_t offset)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ struct gen7_surface_state *dest_surf_state;
+ drm_intel_bo *pixmap_bo = intel_get_pixmap_bo(pixmap);
+
+ if (drm_intel_bo_map(surf_bo, TRUE) != 0)
+ return;
+
+ dest_surf_state = (struct gen7_surface_state *)((char *)surf_bo->virtual + offset);
+ memset(dest_surf_state, 0, sizeof(*dest_surf_state));
+
+ dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
+ dest_surf_state->ss0.tiled_surface = intel_pixmap_tiled(pixmap);
+ dest_surf_state->ss0.tile_walk = 0; /* TileX */
+
+ if (intel->cpp == 2) {
+ dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
+ } else {
+ dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
+ }
+
+ dest_surf_state->ss1.base_addr =
+ intel_emit_reloc(surf_bo,
+ offset + offsetof(struct gen7_surface_state, ss1),
+ pixmap_bo, 0,
+ I915_GEM_DOMAIN_SAMPLER, 0);
+
+ dest_surf_state->ss2.height = pixmap->drawable.height - 1;
+ dest_surf_state->ss2.width = pixmap->drawable.width - 1;
+
+ dest_surf_state->ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
+
+ drm_intel_bo_unmap(surf_bo);
+}
+
+static void gen7_create_src_surface_state(ScrnInfoPtr scrn,
+ drm_intel_bo * src_bo,
+ uint32_t src_offset,
+ int src_width,
+ int src_height,
+ int src_pitch,
+ uint32_t src_surf_format,
+ drm_intel_bo *surface_bo,
+ uint32_t offset)
+{
+ struct gen7_surface_state *src_surf_state;
+
+ if (drm_intel_bo_map(surface_bo, TRUE) != 0)
+ return;
+
+ src_surf_state = (struct gen7_surface_state *)((char *)surface_bo->virtual + offset);
+ memset(src_surf_state, 0, sizeof(*src_surf_state));
+
+ src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
+ src_surf_state->ss0.surface_format = src_surf_format;
+
+ if (src_bo) {
+ src_surf_state->ss1.base_addr =
+ intel_emit_reloc(surface_bo,
+ offset + offsetof(struct gen7_surface_state, ss1),
+ src_bo, src_offset,
+ I915_GEM_DOMAIN_SAMPLER, 0);
+ } else {
+ src_surf_state->ss1.base_addr = src_offset;
+ }
+
+ src_surf_state->ss2.width = src_width - 1;
+ src_surf_state->ss2.height = src_height - 1;
+
+ src_surf_state->ss3.pitch = src_pitch - 1;
+
+ drm_intel_bo_unmap(surface_bo);
+}
+
static void i965_create_binding_table(ScrnInfoPtr scrn,
drm_intel_bo *bind_bo,
int n_surf)
@@ -486,10 +573,10 @@ static void i965_create_binding_table(ScrnInfoPtr scrn,
if (drm_intel_bo_map(bind_bo, TRUE) != 0)
return;
- binding_table = (uint32_t*)((char *)bind_bo->virtual + n_surf * ALIGN(sizeof(struct brw_surface_state), 32));
+ binding_table = (uint32_t*)((char *)bind_bo->virtual + n_surf * SURFACE_STATE_PADDED_SIZE);
for (i = 0; i < n_surf; i++)
- binding_table[i] = i * ALIGN(sizeof(struct brw_surface_state), 32);
+ binding_table[i] = i * SURFACE_STATE_PADDED_SIZE;
drm_intel_bo_unmap(bind_bo);
}
@@ -514,6 +601,26 @@ static drm_intel_bo *i965_create_sampler_state(ScrnInfoPtr scrn)
return sampler_bo;
}
+static drm_intel_bo *gen7_create_sampler_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ drm_intel_bo *sampler_bo;
+ struct gen7_sampler_state *sampler_state;
+
+ if (intel_alloc_and_map(intel, "textured video sampler state", 4096,
+ &sampler_bo, &sampler_state) != 0)
+ return NULL;
+
+ sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
+ sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
+ sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
+ sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
+ sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
+
+ drm_intel_bo_unmap(sampler_bo);
+ return sampler_bo;
+}
+
static drm_intel_bo *i965_create_vs_state(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
@@ -863,7 +970,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * surface_state_binding_tab
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
/* Only the PS uses the binding table */
- OUT_BATCH((n_src_surf + 1) * ALIGN(sizeof(struct brw_surface_state), 32));
+ OUT_BATCH((n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
/* Blend constant color (magenta is fun) */
OUT_BATCH(BRW_3DSTATE_CONSTANT_COLOR | 3);
@@ -1056,7 +1163,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
surface_state_binding_table_bo =
drm_intel_bo_alloc(intel->bufmgr,
"surface state & binding table",
- (n_src_surf + 1) * (ALIGN(sizeof(struct brw_surface_state), 32) + sizeof(uint32_t)),
+ (n_src_surf + 1) * (SURFACE_STATE_PADDED_SIZE + sizeof(uint32_t)),
4096);
if (!surface_state_binding_table_bo)
@@ -1073,7 +1180,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
src_pitch[src_surf],
src_surf_format,
surface_state_binding_table_bo,
- (src_surf + 1) * ALIGN(sizeof(struct brw_surface_state), 32));
+ (src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
}
i965_create_binding_table(scrn, surface_state_binding_table_bo, n_src_surf + 1);
@@ -1351,9 +1458,17 @@ static Bool
gen6_create_vidoe_objects(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
+ drm_intel_bo *(*create_sampler_state)(ScrnInfoPtr);
+
+ if (INTEL_INFO(intel)->gen >= 70) {
+ create_sampler_state = gen7_create_sampler_state;
+ } else {
+ create_sampler_state = i965_create_sampler_state;
+ }
+
if (intel->video.gen4_sampler_bo == NULL)
- intel->video.gen4_sampler_bo = i965_create_sampler_state(scrn);
+ intel->video.gen4_sampler_bo = create_sampler_state(scrn);
if (intel->video.wm_prog_packed_bo == NULL)
intel->video.wm_prog_packed_bo =
@@ -1692,7 +1807,7 @@ gen6_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_tabl
gen6_upload_clip_state(scrn);
gen6_upload_sf_state(scrn);
gen6_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE);
- gen6_upload_binding_table(scrn, (n_src_surf + 1) * ALIGN(sizeof(struct brw_surface_state), 32));;
+ gen6_upload_binding_table(scrn, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
gen6_upload_depth_buffer_state(scrn);
gen6_upload_drawing_rectangle(scrn, pixmap);
gen6_upload_vertex_element_state(scrn);
@@ -1718,6 +1833,23 @@ void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
int src_height[6];
int src_pitch[6];
drm_intel_bo *surface_state_binding_table_bo;
+ void (*create_dst_surface_state)(ScrnInfoPtr,
+ PixmapPtr,
+ drm_intel_bo *,
+ uint32_t);
+ void (*create_src_surface_state)(ScrnInfoPtr,
+ drm_intel_bo *,
+ uint32_t, int,
+ int, int, uint32_t,
+ drm_intel_bo *, uint32_t);
+
+ if (INTEL_INFO(intel)->gen >= 70) {
+ create_dst_surface_state = gen7_create_dst_surface_state;
+ create_src_surface_state = gen7_create_src_surface_state;
+ } else {
+ create_dst_surface_state = i965_create_dst_surface_state;
+ create_src_surface_state = i965_create_src_surface_state;
+ }
src_surf_base[0] = adaptor_priv->YBufOffset;
src_surf_base[1] = adaptor_priv->YBufOffset;
@@ -1753,16 +1885,16 @@ void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
surface_state_binding_table_bo =
drm_intel_bo_alloc(intel->bufmgr,
"surface state & binding table",
- (n_src_surf + 1) * (ALIGN(sizeof(struct brw_surface_state), 32) + sizeof(uint32_t)),
+ (n_src_surf + 1) * (SURFACE_STATE_PADDED_SIZE + sizeof(uint32_t)),
4096);
if (!surface_state_binding_table_bo)
return;
- i965_create_dst_surface_state(scrn, pixmap, surface_state_binding_table_bo, 0);
+ create_dst_surface_state(scrn, pixmap, surface_state_binding_table_bo, 0);
for (src_surf = 0; src_surf < n_src_surf; src_surf++) {
- i965_create_src_surface_state(scrn,
+ create_src_surface_state(scrn,
adaptor_priv->buf,
src_surf_base[src_surf],
src_width[src_surf],
@@ -1770,7 +1902,7 @@ void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
src_pitch[src_surf],
src_surf_format,
surface_state_binding_table_bo,
- (src_surf + 1) * ALIGN(sizeof(struct brw_surface_state), 32));
+ (src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
}
i965_create_binding_table(scrn, surface_state_binding_table_bo, n_src_surf + 1);
commit 70f884772a3adc5dbf56572499c5fb2e080aa84a
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Thu Jun 23 00:02:38 2011 +0800
Xv: New shaders for Xv on Ivybridge
Redefine some M4 macros, also update the check for
intel-gen4asm to support Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/configure.ac b/configure.ac
index eea4708..8d0653a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -59,7 +59,7 @@ m4_ifndef([XORG_DRIVER_CHECK_EXT],
LT_PREREQ([2.2])
LT_INIT([disable-static])
-PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.1], [gen4asm=yes], [gen4asm=no])
+PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.2], [gen4asm=yes], [gen4asm=no])
AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes)
PKG_CHECK_MODULES(UDEV, [libudev], [udev=yes], [udev=no])
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am
index 8e48d27..d7045fa 100644
--- a/src/render_program/Makefile.am
+++ b/src/render_program/Makefile.am
@@ -99,6 +99,20 @@ INTEL_G6B = \
exa_wm_write.g6b \
exa_wm_yuv_rgb.g6b
+INTEL_G7A = \
+ exa_wm_src_affine.g7a \
+ exa_wm_src_sample_argb.g7a \
+ exa_wm_src_sample_planar.g7a \
+ exa_wm_write.g7a \
+ exa_wm_yuv_rgb.g7a
+
+INTEL_G7B = \
+ exa_wm_src_affine.g7b \
+ exa_wm_src_sample_argb.g7b \
+ exa_wm_src_sample_planar.g7b \
+ exa_wm_write.g7b \
+ exa_wm_yuv_rgb.g7b
+
EXTRA_DIST = \
$(INTEL_G4A) \
$(INTEL_G4I) \
@@ -106,23 +120,30 @@ EXTRA_DIST = \
$(INTEL_G4B_GEN5)\
$(INTEL_G6A) \
$(INTEL_G6B) \
- $(INTEL_G6I)
+ $(INTEL_G6I) \
+ $(INTEL_G7A) \
+ $(INTEL_G7B)
if HAVE_GEN4ASM
-SUFFIXES = .g4a .g4b .g6a .g6b
+SUFFIXES = .g4a .g4b .g6a .g6b .g7a .g7b
.g4a.g4b:
m4 -I$(srcdir) -s $< > $*.g4m && intel-gen4asm -o $@ $*.g4m && intel-gen4asm -g 5 -o $@.gen5 $*.g4m && rm $*.g4m
.g6a.g6b:
m4 -I$(srcdir) -s $< > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m
+.g7a.g7b:
+ m4 -I$(srcdir) -s $< > $*.g7m && intel-gen4asm -g 7 -o $@ $*.g7m && rm $*.g7m
+
$(INTEL_G4B): $(INTEL_G4I)
$(INTEL_G6B): $(INTEL_G4I) $(INTEL_G6I)
+$(INTEL_G7B): $(INTEL_G4I) $(INTEL_G6I)
-BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B)
+BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B) $(INTEL_G7B)
clean-local:
-rm -f $(INTEL_G4B) $(INTEL_G4B_GEN5)
-rm -f $(INTEL_G6B)
+ -rm -f $(INTEL_G7B)
endif
diff --git a/src/render_program/exa_wm_src_affine.g7a b/src/render_program/exa_wm_src_affine.g7a
new file mode 100644
index 0000000..cf24b2f
--- /dev/null
+++ b/src/render_program/exa_wm_src_affine.g7a
@@ -0,0 +1,41 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * Fragment to compute src u/v values
+ */
+include(`exa_wm.g4i')
+
+define(`ul', `g66')
+define(`uh', `g67')
+define(`vl', `g68')
+define(`vh', `g69')
+
+define(`bl', `g2.0<8,8,1>F')
+define(`bh', `g4.0<8,8,1>F')
+
+define(`a0_a_x',`g6.0<0,1,0>F')
+define(`a0_a_y',`g6.16<0,1,0>F')
+
+include(`exa_wm_affine.g6i')
diff --git a/src/render_program/exa_wm_src_affine.g7b b/src/render_program/exa_wm_src_affine.g7b
new file mode 100644
index 0000000..f545fba
--- /dev/null
+++ b/src/render_program/exa_wm_src_affine.g7b
@@ -0,0 +1,4 @@
+ { 0x0060005a, 0x284077bd, 0x000000c0, 0x008d0040 },
+ { 0x0060005a, 0x286077bd, 0x000000c0, 0x008d0080 },
+ { 0x0060005a, 0x288077bd, 0x000000d0, 0x008d0040 },
+ { 0x0060005a, 0x28a077bd, 0x000000d0, 0x008d0080 },
diff --git a/src/render_program/exa_wm_src_sample_argb.g7a b/src/render_program/exa_wm_src_sample_argb.g7a
new file mode 100644
index 0000000..69f5ebc
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g7a
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/* Sample the src surface */
+
+include(`exa_wm.g4i')
+
+undefine(`src_msg')
+undefine(`src_msg_ind')
+
+define(`src_msg', `g65')
+define(`src_msg_ind', `65')
+
+include(`exa_wm_src_sample_argb.g4i')
diff --git a/src/render_program/exa_wm_src_sample_argb.g7b b/src/render_program/exa_wm_src_sample_argb.g7b
new file mode 100644
index 0000000..a282cf8
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g7b
@@ -0,0 +1,3 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0000, 0x00000000 },
+ { 0x02800031, 0x21c01ca9, 0x00000820, 0x0a8c0001 },
diff --git a/src/render_program/exa_wm_src_sample_planar.g7a b/src/render_program/exa_wm_src_sample_planar.g7a
new file mode 100644
index 0000000..53b1211
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_planar.g7a
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/* Sample the src surface in planar format */
+
+include(`exa_wm.g4i')
+
+undefine(`src_msg')
+undefine(`src_msg_ind')
+
+define(`src_msg', `g65')
+define(`src_msg_ind', `65')
+
+include(`exa_wm_sample_planar.g4i')
diff --git a/src/render_program/exa_wm_src_sample_planar.g7b b/src/render_program/exa_wm_src_sample_planar.g7b
new file mode 100644
index 0000000..ddd6f36
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_planar.g7b
@@ -0,0 +1,5 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 },
+ { 0x00600001, 0x28200021, 0x008d0000, 0x00000000 },
+ { 0x02800031, 0x22001ca9, 0x00000820, 0x0a2c0001 },
+ { 0x02800031, 0x21c01ca9, 0x00000820, 0x0a2c0003 },
+ { 0x02800031, 0x22401ca9, 0x00000820, 0x0a2c0005 },
diff --git a/src/render_program/exa_wm_write.g7a b/src/render_program/exa_wm_write.g7a
new file mode 100644
index 0000000..d21f9b4
--- /dev/null
+++ b/src/render_program/exa_wm_write.g7a
@@ -0,0 +1,41 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+include(`exa_wm.g4i')
+
+/*
+ * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel,
+ * g70-g71 for Blue and g72-g73 for Alpha channel
+ */
+define(`slot_r_00', `g66')
+define(`slot_r_01', `g67')
+define(`slot_g_00', `g68')
+define(`slot_g_01', `g69')
+define(`slot_b_00', `g70')
+define(`slot_b_01', `g71')
+define(`slot_a_00', `g72')
+define(`slot_a_01', `g73')
+define(`data_port_msg_2_ind', `66')
+
+include(`exa_wm_write.g6i')
diff --git a/src/render_program/exa_wm_write.g7b b/src/render_program/exa_wm_write.g7b
new file mode 100644
index 0000000..f31af51
--- /dev/null
+++ b/src/render_program/exa_wm_write.g7b
@@ -0,0 +1,17 @@
+ { 0x00600001, 0x284003bd, 0x008d01c0, 0x00000000 },
+ { 0x00600001, 0x286003bd, 0x008d01e0, 0x00000000 },
+ { 0x00600001, 0x288003bd, 0x008d0200, 0x00000000 },
+ { 0x00600001, 0x28a003bd, 0x008d0220, 0x00000000 },
+ { 0x00600001, 0x28c003bd, 0x008d0240, 0x00000000 },
+ { 0x00600001, 0x28e003bd, 0x008d0260, 0x00000000 },
+ { 0x00600001, 0x290003bd, 0x008d0280, 0x00000000 },
+ { 0x00600001, 0x292003bd, 0x008d02a0, 0x00000000 },
+ { 0x05800031, 0x24001ca8, 0x00000840, 0x90031000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_wm_yuv_rgb.g7a b/src/render_program/exa_wm_yuv_rgb.g7a
new file mode 120000
index 0000000..d34d246
--- /dev/null
+++ b/src/render_program/exa_wm_yuv_rgb.g7a
@@ -0,0 +1 @@
+exa_wm_yuv_rgb.g4a
\ No newline at end of file
diff --git a/src/render_program/exa_wm_yuv_rgb.g7b b/src/render_program/exa_wm_yuv_rgb.g7b
new file mode 100644
index 0000000..01ec5e5
--- /dev/null
+++ b/src/render_program/exa_wm_yuv_rgb.g7b
@@ -0,0 +1,12 @@
+ { 0x00800040, 0x23007fbd, 0x008d0200, 0xbd808081 },
+ { 0x00800041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 },
+ { 0x00800040, 0x22c07fbd, 0x008d01c0, 0xbf008084 },
+ { 0x00800040, 0x23407fbd, 0x008d0240, 0xbf008084 },
+ { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 },
+ { 0x80800048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba },
+ { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 },
+ { 0x00800048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 },
+ { 0x80800048, 0x22007fbd, 0x008d0340, 0xbec8b439 },
+ { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 },
+ { 0x80800048, 0x22407fbd, 0x008d0340, 0x40011687 },
+ { 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 },
commit 3cf423bd3a9483181e59ee87376a9487fa1f923d
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Wed Jun 22 23:33:08 2011 +0800
Xv: separate fragments from M4 macros
It is to prepare for Xv on Ivybridge. The difference from Sandybridge
is that all message payload must be in GRF registers instead of MRF registers
on Ivybridge. We will only redefine some M4 macros for Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am
index 1a19437..8e48d27 100644
--- a/src/render_program/Makefile.am
+++ b/src/render_program/Makefile.am
@@ -20,7 +20,9 @@ INTEL_G4A = \
INTEL_G4I = \
exa_wm.g4i \
exa_wm_affine.g4i \
- exa_wm_projective.g4i
+ exa_wm_projective.g4i \
+ exa_wm_sample_planar.g4i \
+ exa_wm_src_sample_argb.g4i
INTEL_G4B = \
exa_sf.g4b \
@@ -61,6 +63,10 @@ INTEL_G4B_GEN5 = \
exa_wm_yuv_rgb.g4b.gen5 \
exa_wm_xy.g4b.gen5
+INTEL_G6I = \
+ exa_wm_affine.g6i \
+ exa_wm_write.g6i
+
INTEL_G6A = \
exa_wm_src_affine.g6a \
exa_wm_src_projective.g6a \
@@ -99,7 +105,8 @@ EXTRA_DIST = \
$(INTEL_G4B) \
$(INTEL_G4B_GEN5)\
$(INTEL_G6A) \
- $(INTEL_G6B)
+ $(INTEL_G6B) \
+ $(INTEL_G6I)
if HAVE_GEN4ASM
@@ -111,7 +118,7 @@ SUFFIXES = .g4a .g4b .g6a .g6b
m4 -I$(srcdir) -s $< > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m
$(INTEL_G4B): $(INTEL_G4I)
-$(INTEL_G6B): $(INTEL_G4I)
+$(INTEL_G6B): $(INTEL_G4I) $(INTEL_G6I)
BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B)
diff --git a/src/render_program/exa_wm_affine.g6i b/src/render_program/exa_wm_affine.g6i
new file mode 100644
index 0000000..9ac21d5
--- /dev/null
+++ b/src/render_program/exa_wm_affine.g6i
@@ -0,0 +1,35 @@
+/*
+ * Copyright © 2010-2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * Fragment to compute src u/v values
+ */
+
+/* U */
+pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
+pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
+
+/* V */
+pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */
+pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */
diff --git a/src/render_program/exa_wm_mask_affine.g6a b/src/render_program/exa_wm_mask_affine.g6a
index 2daf4e2..04ad2a2 100644
--- a/src/render_program/exa_wm_mask_affine.g6a
+++ b/src/render_program/exa_wm_mask_affine.g6a
@@ -38,10 +38,4 @@ define(`bh', `g4.0<8,8,1>F')
define(`a0_a_x',`g8.0<0,1,0>F')
define(`a0_a_y',`g8.16<0,1,0>F')
-/* U */
-pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
-pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
-
-/* V */
-pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */
-pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */
+include(`exa_wm_affine.g6i')
diff --git a/src/render_program/exa_wm_sample_planar.g4i b/src/render_program/exa_wm_sample_planar.g4i
new file mode 100644
index 0000000..5452420
--- /dev/null
+++ b/src/render_program/exa_wm_sample_planar.g4i
@@ -0,0 +1,64 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/* Sample the src surface in planar format */
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load r */
+mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable };
+
+/* src_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+
+/* sample Y */
+mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
+send (16) src_msg_ind /* msg reg index */
+ src_sample_g<1>UW /* readback */
+ null
+ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
+
+/* sample U (Cr) */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_r<1>UW /* readback */
+ null
+ sampler (3,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
+
+/* sample V (Cb) */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_b<1>UW /* readback */
+ null
+ sampler (5,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/render_program/exa_wm_src_affine.g6a b/src/render_program/exa_wm_src_affine.g6a
index 08195a4..38623bf 100644
--- a/src/render_program/exa_wm_src_affine.g6a
+++ b/src/render_program/exa_wm_src_affine.g6a
@@ -38,10 +38,4 @@ define(`bh', `g4.0<8,8,1>F')
define(`a0_a_x',`g6.0<0,1,0>F')
define(`a0_a_y',`g6.16<0,1,0>F')
-/* U */
-pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
-pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
-
-/* V */
-pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */
-pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */
+include(`exa_wm_affine.g6i')
diff --git a/src/render_program/exa_wm_src_sample_argb.g4a b/src/render_program/exa_wm_src_sample_argb.g4a
index 384fe26..02119e3 100644
--- a/src/render_program/exa_wm_src_sample_argb.g4a
+++ b/src/render_program/exa_wm_src_sample_argb.g4a
@@ -29,20 +29,4 @@
include(`exa_wm.g4i')
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* load argb */
-mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable };
-mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
-
-/* src_msg will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-send (16) src_msg_ind /* msg reg index */
- src_sample_base<1>UW /* readback */
- null
- sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
+include(`exa_wm_src_sample_argb.g4i')
diff --git a/src/render_program/exa_wm_src_sample_argb.g4i b/src/render_program/exa_wm_src_sample_argb.g4i
new file mode 100644
index 0000000..62d5afc
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g4i
@@ -0,0 +1,44 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load argb */
+mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable };
+mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
+
+/* src_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_base<1>UW /* readback */
+ null
+ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/render_program/exa_wm_src_sample_planar.g4a b/src/render_program/exa_wm_src_sample_planar.g4a
index 5f5520b..59678f5 100644
--- a/src/render_program/exa_wm_src_sample_planar.g4a
+++ b/src/render_program/exa_wm_src_sample_planar.g4a
@@ -29,38 +29,4 @@
include(`exa_wm.g4i')
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* load r */
-mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable };
-
-/* src_msg will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-
-/* sample Y */
-mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
-send (16) src_msg_ind /* msg reg index */
- src_sample_g<1>UW /* readback */
- null
- sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
-
-/* sample U (Cr) */
-send (16) src_msg_ind /* msg reg index */
- src_sample_r<1>UW /* readback */
- null
- sampler (3,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
-
-/* sample V (Cb) */
-send (16) src_msg_ind /* msg reg index */
- src_sample_b<1>UW /* readback */
- null
- sampler (5,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
+include(`exa_wm_sample_planar.g4i')
diff --git a/src/render_program/exa_wm_write.g6a b/src/render_program/exa_wm_write.g6a
index c0f3cc1..ed976b5 100644
--- a/src/render_program/exa_wm_write.g6a
+++ b/src/render_program/exa_wm_write.g6a
@@ -38,40 +38,4 @@ define(`slot_a_00', `m8')
define(`slot_a_01', `m9')
define(`data_port_msg_2_ind', `2')
-mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 };
-mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 };
-
-mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 };
-mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 };
-
-mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 };
-mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 };
-
-mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 };
-mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 };
-
-/* write */
-send (16)
- data_port_msg_2_ind
- acc0<1>UW
- null
- write (
- 0, /* binding_table */
- 16, /* pixel scordboard clear, msg type simd16 single source */
- 12, /* render target write */
- 0, /* no write commit message */
- 0 /* headerless render target write */
- )
- mlen 8
- rlen 0
- { align1 EOT };
-
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-
+include(`exa_wm_write.g6i')
diff --git a/src/render_program/exa_wm_write.g6i b/src/render_program/exa_wm_write.g6i
new file mode 100644
index 0000000..7be1db2
--- /dev/null
+++ b/src/render_program/exa_wm_write.g6i
@@ -0,0 +1,61 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 };
+mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 };
+
+mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 };
+mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 };
+
+mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 };
+mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 };
+
+mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 };
+mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 };
+
+/* write */
+send (16)
+ data_port_msg_2_ind
+ acc0<1>UW
+ null
+ write (
+ 0, /* binding_table */
+ 16, /* pixel scordboard clear, msg type simd16 single source */
+ 12, /* render target write */
+ 0, /* no write commit message */
+ 0 /* headerless render target write */
+ )
+ mlen 8
+ rlen 0
+ { align1 EOT };
+
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+
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