intel-gen4asm: Changes to 'master'

[Haihao Xiang]

 src/brw_defines.h |    6 ++++-
 src/brw_structs.h |   15 +++++++++++++-
 src/gram.y        |   55 +++++++++++++++++++++++++++++++++++++++++++++---------
 src/lex.l         |    1 
 4 files changed, 66 insertions(+), 11 deletions(-)

New commits:
commit 32c680a339ad673737ebe1f31992e73926a0a051
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Tue May 31 13:36:03 2011 +0800

    Support VME on Ivybridge
    
    Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>

commit 07715f818e1535d953cdfa33e702c911c7b1e29c
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Fri Jun 10 16:04:30 2011 +0800

    Support DP for sampler/render/constant/data cache
    
    Since Sandybridge, DP supports cache select for read/write. Some write messages such as
    OWord Block Write don't support render cache any more on Ivybridge. So introduce a
    generic data_port messsage for Sandybridge+.
    
        data_port(
            cache_type,   /* sampler, render, constant or data(on Ivybridge+) cache */
            message_type, /* read or write type */
            message_control,
            binding_table_index,
            write_commit_or_category, /* write commit on Sandybridge, category on Ivybridge+ */
            header_present)
    
    Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>

commit 91a21a9c88f8baa68e597036f80a67a0c7722188
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Mon May 30 16:30:48 2011 +0800

    sampler/render/constant cache unit since Sandybridge
    
    since Sandybrdige, there isn't a single function unit for data port read/write.
    Instead sampler/render/constant cache unit is introduced, data port read/write
    can be specified in a SEND instruction with different cache unit. To keep compatibility,
    currently data port read always uses sampler cache unit however data port write
    uses render cache unit
    
    Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>

commit 4fc9d8c3b5f5294fee5e4b6f773a9818d2ce2a76
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Mon May 30 16:00:12 2011 +0800

    fix an error in commit cf76278
    
    Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>