xf86-video-ati: Branch 'master'

[Alex Deucher]

 src/drmmode_display.c |   25 +++++++++++++++++++++----
 src/radeon.h          |    1 +
 src/radeon_kms.c      |    2 ++
 3 files changed, 24 insertions(+), 4 deletions(-)

New commits:
commit a9a59717d11af37a2dda5555f6a83c5b65449527
Author: Alex Deucher <alexdeucher at gmail.com>
Date:   Sat Feb 12 05:34:50 2011 -0500

    kms: use worst case base/pitch align if we don't have drm tiling info
    
    To avoid CS rejection.
    
    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 82d6a33..a972389 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1130,8 +1130,16 @@ int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling)
 			/* further restrictions for scanout */
 			pitch_align = MAX(info->group_bytes / bpe, pitch_align);
 		} else {
-			/* linear aligned requirements */
-			pitch_align = MAX(64, info->group_bytes / bpe);
+			if (info->have_tiling_info)
+				/* linear aligned requirements */
+				pitch_align = MAX(64, info->group_bytes / bpe);
+			else
+				/* default to 512 elements if we don't know the real
+				 * group size otherwise the kernel may reject the CS
+				 * if the group sizes don't match as the pitch won't
+				 * be aligned properly.
+				 */
+				pitch_align = 512;
 		}
 	} else {
 		/* general surface requirements */
@@ -1155,8 +1163,17 @@ int drmmode_get_base_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling)
 		if (tiling & RADEON_TILING_MACRO)
 			base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe,
 					 pixel_align * bpe * height_align);
-		else
-			base_align = info->group_bytes;
+		else {
+			if (info->have_tiling_info)
+				base_align = info->group_bytes;
+			else
+				/* default to 512 if we don't know the real
+				 * group size otherwise the kernel may reject the CS
+				 * if the group sizes don't match as the base won't
+				 * be aligned properly.
+				 */
+				base_align = 512;
+		}
 	}
 	return base_align;
 }
diff --git a/src/radeon.h b/src/radeon.h
index 67a9b49..4c43717 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1067,6 +1067,7 @@ typedef struct {
     uint64_t gart_size;
     drmmode_rec drmmode;
     /* r6xx+ tile config */
+    Bool have_tiling_info;
     uint32_t tile_config;
     int group_bytes;
     int num_channels;
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index dae512e..269a850 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -513,6 +513,7 @@ static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
 	}
     }
 
+    info->have_tiling_info = TRUE;
     return TRUE;
 }
 
@@ -600,6 +601,7 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
     if (info->ChipFamily >= CHIP_FAMILY_R600) {
 	/* set default group bytes, overridden by kernel info below */
 	info->group_bytes = 256;
+	info->have_tiling_info = FALSE;
 	if (info->dri->pKernelDRMVersion->version_minor >= 6) {
 	    if (r600_get_tile_config(pScrn))
 		info->allowColorTiling = xf86ReturnOptValBool(info->Options,