xf86-video-ati: Branch 'master' - 6 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Thu Feb 10 11:52:28 PST 2011
src/drmmode_display.c | 6
src/evergreen_accel.c | 55 ++++++
src/evergreen_exa.c | 318 +++++++-----------------------------
src/evergreen_state.h | 21 +-
src/evergreen_textured_videofuncs.c | 49 ++---
src/r600_exa.c | 194 +++++++--------------
src/r600_state.h | 7
src/r600_textured_videofuncs.c | 35 +--
src/r6xx_accel.c | 66 +++++++
src/radeon.h | 1
10 files changed, 313 insertions(+), 439 deletions(-)
New commits:
commit 39104c6e8461cf49c1bb03a18858ad75a9d98b46
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Feb 10 14:31:43 2011 -0500
remove EVERGREENSetAccelState()
It was a duplicate of the R600 variant.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 0aeac85..07e3819 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -43,108 +43,6 @@
#include "radeon_exa_shared.h"
#include "radeon_vbo.h"
-Bool
-EVERGREENSetAccelState(ScrnInfoPtr pScrn,
- struct r600_accel_object *src0,
- struct r600_accel_object *src1,
- struct r600_accel_object *dst,
- uint32_t vs_offset, uint32_t ps_offset,
- int rop, Pixel planemask)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
- uint32_t pitch = 0;
- int ret;
-
- if (src0) {
- memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object));
- accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8);
- ret = radeon_bo_get_tiling(accel_state->src_obj[0].bo,
- &accel_state->src_obj[0].tiling_flags,
- &pitch);
- if (ret)
- RADEON_FALLBACK(("src0 radeon_bo_get_tiling failed\n"));
- } else {
- memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
- accel_state->src_size[0] = 0;
- }
-
- if (src1) {
- memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object));
- accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8);
- ret = radeon_bo_get_tiling(accel_state->src_obj[1].bo,
- &accel_state->src_obj[1].tiling_flags,
- &pitch);
- if (ret)
- RADEON_FALLBACK(("src1 radeon_bo_get_tiling failed\n"));
- } else {
- memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
- accel_state->src_size[1] = 0;
- }
-
- if (dst) {
- memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object));
- accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
- ret = radeon_bo_get_tiling(accel_state->dst_obj.bo,
- &accel_state->dst_obj.tiling_flags,
- &pitch);
- if (ret)
- RADEON_FALLBACK(("dst radeon_bo_get_tiling failed\n"));
- } else {
- memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object));
- accel_state->dst_size = 0;
- }
-
- accel_state->rop = rop;
- accel_state->planemask = planemask;
-
- /* bad pitch */
- if (accel_state->src_obj[0].pitch & 7)
- RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[0].pitch));
-
- /* bad offset */
- if (accel_state->src_obj[0].offset & 0xff)
- RADEON_FALLBACK(("Bad src offset 0x%08x\n", accel_state->src_obj[0].offset));
-
- /* bad pitch */
- if (accel_state->src_obj[1].pitch & 7)
- RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[1].pitch));
-
- /* bad offset */
- if (accel_state->src_obj[1].offset & 0xff)
- RADEON_FALLBACK(("Bad src offset 0x%08x\n", accel_state->src_obj[1].offset));
-
- if (accel_state->dst_obj.pitch & 7)
- RADEON_FALLBACK(("Bad dst pitch 0x%08x\n", accel_state->dst_obj.pitch));
-
- if (accel_state->dst_obj.offset & 0xff)
- RADEON_FALLBACK(("Bad dst offset 0x%08x\n", accel_state->dst_obj.offset));
-
- accel_state->vs_size = 512;
- accel_state->ps_size = 512;
-
- accel_state->vs_mc_addr = vs_offset;
- accel_state->ps_mc_addr = ps_offset;
-
- radeon_cs_space_reset_bos(info->cs);
- radeon_cs_space_add_persistent_bo(info->cs, accel_state->shaders_bo,
- RADEON_GEM_DOMAIN_VRAM, 0);
- if (accel_state->src_obj[0].bo)
- radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[0].bo,
- accel_state->src_obj[0].domain, 0);
- if (accel_state->src_obj[1].bo)
- radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[1].bo,
- accel_state->src_obj[1].domain, 0);
- if (accel_state->dst_obj.bo)
- radeon_cs_space_add_persistent_bo(info->cs, accel_state->dst_obj.bo,
- 0, accel_state->dst_obj.domain);
- ret = radeon_cs_space_check(info->cs);
- if (ret)
- RADEON_FALLBACK(("Not enough RAM to hw accel operation\n"));
-
- return TRUE;
-}
-
static void
EVERGREENDoneSolid(PixmapPtr pPix);
@@ -177,12 +75,12 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
dst.bpp = pPix->drawable.bitsPerPixel;
dst.domain = RADEON_GEM_DOMAIN_VRAM;
- if (!EVERGREENSetAccelState(pScrn,
- NULL,
- NULL,
- &dst,
- accel_state->solid_vs_offset, accel_state->solid_ps_offset,
- alu, pm))
+ if (!R600SetAccelState(pScrn,
+ NULL,
+ NULL,
+ &dst,
+ accel_state->solid_vs_offset, accel_state->solid_ps_offset,
+ alu, pm))
return FALSE;
CLEAR (cb_conf);
@@ -552,12 +450,12 @@ EVERGREENPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
dst_obj.bpp = pDst->drawable.bitsPerPixel;
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
- if (!EVERGREENSetAccelState(pScrn,
- &src_obj,
- NULL,
- &dst_obj,
- accel_state->copy_vs_offset, accel_state->copy_ps_offset,
- rop, planemask))
+ if (!R600SetAccelState(pScrn,
+ &src_obj,
+ NULL,
+ &dst_obj,
+ accel_state->copy_vs_offset, accel_state->copy_ps_offset,
+ rop, planemask))
return FALSE;
if (accel_state->same_surface == TRUE) {
@@ -1188,12 +1086,12 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
mask_obj.bpp = pMask->drawable.bitsPerPixel;
mask_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
- if (!EVERGREENSetAccelState(pScrn,
- &src_obj,
- &mask_obj,
- &dst_obj,
- accel_state->comp_vs_offset, accel_state->comp_ps_offset,
- 3, 0xffffffff))
+ if (!R600SetAccelState(pScrn,
+ &src_obj,
+ &mask_obj,
+ &dst_obj,
+ accel_state->comp_vs_offset, accel_state->comp_ps_offset,
+ 3, 0xffffffff))
return FALSE;
accel_state->msk_pic = pMaskPicture;
@@ -1208,12 +1106,12 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
accel_state->src_alpha = FALSE;
}
} else {
- if (!EVERGREENSetAccelState(pScrn,
- &src_obj,
- NULL,
- &dst_obj,
- accel_state->comp_vs_offset, accel_state->comp_ps_offset,
- 3, 0xffffffff))
+ if (!R600SetAccelState(pScrn,
+ &src_obj,
+ NULL,
+ &dst_obj,
+ accel_state->comp_vs_offset, accel_state->comp_ps_offset,
+ 3, 0xffffffff))
return FALSE;
accel_state->msk_pic = NULL;
@@ -1506,12 +1404,12 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
- if (!EVERGREENSetAccelState(pScrn,
- &src_obj,
- NULL,
- &dst_obj,
- accel_state->copy_vs_offset, accel_state->copy_ps_offset,
- 3, 0xffffffff)) {
+ if (!R600SetAccelState(pScrn,
+ &src_obj,
+ NULL,
+ &dst_obj,
+ accel_state->copy_vs_offset, accel_state->copy_ps_offset,
+ 3, 0xffffffff)) {
goto copy;
}
copy_dst = scratch;
@@ -1647,12 +1545,12 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
- if (!EVERGREENSetAccelState(pScrn,
- &src_obj,
- NULL,
- &dst_obj,
- accel_state->copy_vs_offset, accel_state->copy_ps_offset,
- 3, 0xffffffff)) {
+ if (!R600SetAccelState(pScrn,
+ &src_obj,
+ NULL,
+ &dst_obj,
+ accel_state->copy_vs_offset, accel_state->copy_ps_offset,
+ 3, 0xffffffff)) {
goto copy;
}
diff --git a/src/evergreen_state.h b/src/evergreen_state.h
index 5c05001..1c154df 100644
--- a/src/evergreen_state.h
+++ b/src/evergreen_state.h
@@ -327,13 +327,13 @@ evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size);
-Bool
-EVERGREENSetAccelState(ScrnInfoPtr pScrn,
- struct r600_accel_object *src0,
- struct r600_accel_object *src1,
- struct r600_accel_object *dst,
- uint32_t vs_offset, uint32_t ps_offset,
- int rop, Pixel planemask);
+extern Bool
+R600SetAccelState(ScrnInfoPtr pScrn,
+ struct r600_accel_object *src0,
+ struct r600_accel_object *src1,
+ struct r600_accel_object *dst,
+ uint32_t vs_offset, uint32_t ps_offset,
+ int rop, Pixel planemask);
extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index 39a18d6..28b5c58 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -180,12 +180,12 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
dst_obj.bpp = pPixmap->drawable.bitsPerPixel;
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
- if (!EVERGREENSetAccelState(pScrn,
- &src_obj,
- NULL,
- &dst_obj,
- accel_state->xv_vs_offset, accel_state->xv_ps_offset,
- 3, 0xffffffff))
+ if (!R600SetAccelState(pScrn,
+ &src_obj,
+ NULL,
+ &dst_obj,
+ accel_state->xv_vs_offset, accel_state->xv_ps_offset,
+ 3, 0xffffffff))
return;
#ifdef COMPOSITE
commit 7ac3a2e0bcdadff7c7172a9f833f526b526da16b
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Feb 10 14:24:50 2011 -0500
6xx+: switch to linear aligned rather than linear general
linear aligned is supposedly more performant, but more
importantly, linear general only works on the CB without
slices. The texture blocks technically don't support
linear general although, I think linear general gets
upgraded to linear aligned in the hw which is why it
currently works.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index d5ad211..06cfd95 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1130,10 +1130,8 @@ int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling)
/* further restrictions for scanout */
pitch_align = MAX(info->group_bytes / bpe, pitch_align);
} else {
- /* general surface requirements */
- pitch_align = info->group_bytes / bpe;
- /* further restrictions for scanout */
- pitch_align = MAX(32, pitch_align);
+ /* linear aligned requirements */
+ pitch_align = MAX(64, info->group_bytes / bpe);
}
} else {
/* general surface requirements */
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index f10879f..0aeac85 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -53,11 +53,17 @@ EVERGREENSetAccelState(ScrnInfoPtr pScrn,
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
+ uint32_t pitch = 0;
int ret;
if (src0) {
memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object));
accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8);
+ ret = radeon_bo_get_tiling(accel_state->src_obj[0].bo,
+ &accel_state->src_obj[0].tiling_flags,
+ &pitch);
+ if (ret)
+ RADEON_FALLBACK(("src0 radeon_bo_get_tiling failed\n"));
} else {
memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
accel_state->src_size[0] = 0;
@@ -66,6 +72,11 @@ EVERGREENSetAccelState(ScrnInfoPtr pScrn,
if (src1) {
memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object));
accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8);
+ ret = radeon_bo_get_tiling(accel_state->src_obj[1].bo,
+ &accel_state->src_obj[1].tiling_flags,
+ &pitch);
+ if (ret)
+ RADEON_FALLBACK(("src1 radeon_bo_get_tiling failed\n"));
} else {
memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
accel_state->src_size[1] = 0;
@@ -74,6 +85,11 @@ EVERGREENSetAccelState(ScrnInfoPtr pScrn,
if (dst) {
memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object));
accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
+ ret = radeon_bo_get_tiling(accel_state->dst_obj.bo,
+ &accel_state->dst_obj.tiling_flags,
+ &pitch);
+ if (ret)
+ RADEON_FALLBACK(("dst radeon_bo_get_tiling failed\n"));
} else {
memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object));
accel_state->dst_size = 0;
@@ -229,6 +245,8 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
if (accel_state->planemask & 0xff000000)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
+ if (accel_state->dst_obj.tiling_flags == 0)
+ cb_conf.array_mode = 1;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
evergreen_set_spi(pScrn, 0, 0);
@@ -391,6 +409,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
tex_samp.id = 0;
@@ -430,6 +450,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
if (accel_state->planemask & 0xff000000)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
+ if (accel_state->dst_obj.tiling_flags == 0)
+ cb_conf.array_mode = 1;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
evergreen_set_spi(pScrn, (1 - 1), 1);
@@ -990,6 +1012,8 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
+ if (accel_state->src_obj[unit].tiling_flags == 0)
+ tex_res.array_mode = 1;
evergreen_set_tex_resource (pScrn, &tex_res, accel_state->src_obj[unit].domain);
tex_samp.id = unit;
@@ -1298,6 +1322,8 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.blendcntl |= CB_BLEND0_CONTROL__ENABLE_bit;
cb_conf.rop = 3;
cb_conf.pmask = 0xf;
+ if (accel_state->dst_obj.tiling_flags == 0)
+ cb_conf.array_mode = 1;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
if (pMask)
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index 5bccfa6..39a18d6 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -265,6 +265,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* Y sampler */
@@ -296,6 +298,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* U or V sampler */
@@ -317,6 +321,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
@@ -354,6 +360,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* Y sampler */
@@ -389,6 +397,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
tex_res.size = accel_state->src_size[0];
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
@@ -425,6 +435,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.blend_clamp = 1;
cb_conf.pmask = 0xf;
cb_conf.rop = 3;
+ if (accel_state->dst_obj.tiling_flags == 0)
+ cb_conf.array_mode = 1;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
evergreen_set_spi(pScrn, (1 - 1), 1);
diff --git a/src/r600_exa.c b/src/r600_exa.c
index ea65de9..1103c35 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -53,10 +53,23 @@ R600SetAccelState(ScrnInfoPtr pScrn,
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
+ uint32_t pitch = 0;
+#if defined(XF86DRM_MODE)
+ int ret;
+#endif
if (src0) {
memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object));
accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8);
+#if defined(XF86DRM_MODE)
+ if (info->cs) {
+ ret = radeon_bo_get_tiling(accel_state->src_obj[0].bo,
+ &accel_state->src_obj[0].tiling_flags,
+ &pitch);
+ if (ret)
+ RADEON_FALLBACK(("src0 radeon_bo_get_tiling failed\n"));
+ }
+#endif
} else {
memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
accel_state->src_size[0] = 0;
@@ -65,6 +78,15 @@ R600SetAccelState(ScrnInfoPtr pScrn,
if (src1) {
memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object));
accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8);
+#if defined(XF86DRM_MODE)
+ if (info->cs) {
+ ret = radeon_bo_get_tiling(accel_state->src_obj[1].bo,
+ &accel_state->src_obj[1].tiling_flags,
+ &pitch);
+ if (ret)
+ RADEON_FALLBACK(("src1 radeon_bo_get_tiling failed\n"));
+ }
+#endif
} else {
memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
accel_state->src_size[1] = 0;
@@ -73,6 +95,15 @@ R600SetAccelState(ScrnInfoPtr pScrn,
if (dst) {
memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object));
accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
+#if defined(XF86DRM_MODE)
+ if (info->cs) {
+ ret = radeon_bo_get_tiling(accel_state->dst_obj.bo,
+ &accel_state->dst_obj.tiling_flags,
+ &pitch);
+ if (ret)
+ RADEON_FALLBACK(("dst radeon_bo_get_tiling failed\n"));
+ }
+#endif
} else {
memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object));
accel_state->dst_size = 0;
@@ -107,7 +138,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
accel_state->ps_size = 512;
#if defined(XF86DRM_MODE)
if (info->cs) {
- int ret;
accel_state->vs_mc_addr = vs_offset;
accel_state->ps_mc_addr = ps_offset;
@@ -243,6 +273,8 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
if (accel_state->planemask & 0xff000000)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
+ if (accel_state->dst_obj.tiling_flags == 0)
+ cb_conf.array_mode = 1;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_spi(pScrn, accel_state->ib, 0, 0);
@@ -402,6 +434,8 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
tex_samp.id = 0;
@@ -442,6 +476,8 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
if (accel_state->planemask & 0xff000000)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
+ if (accel_state->dst_obj.tiling_flags == 0)
+ cb_conf.array_mode = 1;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
@@ -1003,6 +1039,8 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
+ if (accel_state->src_obj[unit].tiling_flags == 0)
+ tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[unit].domain);
tex_samp.id = unit;
@@ -1350,6 +1388,8 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.blend_enable = 1;
cb_conf.pmask = 0xf;
cb_conf.rop = 3;
+ if (accel_state->dst_obj.tiling_flags == 0)
+ cb_conf.array_mode = 1;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
if (pMask)
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 8eabb08..0fb919b 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -280,6 +280,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* Y sampler */
@@ -311,6 +313,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* U or V sampler */
@@ -332,6 +336,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
@@ -370,6 +376,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* Y sampler */
@@ -406,6 +414,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
tex_res.size = accel_state->src_size[0];
+ if (accel_state->src_obj[0].tiling_flags == 0)
+ tex_res.tile_mode = 1;
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
@@ -442,6 +452,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.blend_clamp = 1;
cb_conf.pmask = 0xf;
cb_conf.rop = 3;
+ if (accel_state->dst_obj.tiling_flags == 0)
+ cb_conf.array_mode = 1;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
diff --git a/src/radeon.h b/src/radeon.h
index 4da9bf7..67a9b49 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -683,6 +683,7 @@ struct r600_accel_object {
int bpp;
uint32_t domain;
struct radeon_bo *bo;
+ uint32_t tiling_flags;
};
struct radeon_vbo_object {
commit e3145801b80fd4be4cf770128876e86e89bda66f
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Feb 10 14:14:55 2011 -0500
evergreen/NI: consolidate spi setup
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index c6c38b2..ef24e18 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -327,6 +327,22 @@ void evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix,
}
void
+evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ BEGIN_BATCH(8);
+ /* Interpolator setup */
+ EREG(SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift));
+ PACK0(SPI_PS_IN_CONTROL_0, 3);
+ E32(((num_interp << NUM_INTERP_shift) |
+ LINEAR_GRADIENT_ENA_bit)); // SPI_PS_IN_CONTROL_0
+ E32(0); // SPI_PS_IN_CONTROL_1
+ E32(0); // SPI_INTERP_CONTROL_0
+ END_BATCH();
+}
+
+void
evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -1043,7 +1059,7 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
evergreen_set_vport_scissor (pScrn, i, 0, 0, 8192, 8192);
- BEGIN_BATCH(50);
+ BEGIN_BATCH(57);
PACK0(PA_SC_MODE_CNTL_0, 2);
E32(0); // PA_SC_MODE_CNTL_0
E32(0); // PA_SC_MODE_CNTL_1
@@ -1087,6 +1103,17 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
E32(0);
E32(0);
+ /* src = semantic id 0; mask = semantic id 1 */
+ EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
+ (1 << SEMANTIC_1_shift)));
+ PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
+ /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
+ E32(((0 << SEMANTIC_shift) |
+ (0x01 << DEFAULT_VAL_shift)));
+ /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
+ E32(((1 << SEMANTIC_shift) |
+ (0x01 << DEFAULT_VAL_shift)));
+
PACK0(SPI_INPUT_Z, 8);
E32(0); // SPI_INPUT_Z
E32(0); // SPI_FOG_CNTL
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index ea01d4c..f10879f 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -231,26 +231,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_conf.rop = accel_state->rop;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
- BEGIN_BATCH(14);
- /* Interpolator setup */
- /* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
- EREG(SPI_VS_OUT_CONFIG, (0 << VS_EXPORT_COUNT_shift));
- EREG(SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
- /* color semantic id 0 -> GPR[0] */
- EREG(SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) |
- (0x03 << DEFAULT_VAL_shift) |
- FLAT_SHADE_bit));
-
- /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
- * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
- /* no VS exports as PS input (NUM_INTERP is not zero based, no minus one) */
- PACK0(SPI_PS_IN_CONTROL_0, 3);
- E32(((0 << NUM_INTERP_shift) |
- LINEAR_GRADIENT_ENA_bit)); // SPI_PS_IN_CONTROL_0
- E32(0); // SPI_PS_IN_CONTROL_1
- E32(FLAT_SHADE_ENA_bit); // SPI_INTERP_CONTROL_0
- END_BATCH();
-
+ evergreen_set_spi(pScrn, 0, 0);
/* PS alu constants */
ps_const_conf.size_bytes = 256;
@@ -451,24 +432,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.rop = accel_state->rop;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
- BEGIN_BATCH(14);
- /* Interpolator setup */
- /* export tex coord from VS */
- EREG(SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
- EREG(SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
- /* color semantic id 0 -> GPR[0] */
- EREG(SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) |
- (0x01 << DEFAULT_VAL_shift)));
-
- /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
- * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
- /* input tex coord from VS */
- PACK0(SPI_PS_IN_CONTROL_0, 3);
- E32(((1 << NUM_INTERP_shift) |
- LINEAR_GRADIENT_ENA_bit)); // SPI_PS_IN_CONTROL_0
- E32(0); //SPI_PS_IN_CONTROL_1
- E32(0); // SPI_INTERP_CONTROL_0
- END_BATCH();
+ evergreen_set_spi(pScrn, (1 - 1), 1);
}
@@ -1336,42 +1300,10 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.pmask = 0xf;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
- BEGIN_BATCH(15);
- /* Interpolator setup */
- if (pMask) {
- /* export 2 tex coords from VS */
- EREG(SPI_VS_OUT_CONFIG, ((2 - 1) << VS_EXPORT_COUNT_shift));
- /* src = semantic id 0; mask = semantic id 1 */
- EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
- (1 << SEMANTIC_1_shift)));
- } else {
- /* export 1 tex coords from VS */
- EREG(SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
- /* src = semantic id 0 */
- EREG(SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
- }
-
- PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
- /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
- E32(((0 << SEMANTIC_shift) |
- (0x01 << DEFAULT_VAL_shift)));
- /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
- E32(((1 << SEMANTIC_shift) |
- (0x01 << DEFAULT_VAL_shift)));
-
- PACK0(SPI_PS_IN_CONTROL_0, 3);
- if (pMask) {
- /* input 2 tex coords from VS */
- E32(((2 << NUM_INTERP_shift) |
- LINEAR_GRADIENT_ENA_bit)); // SPI_PS_IN_CONTROL_0
- } else {
- /* input 1 tex coords from VS */
- E32(((1 << NUM_INTERP_shift) |
- LINEAR_GRADIENT_ENA_bit)); // SPI_PS_IN_CONTROL_0
- }
- E32(0); // SPI_PS_IN_CONTROL_1
- E32(0); // SPI_INTERP_CONTROL_0
- END_BATCH();
+ if (pMask)
+ evergreen_set_spi(pScrn, (2 - 1), 2);
+ else
+ evergreen_set_spi(pScrn, (1 - 1), 1);
/* VS alu constants */
vs_const_conf.size_bytes = 256;
diff --git a/src/evergreen_state.h b/src/evergreen_state.h
index 5d03adc..5c05001 100644
--- a/src/evergreen_state.h
+++ b/src/evergreen_state.h
@@ -295,6 +295,8 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
void
evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
+evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp);
+void
evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
void
evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index 434bd2e..5bccfa6 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -427,23 +427,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.rop = 3;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
- /* Render setup */
- BEGIN_BATCH(14);
- /* Interpolator setup */
- /* export tex coords from VS */
- EREG(SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
- EREG(SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
- EREG(SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) |
- (0x03 << DEFAULT_VAL_shift)));
-
- /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
- * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
- PACK0(SPI_PS_IN_CONTROL_0, 3);
- E32(((1 << NUM_INTERP_shift) |
- LINEAR_GRADIENT_ENA_bit)); // SPI_PS_IN_CONTROL_0
- E32(0); // SPI_PS_IN_CONTROL_1
- E32(0); // SPI_INTERP_CONTROL_0
- END_BATCH();
+ evergreen_set_spi(pScrn, (1 - 1), 1);
/* PS alu constants */
ps_const_conf.size_bytes = 256;
commit be67ded05621aff9c85525372fd119071d3278ec
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Feb 10 14:06:38 2011 -0500
6xx/7xx: consolidate spi setup
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 83248b3..ea65de9 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -245,25 +245,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_conf.rop = accel_state->rop;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
- BEGIN_BATCH(14);
- /* Interpolator setup */
- /* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
- EREG(accel_state->ib, SPI_VS_OUT_CONFIG, (0 << VS_EXPORT_COUNT_shift));
- EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
- /* color semantic id 0 -> GPR[0] */
- EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) |
- (0x03 << DEFAULT_VAL_shift) |
- FLAT_SHADE_bit |
- SEL_CENTROID_bit));
-
- /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
- * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
- /* no VS exports as PS input (NUM_INTERP is not zero based, no minus one) */
- PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3);
- E32(accel_state->ib, (0 << NUM_INTERP_shift));
- E32(accel_state->ib, 0);
- E32(accel_state->ib, FLAT_SHADE_ENA_bit);
- END_BATCH();
+ r600_set_spi(pScrn, accel_state->ib, 0, 0);
/* PS alu constants */
if (accel_state->dst_obj.bpp == 16) {
@@ -346,7 +328,6 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- int pmask = 0;
cb_config_t cb_conf;
tex_resource_t tex_res;
tex_sampler_t tex_samp;
@@ -462,24 +443,8 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
- BEGIN_BATCH(14);
- /* Interpolator setup */
- /* export tex coord from VS */
- EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
- EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
- /* color semantic id 0 -> GPR[0] */
- EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) |
- (0x01 << DEFAULT_VAL_shift) |
- SEL_CENTROID_bit));
-
- /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
- * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
- /* input tex coord from VS */
- PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3);
- E32(accel_state->ib, ((1 << NUM_INTERP_shift)));
- E32(accel_state->ib, 0);
- E32(accel_state->ib, 0);
- END_BATCH();
+
+ r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
}
@@ -1387,42 +1352,10 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.rop = 3;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
- BEGIN_BATCH(15);
- /* Interpolator setup */
- if (pMask) {
- /* export 2 tex coords from VS */
- EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((2 - 1) << VS_EXPORT_COUNT_shift));
- /* src = semantic id 0; mask = semantic id 1 */
- EREG(accel_state->ib, SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
- (1 << SEMANTIC_1_shift)));
- } else {
- /* export 1 tex coords from VS */
- EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
- /* src = semantic id 0 */
- EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
- }
-
- PACK0(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
- /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
- E32(accel_state->ib, ((0 << SEMANTIC_shift) |
- (0x01 << DEFAULT_VAL_shift) |
- SEL_CENTROID_bit));
- /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
- E32(accel_state->ib, ((1 << SEMANTIC_shift) |
- (0x01 << DEFAULT_VAL_shift) |
- SEL_CENTROID_bit));
-
- PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3);
- if (pMask) {
- /* input 2 tex coords from VS */
- E32(accel_state->ib, (2 << NUM_INTERP_shift));
- } else {
- /* input 1 tex coords from VS */
- E32(accel_state->ib, (1 << NUM_INTERP_shift));
- }
- E32(accel_state->ib, 0);
- E32(accel_state->ib, 0);
- END_BATCH();
+ if (pMask)
+ r600_set_spi(pScrn, accel_state->ib, (2 - 1), 2);
+ else
+ r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
if (accel_state->vsync)
RADEONVlineHelperClear(pScrn);
diff --git a/src/r600_state.h b/src/r600_state.h
index 59670db..d5785cd 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -290,6 +290,8 @@ r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, ui
void
r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
+r600_set_spi(ScrnInfoPtr pScrn, drmBufPtr ib, int vs_export_count, int num_interp);
+void
r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
void
r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index f21d6f2..8eabb08 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -444,23 +444,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.rop = 3;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
- /* Render setup */
- BEGIN_BATCH(14);
- /* Interpolator setup */
- /* export tex coords from VS */
- EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
- EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
- EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) |
- (0x03 << DEFAULT_VAL_shift) |
- SEL_CENTROID_bit));
-
- /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
- * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
- PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3);
- E32(accel_state->ib, ((1 << NUM_INTERP_shift)));
- E32(accel_state->ib, 0);
- E32(accel_state->ib, 0);
- END_BATCH();
+ r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
vs_alu_consts[0] = 1.0 / pPriv->w;
vs_alu_consts[1] = 1.0 / pPriv->h;
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index e77f87a..a9d1cb4 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -419,6 +419,21 @@ r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
}
void
+r600_set_spi(ScrnInfoPtr pScrn, drmBufPtr ib, int vs_export_count, int num_interp)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ BEGIN_BATCH(8);
+ /* Interpolator setup */
+ EREG(ib, SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift));
+ PACK0(ib, SPI_PS_IN_CONTROL_0, 3);
+ E32(ib, (num_interp << NUM_INTERP_shift));
+ E32(ib, 0);
+ E32(ib, 0);
+ END_BATCH();
+}
+
+void
r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -1036,7 +1051,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
r600_set_vport_scissor(pScrn, ib, i, 0, 0, 8192, 8192);
- BEGIN_BATCH(42);
+ BEGIN_BATCH(49);
PACK0(ib, PA_SC_MPASS_PS_CNTL, 2);
E32(ib, 0);
if (info->ChipFamily < CHIP_FAMILY_RV770)
@@ -1080,6 +1095,19 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
else
EREG(ib, R7xx_SPI_THREAD_GROUPING, (1 << PS_GROUPING_shift));
+ /* default Interpolator setup */
+ EREG(ib, SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
+ (1 << SEMANTIC_1_shift)));
+ PACK0(ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
+ /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
+ E32(ib, ((0 << SEMANTIC_shift) |
+ (0x01 << DEFAULT_VAL_shift) |
+ SEL_CENTROID_bit));
+ /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
+ E32(ib, ((1 << SEMANTIC_shift) |
+ (0x01 << DEFAULT_VAL_shift) |
+ SEL_CENTROID_bit));
+
PACK0(ib, SPI_INPUT_Z, 4);
E32(ib, 0); // SPI_INPUT_Z
E32(ib, 0); // SPI_FOG_CNTL
commit 2c5ae1724307e0dba5d0306fe27c1e15a7390a2f
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Feb 10 13:47:53 2011 -0500
evergreen/ni: consolidate CB state handling
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index 4f5a120..c6c38b2 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -43,6 +43,25 @@
#include "radeon_vbo.h"
#include "radeon_exa_shared.h"
+static const uint32_t EVERGREEN_ROP[16] = {
+ RADEON_ROP3_ZERO, /* GXclear */
+ RADEON_ROP3_DSa, /* Gxand */
+ RADEON_ROP3_SDna, /* GXandReverse */
+ RADEON_ROP3_S, /* GXcopy */
+ RADEON_ROP3_DSna, /* GXandInverted */
+ RADEON_ROP3_D, /* GXnoop */
+ RADEON_ROP3_DSx, /* GXxor */
+ RADEON_ROP3_DSo, /* GXor */
+ RADEON_ROP3_DSon, /* GXnor */
+ RADEON_ROP3_DSxn, /* GXequiv */
+ RADEON_ROP3_Dn, /* GXinvert */
+ RADEON_ROP3_SDno, /* GXorReverse */
+ RADEON_ROP3_Sn, /* GXcopyInverted */
+ RADEON_ROP3_DSno, /* GXorInverted */
+ RADEON_ROP3_DSan, /* GXnand */
+ RADEON_ROP3_ONE, /* GXset */
+};
+
void
evergreen_start_3d(ScrnInfoPtr pScrn)
{
@@ -204,7 +223,7 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
- BEGIN_BATCH(24);
+ BEGIN_BATCH(33);
EREG(CB_COLOR0_PITCH + (0x3c * cb_conf->id), pitch);
EREG(CB_COLOR0_SLICE + (0x3c * cb_conf->id), slice);
EREG(CB_COLOR0_VIEW + (0x3c * cb_conf->id), 0);
@@ -216,7 +235,12 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
E32(0);
E32(0);
E32(0);
+ EREG(CB_TARGET_MASK, (cb_conf->pmask << TARGET0_ENABLE_shift));
+ EREG(CB_COLOR_CONTROL, (EVERGREEN_ROP[cb_conf->rop] |
+ (CB_NORMAL << CB_COLOR_CONTROL__MODE_shift)));
+ EREG(CB_BLEND0_CONTROL, cb_conf->blendcntl);
END_BATCH();
+
}
static void
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 52a5030..ea01d4c 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -43,25 +43,6 @@
#include "radeon_exa_shared.h"
#include "radeon_vbo.h"
-uint32_t EVERGREEN_ROP[16] = {
- RADEON_ROP3_ZERO, /* GXclear */
- RADEON_ROP3_DSa, /* Gxand */
- RADEON_ROP3_SDna, /* GXandReverse */
- RADEON_ROP3_S, /* GXcopy */
- RADEON_ROP3_DSna, /* GXandInverted */
- RADEON_ROP3_D, /* GXnoop */
- RADEON_ROP3_DSx, /* GXxor */
- RADEON_ROP3_DSo, /* GXor */
- RADEON_ROP3_DSon, /* GXnor */
- RADEON_ROP3_DSxn, /* GXequiv */
- RADEON_ROP3_Dn, /* GXinvert */
- RADEON_ROP3_SDno, /* GXorReverse */
- RADEON_ROP3_Sn, /* GXcopyInverted */
- RADEON_ROP3_DSno, /* GXorInverted */
- RADEON_ROP3_DSan, /* GXnand */
- RADEON_ROP3_ONE, /* GXset */
-};
-
Bool
EVERGREENSetAccelState(ScrnInfoPtr pScrn,
struct r600_accel_object *src0,
@@ -159,7 +140,6 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
struct radeon_accel_state *accel_state = info->accel_state;
cb_config_t cb_conf;
shader_config_t vs_conf, ps_conf;
- int pmask = 0;
uint32_t a, r, g, b;
float *ps_alu_consts;
const_config_t ps_const_conf;
@@ -239,24 +219,19 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
}
cb_conf.source_format = EXPORT_4C_16BPC;
cb_conf.blend_clamp = 1;
- evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
-
/* Render setup */
if (accel_state->planemask & 0x000000ff)
- pmask |= 4; /* B */
+ cb_conf.pmask |= 4; /* B */
if (accel_state->planemask & 0x0000ff00)
- pmask |= 2; /* G */
+ cb_conf.pmask |= 2; /* G */
if (accel_state->planemask & 0x00ff0000)
- pmask |= 1; /* R */
+ cb_conf.pmask |= 1; /* R */
if (accel_state->planemask & 0xff000000)
- pmask |= 8; /* A */
-
- BEGIN_BATCH(23);
- EREG(CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
- EREG(CB_COLOR_CONTROL, (EVERGREEN_ROP[accel_state->rop] |
- (CB_NORMAL << CB_COLOR_CONTROL__MODE_shift)));
- EREG(CB_BLEND0_CONTROL, 0);
+ cb_conf.pmask |= 8; /* A */
+ cb_conf.rop = accel_state->rop;
+ evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
+ BEGIN_BATCH(14);
/* Interpolator setup */
/* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
EREG(SPI_VS_OUT_CONFIG, (0 << VS_EXPORT_COUNT_shift));
@@ -363,7 +338,6 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- int pmask = 0;
cb_config_t cb_conf;
tex_resource_t tex_res;
tex_sampler_t tex_samp;
@@ -465,24 +439,19 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
}
cb_conf.source_format = EXPORT_4C_16BPC;
cb_conf.blend_clamp = 1;
- evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
-
/* Render setup */
if (accel_state->planemask & 0x000000ff)
- pmask |= 4; /* B */
+ cb_conf.pmask |= 4; /* B */
if (accel_state->planemask & 0x0000ff00)
- pmask |= 2; /* G */
+ cb_conf.pmask |= 2; /* G */
if (accel_state->planemask & 0x00ff0000)
- pmask |= 1; /* R */
+ cb_conf.pmask |= 1; /* R */
if (accel_state->planemask & 0xff000000)
- pmask |= 8; /* A */
-
- BEGIN_BATCH(23);
- EREG(CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
- EREG(CB_COLOR_CONTROL, (EVERGREEN_ROP[accel_state->rop] |
- (CB_NORMAL << CB_COLOR_CONTROL__MODE_shift)));
- EREG(CB_BLEND0_CONTROL, 0);
+ cb_conf.pmask |= 8; /* A */
+ cb_conf.rop = accel_state->rop;
+ evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
+ BEGIN_BATCH(14);
/* Interpolator setup */
/* export tex coord from VS */
EREG(SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
@@ -1191,7 +1160,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
ScrnInfoPtr pScrn = xf86Screens[pSrc->drawable.pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- uint32_t blendcntl, dst_format;
+ uint32_t dst_format;
cb_config_t cb_conf;
shader_config_t vs_conf, ps_conf;
const_config_t vs_const_conf;
@@ -1361,16 +1330,13 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
}
cb_conf.source_format = EXPORT_4C_16BPC;
cb_conf.blend_clamp = 1;
+ cb_conf.blendcntl = EVERGREENGetBlendCntl(op, pMaskPicture, pDstPicture->format);
+ cb_conf.blendcntl |= CB_BLEND0_CONTROL__ENABLE_bit;
+ cb_conf.rop = 3;
+ cb_conf.pmask = 0xf;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
- blendcntl = EVERGREENGetBlendCntl(op, pMaskPicture, pDstPicture->format);
-
- BEGIN_BATCH(24);
- EREG(CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
- EREG(CB_COLOR_CONTROL, (EVERGREEN_ROP[3] |
- (CB_NORMAL << CB_COLOR_CONTROL__MODE_shift)));
- EREG(CB_BLEND0_CONTROL, blendcntl | CB_BLEND0_CONTROL__ENABLE_bit);
-
+ BEGIN_BATCH(15);
/* Interpolator setup */
if (pMask) {
/* export 2 tex coords from VS */
diff --git a/src/evergreen_state.h b/src/evergreen_state.h
index 7e49164..5d03adc 100644
--- a/src/evergreen_state.h
+++ b/src/evergreen_state.h
@@ -86,6 +86,11 @@ typedef struct {
int fast_clear;
int compression;
int rat;
+ /* 2D related CB state */
+ uint32_t pmask;
+ int rop;
+ int blend_enable;
+ uint32_t blendcntl;
struct radeon_bo *bo;
} cb_config_t;
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index d60d194..434bd2e 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -423,15 +423,12 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.source_format = EXPORT_4C_16BPC;
cb_conf.blend_clamp = 1;
+ cb_conf.pmask = 0xf;
+ cb_conf.rop = 3;
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
/* Render setup */
- BEGIN_BATCH(23);
- EREG(CB_TARGET_MASK, (0x0f << TARGET0_ENABLE_shift));
- EREG(CB_COLOR_CONTROL, ((0xcc << ROP3_shift) |
- (CB_NORMAL << CB_COLOR_CONTROL__MODE_shift)));
- EREG(CB_BLEND0_CONTROL, 0);
-
+ BEGIN_BATCH(14);
/* Interpolator setup */
/* export tex coords from VS */
EREG(SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
commit c52d817b51e13447802fe338be2d247ffba2a669
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Feb 10 13:35:02 2011 -0500
6xx/7xx: consolidate remaining CB state
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 631cf39..83248b3 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -43,25 +43,6 @@
/* #define SHOW_VERTEXES */
-uint32_t R600_ROP[16] = {
- RADEON_ROP3_ZERO, /* GXclear */
- RADEON_ROP3_DSa, /* Gxand */
- RADEON_ROP3_SDna, /* GXandReverse */
- RADEON_ROP3_S, /* GXcopy */
- RADEON_ROP3_DSna, /* GXandInverted */
- RADEON_ROP3_D, /* GXnoop */
- RADEON_ROP3_DSx, /* GXxor */
- RADEON_ROP3_DSo, /* GXor */
- RADEON_ROP3_DSon, /* GXnor */
- RADEON_ROP3_DSxn, /* GXequiv */
- RADEON_ROP3_Dn, /* GXinvert */
- RADEON_ROP3_SDno, /* GXorReverse */
- RADEON_ROP3_Sn, /* GXcopyInverted */
- RADEON_ROP3_DSno, /* GXorInverted */
- RADEON_ROP3_DSan, /* GXnand */
- RADEON_ROP3_ONE, /* GXset */
-};
-
Bool
R600SetAccelState(ScrnInfoPtr pScrn,
struct r600_accel_object *src0,
@@ -169,7 +150,6 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
struct radeon_accel_state *accel_state = info->accel_state;
cb_config_t cb_conf;
shader_config_t vs_conf, ps_conf;
- int pmask = 0;
uint32_t a, r, g, b;
float ps_alu_consts[4];
struct r600_accel_object dst;
@@ -253,21 +233,19 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
-
/* Render setup */
if (accel_state->planemask & 0x000000ff)
- pmask |= 4; /* B */
+ cb_conf.pmask |= 4; /* B */
if (accel_state->planemask & 0x0000ff00)
- pmask |= 2; /* G */
+ cb_conf.pmask |= 2; /* G */
if (accel_state->planemask & 0x00ff0000)
- pmask |= 1; /* R */
+ cb_conf.pmask |= 1; /* R */
if (accel_state->planemask & 0xff000000)
- pmask |= 8; /* A */
- BEGIN_BATCH(20);
- EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
- EREG(accel_state->ib, CB_COLOR_CONTROL, R600_ROP[accel_state->rop]);
+ cb_conf.pmask |= 8; /* A */
+ cb_conf.rop = accel_state->rop;
+ r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
+ BEGIN_BATCH(14);
/* Interpolator setup */
/* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
EREG(accel_state->ib, SPI_VS_OUT_CONFIG, (0 << VS_EXPORT_COUNT_shift));
@@ -472,21 +450,19 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
- r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
/* Render setup */
if (accel_state->planemask & 0x000000ff)
- pmask |= 4; /* B */
+ cb_conf.pmask |= 4; /* B */
if (accel_state->planemask & 0x0000ff00)
- pmask |= 2; /* G */
+ cb_conf.pmask |= 2; /* G */
if (accel_state->planemask & 0x00ff0000)
- pmask |= 1; /* R */
+ cb_conf.pmask |= 1; /* R */
if (accel_state->planemask & 0xff000000)
- pmask |= 8; /* A */
- BEGIN_BATCH(20);
- EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
- EREG(accel_state->ib, CB_COLOR_CONTROL, R600_ROP[accel_state->rop]);
-
+ cb_conf.pmask |= 8; /* A */
+ cb_conf.rop = accel_state->rop;
+ r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
+ BEGIN_BATCH(14);
/* Interpolator setup */
/* export tex coord from VS */
EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
@@ -1226,7 +1202,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
ScrnInfoPtr pScrn = xf86Screens[pSrc->drawable.pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- uint32_t blendcntl, dst_format;
+ uint32_t dst_format;
cb_config_t cb_conf;
shader_config_t vs_conf, ps_conf;
struct r600_accel_object src_obj, mask_obj, dst_obj;
@@ -1405,24 +1381,13 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
+ cb_conf.blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format);
+ cb_conf.blend_enable = 1;
+ cb_conf.pmask = 0xf;
+ cb_conf.rop = 3;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
- BEGIN_BATCH(24);
- EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
-
- blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format);
-
- if (info->ChipFamily == CHIP_FAMILY_R600) {
- /* no per-MRT blend on R600 */
- EREG(accel_state->ib, CB_COLOR_CONTROL, R600_ROP[3] | (1 << TARGET_BLEND_ENABLE_shift));
- EREG(accel_state->ib, CB_BLEND_CONTROL, blendcntl);
- } else {
- EREG(accel_state->ib, CB_COLOR_CONTROL, (R600_ROP[3] |
- (1 << TARGET_BLEND_ENABLE_shift) |
- PER_MRT_BLEND_bit));
- EREG(accel_state->ib, CB_BLEND0_CONTROL, blendcntl);
- }
-
+ BEGIN_BATCH(15);
/* Interpolator setup */
if (pMask) {
/* export 2 tex coords from VS */
diff --git a/src/r600_state.h b/src/r600_state.h
index 1e8dea3..59670db 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -50,6 +50,11 @@ typedef struct {
int round_mode;
int tile_compact;
int source_format;
+ /* 2D related CB state */
+ uint32_t pmask;
+ int rop;
+ int blend_enable;
+ uint32_t blendcntl;
struct radeon_bo *bo;
} cb_config_t;
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index f71a61b..f21d6f2 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -440,13 +440,12 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
+ cb_conf.pmask = 0xf;
+ cb_conf.rop = 3;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
/* Render setup */
- BEGIN_BATCH(20);
- EREG(accel_state->ib, CB_TARGET_MASK, (0x0f << TARGET0_ENABLE_shift));
- EREG(accel_state->ib, CB_COLOR_CONTROL, (0xcc << ROP3_shift)); /* copy */
-
+ BEGIN_BATCH(14);
/* Interpolator setup */
/* export tex coords from VS */
EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 0c7714a..e77f87a 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -41,6 +41,25 @@
#include "radeon_vbo.h"
#include "radeon_exa_shared.h"
+static const uint32_t R600_ROP[16] = {
+ RADEON_ROP3_ZERO, /* GXclear */
+ RADEON_ROP3_DSa, /* Gxand */
+ RADEON_ROP3_SDna, /* GXandReverse */
+ RADEON_ROP3_S, /* GXcopy */
+ RADEON_ROP3_DSna, /* GXandInverted */
+ RADEON_ROP3_D, /* GXnoop */
+ RADEON_ROP3_DSx, /* GXxor */
+ RADEON_ROP3_DSo, /* GXor */
+ RADEON_ROP3_DSon, /* GXnor */
+ RADEON_ROP3_DSxn, /* GXequiv */
+ RADEON_ROP3_Dn, /* GXinvert */
+ RADEON_ROP3_SDno, /* GXorReverse */
+ RADEON_ROP3_Sn, /* GXcopyInverted */
+ RADEON_ROP3_DSno, /* GXorInverted */
+ RADEON_ROP3_DSan, /* GXnand */
+ RADEON_ROP3_ONE, /* GXset */
+};
+
/* we try and batch operations together under KMS -
but it doesn't work yet without misrendering */
#define KMS_MULTI_OP 1
@@ -203,7 +222,7 @@ r600_sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
void
r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
{
- uint32_t cb_color_info;
+ uint32_t cb_color_info, cb_color_control;
int pitch, slice, h;
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -276,6 +295,21 @@ r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, ui
RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
+ BEGIN_BATCH(9);
+ EREG(ib, CB_TARGET_MASK, (cb_conf->pmask << TARGET0_ENABLE_shift));
+ cb_color_control = R600_ROP[cb_conf->rop] |
+ (cb_conf->blend_enable << TARGET_BLEND_ENABLE_shift);
+ if (info->ChipFamily == CHIP_FAMILY_R600) {
+ /* no per-MRT blend on R600 */
+ EREG(ib, CB_COLOR_CONTROL, cb_color_control);
+ EREG(ib, CB_BLEND_CONTROL, cb_conf->blendcntl);
+ } else {
+ if (cb_conf->blend_enable)
+ cb_color_control |= PER_MRT_BLEND_bit;
+ EREG(ib, CB_COLOR_CONTROL, cb_color_control);
+ EREG(ib, CB_BLEND0_CONTROL, cb_conf->blendcntl);
+ }
+ END_BATCH();
}
static void
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