xf86-video-ati: Branch 'master'
Alex Deucher
agd5f at kemper.freedesktop.org
Wed Apr 20 00:14:47 PDT 2011
src/evergreen_exa.c | 10 ++++++++++
src/evergreen_textured_videofuncs.c | 18 ++++++------------
src/r600_exa.c | 26 ++++++++++----------------
src/r600_textured_videofuncs.c | 4 +++-
src/radeon.h | 1 +
src/radeon_exa.c | 7 +++++++
6 files changed, 37 insertions(+), 29 deletions(-)
New commits:
commit 903e90c31cf0319be9297529aa7b8daa1756cf63
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Wed Apr 20 03:10:08 2011 -0400
EXA/Xv: used cached bo tiling flags for accel setup on 6xx+
This avoids calling into the kernel for each bo in the accel
code. This is a follow on to:
cc7d1fa39da40a532fcdbe6c7924ca47a879e66a
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index d93cb42..d257939 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -68,6 +68,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
dst.offset = 0;
dst.bo = radeon_get_pixmap_bo(pPix);
+ dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
dst.pitch = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8);
dst.width = pPix->drawable.width;
@@ -448,6 +449,8 @@ EVERGREENPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
dst_obj.offset = 0;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.bo = radeon_get_pixmap_bo(pDst);
+ dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
+ src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))
accel_state->same_surface = TRUE;
@@ -1095,6 +1098,8 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
dst_obj.offset = 0;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.bo = radeon_get_pixmap_bo(pDst);
+ dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
+ src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
@@ -1112,6 +1117,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
if (pMask) {
mask_obj.offset = 0;
mask_obj.bo = radeon_get_pixmap_bo(pMask);
+ mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8);
mask_obj.width = pMask->drawable.width;
@@ -1438,6 +1444,7 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
src_obj.bpp = bpp;
src_obj.domain = RADEON_GEM_DOMAIN_GTT;
src_obj.bo = scratch;
+ src_obj.tiling_flags = 0;
dst_obj.pitch = dst_pitch_hw;
dst_obj.width = pDst->drawable.width;
@@ -1446,6 +1453,7 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
+ dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
if (!R600SetAccelState(pScrn,
&src_obj,
@@ -1575,6 +1583,7 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
src_obj.bpp = bpp;
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
+ src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
dst_obj.pitch = scratch_pitch;
dst_obj.width = w;
@@ -1583,6 +1592,7 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
dst_obj.bo = scratch;
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
+ dst_obj.tiling_flags = 0;
if (!R600SetAccelState(pScrn,
&src_obj,
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index 147cd4e..6200cdc 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -154,18 +154,11 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
CLEAR (vs_const_conf);
CLEAR (ps_const_conf);
-#if defined(XF86DRM_MODE)
- if (info->cs) {
- dst_obj.offset = 0;
- src_obj.offset = 0;
- dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
- } else
-#endif
- {
- dst_obj.offset = exaGetPixmapOffset(pPixmap) + info->fbLocation + pScrn->fbOffset;
- src_obj.offset = pPriv->src_offset + info->fbLocation + pScrn->fbOffset;
- dst_obj.bo = src_obj.bo = NULL;
- }
+ dst_obj.offset = 0;
+ src_obj.offset = 0;
+ dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
+ dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
+
dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8);
src_obj.pitch = pPriv->src_pitch;
@@ -174,6 +167,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
src_obj.bpp = 16;
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = pPriv->src_bo[pPriv->currentBuffer];
+ src_obj.tiling_flags = 0;
dst_obj.width = pPixmap->drawable.width;
dst_obj.height = pPixmap->drawable.height;
diff --git a/src/r600_exa.c b/src/r600_exa.c
index c6a244c..2673599 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -53,7 +53,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- uint32_t pitch = 0;
uint32_t pitch_align = 0x7, base_align = 0xff;
#if defined(XF86DRM_MODE)
int ret;
@@ -64,11 +63,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8);
#if defined(XF86DRM_MODE)
if (info->cs) {
- ret = radeon_bo_get_tiling(accel_state->src_obj[0].bo,
- &accel_state->src_obj[0].tiling_flags,
- &pitch);
- if (ret)
- RADEON_FALLBACK(("src0 radeon_bo_get_tiling failed\n"));
pitch_align = drmmode_get_pitch_align(pScrn,
accel_state->src_obj[0].bpp / 8,
accel_state->src_obj[0].tiling_flags) - 1;
@@ -95,11 +89,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8);
#if defined(XF86DRM_MODE)
if (info->cs) {
- ret = radeon_bo_get_tiling(accel_state->src_obj[1].bo,
- &accel_state->src_obj[1].tiling_flags,
- &pitch);
- if (ret)
- RADEON_FALLBACK(("src1 radeon_bo_get_tiling failed\n"));
pitch_align = drmmode_get_pitch_align(pScrn,
accel_state->src_obj[1].bpp / 8,
accel_state->src_obj[1].tiling_flags) - 1;
@@ -125,11 +114,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
#if defined(XF86DRM_MODE)
if (info->cs) {
- ret = radeon_bo_get_tiling(accel_state->dst_obj.bo,
- &accel_state->dst_obj.tiling_flags,
- &pitch);
- if (ret)
- RADEON_FALLBACK(("dst radeon_bo_get_tiling failed\n"));
pitch_align = drmmode_get_pitch_align(pScrn,
accel_state->dst_obj.bpp / 8,
accel_state->dst_obj.tiling_flags) - 1;
@@ -210,6 +194,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
if (info->cs) {
dst.offset = 0;
dst.bo = radeon_get_pixmap_bo(pPix);
+ dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
} else
#endif
{
@@ -589,6 +574,8 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
dst_obj.offset = 0;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.bo = radeon_get_pixmap_bo(pDst);
+ dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
+ src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))
accel_state->same_surface = TRUE;
} else
@@ -1269,6 +1256,8 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
dst_obj.offset = 0;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.bo = radeon_get_pixmap_bo(pDst);
+ dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
+ src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
} else
#endif
{
@@ -1295,6 +1284,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
if (info->cs) {
mask_obj.offset = 0;
mask_obj.bo = radeon_get_pixmap_bo(pMask);
+ mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
} else
#endif
{
@@ -1820,6 +1810,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
src_obj.bpp = bpp;
src_obj.domain = RADEON_GEM_DOMAIN_GTT;
src_obj.bo = scratch;
+ src_obj.tiling_flags = 0;
dst_obj.pitch = dst_pitch_hw;
dst_obj.width = pDst->drawable.width;
@@ -1828,6 +1819,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
+ dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
if (!R600SetAccelState(pScrn,
&src_obj,
@@ -1953,6 +1945,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
src_obj.bpp = bpp;
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
+ src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
dst_obj.pitch = scratch_pitch;
dst_obj.width = w;
@@ -1961,6 +1954,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
dst_obj.bo = scratch;
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
+ dst_obj.tiling_flags = 0;
if (!R600SetAccelState(pScrn,
&src_obj,
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 4ff0833..aab43f3 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -169,6 +169,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
dst_obj.offset = 0;
src_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
+ dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
} else
#endif
{
@@ -184,7 +185,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
src_obj.bpp = 16;
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = pPriv->src_bo[pPriv->currentBuffer];
-
+ src_obj.tiling_flags = 0;
+
dst_obj.width = pPixmap->drawable.width;
dst_obj.height = pPixmap->drawable.height;
dst_obj.bpp = pPixmap->drawable.bitsPerPixel;
diff --git a/src/radeon.h b/src/radeon.h
index 9283c4d..f655040 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1384,6 +1384,7 @@ void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size);
#endif
struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo);
+uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix);
#ifdef XF86DRI
# ifdef USE_XAA
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index c11c938..f3daec0 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -532,6 +532,13 @@ struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix)
return driver_priv->bo;
}
+uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix)
+{
+ struct radeon_exa_pixmap_priv *driver_priv;
+ driver_priv = exaGetPixmapDriverPrivate(pPix);
+ return driver_priv->tiling_flags;
+}
+
void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
{
struct radeon_exa_pixmap_priv *driver_priv;
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