xf86-video-ati: Branch 'master' - 2 commits
Michel Dänzer
daenzer at kemper.freedesktop.org
Tue Apr 5 05:43:11 PDT 2011
src/evergreen_exa.c | 16 ++------
src/r600_exa.c | 16 ++------
src/radeon.h | 5 --
src/radeon_dri2.c | 95 ++++++++++++++++++++++++++++---------------------
src/radeon_exa.c | 22 +++++++----
src/radeon_exa_funcs.c | 14 +------
6 files changed, 81 insertions(+), 87 deletions(-)
New commits:
commit cc7d1fa39da40a532fcdbe6c7924ca47a879e66a
Author: Michel Dänzer <daenzer at vmware.com>
Date: Mon Apr 4 17:37:12 2011 +0200
EXA: Cache BO tiling flags.
Calling into the kernel every time is quite expensive, and nobody else should
ever change the tiling flags.
There's still more to do along the same lines for >= R6xx.
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index ae73e38..d93cb42 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -1402,7 +1402,7 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
Bool r;
int i;
struct r600_accel_object src_obj, dst_obj;
- uint32_t tiling_flags = 0, pitch = 0, height, base_align;
+ uint32_t height, base_align;
if (bpp < 8)
return FALSE;
@@ -1411,14 +1411,10 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
/* If we know the BO won't be busy, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
@@ -1519,7 +1515,7 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
Bool flush = FALSE;
Bool r;
struct r600_accel_object src_obj, dst_obj;
- uint32_t tiling_flags = 0, pitch = 0, height, base_align;
+ uint32_t height, base_align;
if (bpp < 8)
return FALSE;
@@ -1528,14 +1524,10 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
/* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
copy_src = driver_priv->bo;
copy_pitch = pSrc->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
src_domain = radeon_bo_get_src_domain(driver_priv->bo);
if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 7736d24..c6a244c 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -1784,7 +1784,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
Bool r;
int i;
struct r600_accel_object src_obj, dst_obj;
- uint32_t tiling_flags = 0, pitch = 0, height, base_align;
+ uint32_t height, base_align;
if (bpp < 8)
return FALSE;
@@ -1793,14 +1793,10 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
/* If we know the BO won't be busy, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
@@ -1901,7 +1897,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
Bool flush = FALSE;
Bool r;
struct r600_accel_object src_obj, dst_obj;
- uint32_t tiling_flags = 0, pitch = 0, height, base_align;
+ uint32_t height, base_align;
if (bpp < 8)
return FALSE;
@@ -1910,14 +1906,10 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
/* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
copy_src = driver_priv->bo;
copy_pitch = pSrc->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
src_domain = radeon_bo_get_src_domain(driver_priv->bo);
if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
diff --git a/src/radeon.h b/src/radeon.h
index a6d20d7..9283c4d 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -495,7 +495,7 @@ typedef struct _atomBiosHandle *atomBiosHandlePtr;
struct radeon_exa_pixmap_priv {
struct radeon_bo *bo;
- int flags;
+ uint32_t tiling_flags;
Bool bo_mapped;
};
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 1c647b9..c11c938 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -130,6 +130,13 @@ static Bool RADEONPixmapIsColortiled(PixmapPtr pPix)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
+#ifdef XF86DRM_MODE
+ if (info->cs) {
+ /* Taken care of by the kernel relocation handling */
+ return FALSE;
+ }
+#endif
+
/* This doesn't account for the back buffer, which we may want to wrap in
* a pixmap at some point for the purposes of DRI buffer moves.
*/
@@ -308,7 +315,6 @@ Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index)
#endif
Bool flush = FALSE;
int ret;
- uint32_t tiling_flags = 0, pitch = 0;
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* May need to handle byte swapping in DownloadFrom/UploadToScreen */
@@ -320,12 +326,8 @@ Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index)
if (!driver_priv)
return FALSE;
- /* check if we are tiled */
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- return FALSE;
/* untile in DFS/UTS */
- if (tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))
+ if (driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))
return FALSE;
/* if we have more refs than just the BO then flush */
@@ -505,8 +507,8 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
return NULL;
}
- if (tiling)
- radeon_bo_set_tiling(new_priv->bo, tiling, *new_pitch);
+ if (tiling && !radeon_bo_set_tiling(new_priv->bo, tiling, *new_pitch))
+ new_priv->tiling_flags = tiling;
return new_priv;
}
@@ -536,11 +538,15 @@ void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
driver_priv = exaGetPixmapDriverPrivate(pPix);
if (driver_priv) {
+ uint32_t pitch;
+
if (driver_priv->bo)
radeon_bo_unref(driver_priv->bo);
radeon_bo_ref(bo);
driver_priv->bo = bo;
+
+ radeon_bo_get_tiling(bo, &driver_priv->tiling_flags, &pitch);
}
}
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index e8c5571..b6767f0 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -474,7 +474,6 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
Bool flush = TRUE;
Bool r;
int i;
- uint32_t tiling_flags = 0, pitch = 0;
if (bpp < 8)
return FALSE;
@@ -483,10 +482,6 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (bpp) {
case 32:
@@ -501,7 +496,7 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
/* If we know the BO won't be busy, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
@@ -580,7 +575,6 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
int ret;
Bool flush = FALSE;
Bool r;
- uint32_t tiling_flags = 0, pitch = 0;
if (bpp < 8)
return FALSE;
@@ -589,10 +583,6 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (bpp) {
case 32:
@@ -607,7 +597,7 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
/* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
copy_src = driver_priv->bo;
copy_pitch = pSrc->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
src_domain = radeon_bo_get_src_domain(driver_priv->bo);
if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
commit f0b7d7b449cc77bb2b281d81108507f8bc2e6018
Author: Michel Dänzer <daenzer at vmware.com>
Date: Tue Apr 5 13:36:01 2011 +0200
DRI2: Some cleanups for the scheduling mess.
* Fix build against libdrm that doesn't define *_VBLANK_HIGH_CRTC*.
* If we have more than two CRTCs but can't use DRM_VBLANK_HIGH_CRTC_MASK, don't
enable scheduling in the first place rather than relying on
DRM_VBLANK_SECONDARY magically doing something sensible for higher CRTCs.
* Only set up client state tracking when scheduling is enabled.
* Only declare pRADEONEnt when it's needed, and break long lines.
diff --git a/src/radeon.h b/src/radeon.h
index 1a746c7..a6d20d7 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -931,9 +931,6 @@ typedef struct {
RADEONFBLayout CurrentLayout;
-#ifdef RADEON_DRI2
- Bool high_crtc_works;
-#endif
#ifdef XF86DRI
Bool directRenderingEnabled;
Bool directRenderingInited;
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 8b31483..e618cc5 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -777,13 +777,16 @@ static drmVBlankSeqType populate_vbl_request_type(RADEONInfoPtr info, int crtc)
if (crtc == 1)
type |= DRM_VBLANK_SECONDARY;
- else if (crtc > 1) {
- if (info->high_crtc_works) {
- type |= (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) &
+ else if (crtc > 1)
+#ifdef DRM_VBLANK_HIGH_CRTC_MASK
+ type |= (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) &
DRM_VBLANK_HIGH_CRTC_MASK;
- } else
- type |= DRM_VBLANK_SECONDARY;
- }
+#else
+ ErrorF("radeon driver bug: %s called for CRTC %d > 1, but "
+ "DRM_VBLANK_HIGH_CRTC_MASK not defined at build time\n",
+ __func__, crtc);
+#endif
+
return type;
}
@@ -1221,12 +1224,12 @@ Bool
radeon_dri2_screen_init(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
DRI2InfoRec dri2_info = { 0 };
#ifdef USE_DRI2_SCHEDULING
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
const char *driverNames[1];
- uint64_t cap_value;
+ Bool scheduling_works = TRUE;
#endif
if (!info->useEXA) {
@@ -1258,9 +1261,34 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
#endif
dri2_info.CopyRegion = radeon_dri2_copy_region;
- info->high_crtc_works = FALSE;
#ifdef USE_DRI2_SCHEDULING
- if (info->dri->pKernelDRMVersion->version_minor >= 4) {
+ if (info->dri->pKernelDRMVersion->version_minor < 4) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for "
+ "sync extension\n");
+ scheduling_works = FALSE;
+ }
+
+ if (scheduling_works && info->drmmode.mode_res->count_crtcs > 2) {
+#ifdef DRM_CAP_VBLANK_HIGH_CRTC
+ uint64_t cap_value;
+
+ if (drmGetCap(info->dri2.drm_fd, DRM_CAP_VBLANK_HIGH_CRTC, &cap_value)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel "
+ "for VBLANKs on CRTC > 1\n");
+ scheduling_works = FALSE;
+ } else if (!cap_value) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Your kernel does not "
+ "handle VBLANKs on CRTC > 1\n");
+ scheduling_works = FALSE;
+ }
+#else
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need to rebuild against a "
+ "newer libdrm to handle VBLANKs on CRTC > 1\n");
+ scheduling_works = FALSE;
+#endif
+ }
+
+ if (scheduling_works) {
dri2_info.version = 4;
dri2_info.ScheduleSwap = radeon_dri2_schedule_swap;
dri2_info.GetMSC = radeon_dri2_get_msc;
@@ -1268,40 +1296,29 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
dri2_info.numDrivers = 1;
dri2_info.driverNames = driverNames;
driverNames[0] = dri2_info.driverName;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for sync extension\n");
- }
- if (info->drmmode.mode_res->count_crtcs > 2) {
- if (drmGetCap(info->dri2.drm_fd, DRM_CAP_VBLANK_HIGH_CRTC, &cap_value)) {
- info->high_crtc_works = FALSE;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for VBLANKs on CRTC > 1\n");
- } else {
- if (cap_value) {
- info->high_crtc_works = TRUE;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Your kernel does not handle VBLANKs on CRTC > 1\n");
- info->high_crtc_works = FALSE;
- }
- }
- }
-
- if (pRADEONEnt->dri2_info_cnt == 0) {
+ if (pRADEONEnt->dri2_info_cnt == 0) {
#if HAS_DIXREGISTERPRIVATEKEY
- if (!dixRegisterPrivateKey(DRI2ClientEventsPrivateKey, PRIVATE_CLIENT, sizeof(DRI2ClientEventsRec))) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI2 registering private key to client failed\n");
- return FALSE;
- }
+ if (!dixRegisterPrivateKey(DRI2ClientEventsPrivateKey,
+ PRIVATE_CLIENT, sizeof(DRI2ClientEventsRec))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI2 registering "
+ "private key to client failed\n");
+ return FALSE;
+ }
#else
- if (!dixRequestPrivate(DRI2ClientEventsPrivateKey, sizeof(DRI2ClientEventsRec))) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI2 requesting private key to client failed\n");
- return FALSE;
- }
+ if (!dixRequestPrivate(DRI2ClientEventsPrivateKey,
+ sizeof(DRI2ClientEventsRec))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI2 requesting "
+ "private key to client failed\n");
+ return FALSE;
+ }
#endif
- AddCallback(&ClientStateCallback, radeon_dri2_client_state_changed, 0);
+ AddCallback(&ClientStateCallback, radeon_dri2_client_state_changed, 0);
+ }
+
+ pRADEONEnt->dri2_info_cnt++;
}
- pRADEONEnt->dri2_info_cnt++;
#endif
info->dri2.enabled = DRI2ScreenInit(pScreen, &dri2_info);
@@ -1312,9 +1329,9 @@ void radeon_dri2_close_screen(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
+#ifdef USE_DRI2_SCHEDULING
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-#ifdef USE_DRI2_SCHEDULING
if (--pRADEONEnt->dri2_info_cnt == 0)
DeleteCallback(&ClientStateCallback, radeon_dri2_client_state_changed, 0);
#endif
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