xf86-video-ati: Branch 'master' - 2 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Apr 4 08:09:28 PDT 2011
src/ati_pciids_gen.h | 2 +
src/pcidb/ati_pciids.csv | 2 +
src/radeon.h | 3 ++
src/radeon_chipinfo_gen.h | 2 +
src/radeon_chipset_gen.h | 2 +
src/radeon_dri2.c | 53 +++++++++++++++++++++++++++-----------
src/radeon_pci_chipset_gen.h | 2 +
src/radeon_pci_device_match_gen.h | 2 +
8 files changed, 54 insertions(+), 14 deletions(-)
New commits:
commit 7acf9bc833de539fa2259a051c66a99445a54bc4
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Apr 4 11:08:37 2011 -0400
radeon: add some additional ontario pci ids
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 598dd72..ba46c17 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -461,6 +461,8 @@
#define PCI_CHIP_PALM_9803 0x9803
#define PCI_CHIP_PALM_9804 0x9804
#define PCI_CHIP_PALM_9805 0x9805
+#define PCI_CHIP_PALM_9806 0x9806
+#define PCI_CHIP_PALM_9807 0x9807
#define PCI_CHIP_CYPRESS_6880 0x6880
#define PCI_CHIP_CYPRESS_6888 0x6888
#define PCI_CHIP_CYPRESS_6889 0x6889
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 07454af..fd1fdbc 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -462,6 +462,8 @@
"0x9803","PALM_9803","PALM",,1,,,1,"AMD Radeon HD 6310 Graphics"
"0x9804","PALM_9804","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics"
"0x9805","PALM_9805","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics"
+"0x9806","PALM_9806","PALM",,1,,,1,"AMD Radeon HD 6300 Series Graphics"
+"0x9807","PALM_9807","PALM",,1,,,1,"AMD Radeon HD 6200 Series Graphics"
"0x6880","CYPRESS_6880","CYPRESS",1,,,,,"CYPRESS"
"0x6888","CYPRESS_6888","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
"0x6889","CYPRESS_6889","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index 2caeed9..630154b 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -381,6 +381,8 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9803, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x9804, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x9805, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
+ { 0x9806, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
+ { 0x9807, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x6880, CHIP_FAMILY_CYPRESS, 1, 0, 0, 0, 0 },
{ 0x6888, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
{ 0x6889, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index e4c38f0..9996e0a 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -381,6 +381,8 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_PALM_9803, "AMD Radeon HD 6310 Graphics" },
{ PCI_CHIP_PALM_9804, "AMD Radeon HD 6250 Graphics" },
{ PCI_CHIP_PALM_9805, "AMD Radeon HD 6250 Graphics" },
+ { PCI_CHIP_PALM_9806, "AMD Radeon HD 6300 Series Graphics" },
+ { PCI_CHIP_PALM_9807, "AMD Radeon HD 6200 Series Graphics" },
{ PCI_CHIP_CYPRESS_6880, "CYPRESS" },
{ PCI_CHIP_CYPRESS_6888, "ATI FirePro (FireGL) Graphics Adapter" },
{ PCI_CHIP_CYPRESS_6889, "ATI FirePro (FireGL) Graphics Adapter" },
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 1165049..67fec23 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -381,6 +381,8 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_PALM_9803, PCI_CHIP_PALM_9803, RES_SHARED_VGA },
{ PCI_CHIP_PALM_9804, PCI_CHIP_PALM_9804, RES_SHARED_VGA },
{ PCI_CHIP_PALM_9805, PCI_CHIP_PALM_9805, RES_SHARED_VGA },
+ { PCI_CHIP_PALM_9806, PCI_CHIP_PALM_9806, RES_SHARED_VGA },
+ { PCI_CHIP_PALM_9807, PCI_CHIP_PALM_9807, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6880, PCI_CHIP_CYPRESS_6880, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6888, PCI_CHIP_CYPRESS_6888, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6889, PCI_CHIP_CYPRESS_6889, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 4bebfeb..60b975c 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -381,6 +381,8 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9803, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9804, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9805, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_PALM_9806, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_PALM_9807, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6880, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6888, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6889, 0 ),
commit 0af6386f85a0f1ba14864a3334164733a10a6cb8
Author: Ilija Hadzic <ihadzic at research.bell-labs.com>
Date: Thu Mar 24 13:33:27 2011 -0400
xf86-video-ati: (revised #2) add support for vblank on crtc > 1
Hi Alex,
Enclosed is a revised version of two patches sent on Mar 18 and Mar 22,
respectively. Details summarized in these two threads:
http://lists.freedesktop.org/archives/dri-devel/2011-March/009463.html
http://lists.freedesktop.org/archives/dri-devel/2011-March/009582.html
This patch reconciles the DDX with the change in libdrm sent to this list
earlier today. Specifically, it refers to a symbol that has been renamed
from DRM_CAP_HIGH_CRTC to DRM_CAP_VBLANK_HIGH_CRTC. It *supersedes* the
previous patch (i.e. apply it to the master branch as it exists at the
time of this writing, not as an incremental patch to the one sent previously).
Regards,
Ilija
Signed-off-by: Ilija Hadzic <ihadzic at research.bell-labs.com>
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/radeon.h b/src/radeon.h
index a6d20d7..1a746c7 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -931,6 +931,9 @@ typedef struct {
RADEONFBLayout CurrentLayout;
+#ifdef RADEON_DRI2
+ Bool high_crtc_works;
+#endif
#ifdef XF86DRI
Bool directRenderingEnabled;
Bool directRenderingInited;
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 66df03c..8b31483 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -771,6 +771,22 @@ cleanup:
free(event);
}
+static drmVBlankSeqType populate_vbl_request_type(RADEONInfoPtr info, int crtc)
+{
+ drmVBlankSeqType type = 0;
+
+ if (crtc == 1)
+ type |= DRM_VBLANK_SECONDARY;
+ else if (crtc > 1) {
+ if (info->high_crtc_works) {
+ type |= (crtc << DRM_VBLANK_HIGH_CRTC_SHIFT) &
+ DRM_VBLANK_HIGH_CRTC_MASK;
+ } else
+ type |= DRM_VBLANK_SECONDARY;
+ }
+ return type;
+}
+
/*
* Get current frame count and frame count timestamp, based on drawable's
* crtc.
@@ -791,8 +807,7 @@ static int radeon_dri2_get_msc(DrawablePtr draw, CARD64 *ust, CARD64 *msc)
return TRUE;
}
vbl.request.type = DRM_VBLANK_RELATIVE;
- if (crtc > 0)
- vbl.request.type |= DRM_VBLANK_SECONDARY;
+ vbl.request.type |= populate_vbl_request_type(info, crtc);
vbl.request.sequence = 0;
ret = drmWaitVBlank(info->dri2.drm_fd, &vbl);
@@ -855,8 +870,7 @@ static int radeon_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw,
/* Get current count */
vbl.request.type = DRM_VBLANK_RELATIVE;
- if (crtc > 0)
- vbl.request.type |= DRM_VBLANK_SECONDARY;
+ vbl.request.type |= populate_vbl_request_type(info, crtc);
vbl.request.sequence = 0;
ret = drmWaitVBlank(info->dri2.drm_fd, &vbl);
if (ret) {
@@ -882,8 +896,7 @@ static int radeon_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw,
if (current_msc >= target_msc)
target_msc = current_msc;
vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
- if (crtc > 0)
- vbl.request.type |= DRM_VBLANK_SECONDARY;
+ vbl.request.type |= populate_vbl_request_type(info, crtc);
vbl.request.sequence = target_msc;
vbl.request.signal = (unsigned long)wait_info;
ret = drmWaitVBlank(info->dri2.drm_fd, &vbl);
@@ -903,8 +916,7 @@ static int radeon_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw,
* so we queue an event that will satisfy the divisor/remainder equation.
*/
vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
- if (crtc > 0)
- vbl.request.type |= DRM_VBLANK_SECONDARY;
+ vbl.request.type |= populate_vbl_request_type(info, crtc);
vbl.request.sequence = current_msc - (current_msc % divisor) +
remainder;
@@ -1068,8 +1080,7 @@ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw,
/* Get current count */
vbl.request.type = DRM_VBLANK_RELATIVE;
- if (crtc > 0)
- vbl.request.type |= DRM_VBLANK_SECONDARY;
+ vbl.request.type |= populate_vbl_request_type(info, crtc);
vbl.request.sequence = 0;
ret = drmWaitVBlank(info->dri2.drm_fd, &vbl);
if (ret) {
@@ -1111,8 +1122,7 @@ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw,
*/
if (flip == 0)
vbl.request.type |= DRM_VBLANK_NEXTONMISS;
- if (crtc > 0)
- vbl.request.type |= DRM_VBLANK_SECONDARY;
+ vbl.request.type |= populate_vbl_request_type(info, crtc);
/* If target_msc already reached or passed, set it to
* current_msc to ensure we return a reasonable value back
@@ -1145,8 +1155,7 @@ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw,
vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
if (flip == 0)
vbl.request.type |= DRM_VBLANK_NEXTONMISS;
- if (crtc > 0)
- vbl.request.type |= DRM_VBLANK_SECONDARY;
+ vbl.request.type |= populate_vbl_request_type(info, crtc);
vbl.request.sequence = current_msc - (current_msc % divisor) +
remainder;
@@ -1217,6 +1226,7 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
DRI2InfoRec dri2_info = { 0 };
#ifdef USE_DRI2_SCHEDULING
const char *driverNames[1];
+ uint64_t cap_value;
#endif
if (!info->useEXA) {
@@ -1248,6 +1258,7 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
#endif
dri2_info.CopyRegion = radeon_dri2_copy_region;
+ info->high_crtc_works = FALSE;
#ifdef USE_DRI2_SCHEDULING
if (info->dri->pKernelDRMVersion->version_minor >= 4) {
dri2_info.version = 4;
@@ -1261,6 +1272,20 @@ radeon_dri2_screen_init(ScreenPtr pScreen)
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for sync extension\n");
}
+ if (info->drmmode.mode_res->count_crtcs > 2) {
+ if (drmGetCap(info->dri2.drm_fd, DRM_CAP_VBLANK_HIGH_CRTC, &cap_value)) {
+ info->high_crtc_works = FALSE;
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for VBLANKs on CRTC > 1\n");
+ } else {
+ if (cap_value) {
+ info->high_crtc_works = TRUE;
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Your kernel does not handle VBLANKs on CRTC > 1\n");
+ info->high_crtc_works = FALSE;
+ }
+ }
+ }
+
if (pRADEONEnt->dri2_info_cnt == 0) {
#if HAS_DIXREGISTERPRIVATEKEY
if (!dixRegisterPrivateKey(DRI2ClientEventsPrivateKey, PRIVATE_CLIENT, sizeof(DRI2ClientEventsRec))) {
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