xf86-video-intel: src/intel_driver.h src/intel_module.c

[Zhenyu Wang]

 src/intel_driver.h |   27 ++++++++++++++++++---------
 src/intel_module.c |   33 ++++++++++++++++++++++++++++++---
 2 files changed, 48 insertions(+), 12 deletions(-)

New commits:
commit 53767cc0d0a58d36cd445da3a31c65b349eebbba
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date:   Tue Sep 7 14:17:05 2010 +0800

    Add more sandybridge graphics device ids
    
    New ids for GT2 and GT2+ on desktop and mobile sandybridge, and
    server sandybridge device ids.

diff --git a/src/intel_driver.h b/src/intel_driver.h
index 00e8488..50f176a 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -168,12 +168,17 @@
 #define PCI_CHIP_IGDNG_M_G_BRIDGE	0x0044
 #endif
 
-#ifndef PCI_CHIP_SANDYBRIDGE
-#define PCI_CHIP_SANDYBRIDGE		0x0102
-#define PCI_CHIP_SANDYBRIDGE_BRIDGE	0x0100
-#define PCI_CHIP_SANDYBRIDGE_M		0x0106
-#define PCI_CHIP_SANDYBRIDGE_M_D0	0x0126
-#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M	0x0104
+#ifndef PCI_CHIP_SANDYBRIDGE_BRIDGE
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE	0x0100	/* Desktop */
+#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102
+#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
+#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M	0x0104	/* Mobile */
+#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106
+#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
+#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE_S	0x0108	/* Server */
+#define PCI_CHIP_SANDYBRIDGE_S_GT	0x010A
 #endif
 
 #define I85X_CAPID			0x44
@@ -242,9 +247,13 @@
 
 #define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
 
-#define IS_GEN6(pI810) ((pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE || \
-			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M ||\
-			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_D0)
+#define IS_GEN6(pI810) ((pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_GT1 || \
+			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_GT2 || \
+			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
+			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_GT1 ||\
+			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS ||\
+			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_S_GT)
 
 #define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810))
 /* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
diff --git a/src/intel_module.c b/src/intel_module.c
index 55e19d1..d37896e 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -72,6 +72,13 @@ static const SymTabRec _intel_chipsets[] = {
     {PCI_CHIP_B43_G,		"B43"},
     {PCI_CHIP_IGDNG_D_G,		"Clarkdale"},
     {PCI_CHIP_IGDNG_M_G,		"Arrandale"},
+    {PCI_CHIP_SANDYBRIDGE_GT1,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_GT2,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_GT2_PLUS,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_M_GT1,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_M_GT2,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_S_GT,	"Sandybridge" },
     {-1,				NULL}
 };
 SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
@@ -114,9 +121,13 @@ static const struct pci_id_match intel_device_match[] = {
     INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ),
     INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_D_G, 0 ),
     INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_M_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_D0, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, 0 ),
     { 0, 0, 0 },
 };
 
@@ -155,6 +166,13 @@ static PciChipsets intel_pci_chipsets[] = {
     {PCI_CHIP_B43_G,		PCI_CHIP_B43_G,		NULL},
     {PCI_CHIP_IGDNG_D_G,		PCI_CHIP_IGDNG_D_G,	NULL},
     {PCI_CHIP_IGDNG_M_G,		PCI_CHIP_IGDNG_M_G,	NULL},
+    {PCI_CHIP_SANDYBRIDGE_GT1,	PCI_CHIP_SANDYBRIDGE_GT1,	NULL},
+    {PCI_CHIP_SANDYBRIDGE_GT2,	PCI_CHIP_SANDYBRIDGE_GT2,	NULL},
+    {PCI_CHIP_SANDYBRIDGE_GT2_PLUS,	PCI_CHIP_SANDYBRIDGE_GT2_PLUS,	NULL},
+    {PCI_CHIP_SANDYBRIDGE_M_GT1,	PCI_CHIP_SANDYBRIDGE_M_GT1,	NULL},
+    {PCI_CHIP_SANDYBRIDGE_M_GT2,	PCI_CHIP_SANDYBRIDGE_M_GT2,	NULL},
+    {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS,	PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, NULL},
+    {PCI_CHIP_SANDYBRIDGE_S_GT,		PCI_CHIP_SANDYBRIDGE_S_GT,	NULL},
     {-1,				-1, NULL }
 };
 
@@ -290,6 +308,15 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
     case PCI_CHIP_IGDNG_M_G:
 	chipset->name = "Arrandale";
 	break;
+    case PCI_CHIP_SANDYBRIDGE_GT1:
+    case PCI_CHIP_SANDYBRIDGE_GT2:
+    case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
+    case PCI_CHIP_SANDYBRIDGE_M_GT1:
+    case PCI_CHIP_SANDYBRIDGE_M_GT2:
+    case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
+    case PCI_CHIP_SANDYBRIDGE_S_GT:
+	chipset->name = "Sandybridge";
+	break;
     default:
 	chipset->name = "unknown chipset";
 	break;