xf86-video-ati: Branch 'master' - 4 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Nov 22 15:07:08 PST 2010
src/ati_pciids_gen.h | 4 +++
src/atombios_output.c | 20 +++++++++++++++--
src/evergreen_accel.c | 27 ++++++++++++++++++++++-
src/evergreen_exa.c | 4 +++
src/pcidb/ati_pciids.csv | 4 +++
src/radeon.h | 3 ++
src/radeon_chipinfo_gen.h | 4 +++
src/radeon_chipset_gen.h | 4 +++
src/radeon_crtc.c | 2 -
src/radeon_driver.c | 43 +++++++++++++++++++++++---------------
src/radeon_pci_chipset_gen.h | 4 +++
src/radeon_pci_device_match_gen.h | 4 +++
12 files changed, 101 insertions(+), 22 deletions(-)
New commits:
commit 718dfd443897d70d97fc19afddfbcfe1e39a9c59
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Nov 22 13:11:50 2010 -0500
Ontario: add workaround for small pixmap issues with DFS
On past asics these kind a problems were usually due to a bad
backend map config. I suspect in this case, and the previous
cases it may be related to using linear buffers rather than
tiled.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 72e3a5d..1c02752 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -1671,6 +1671,10 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM)
goto copy;
+ if ((info->ChipFamily == CHIP_FAMILY_PALM) &&
+ ((w < 128) || (h < 128)))
+ goto copy;
+
size = scratch_pitch * h;
scratch = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_GTT, 0);
if (scratch == NULL) {
commit 61c97b0812c820564c7bc9d64a998c109bcd46b3
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Nov 22 13:10:16 2010 -0500
Add EXA/Xv acceleration support for Ontario Fusion APUs
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index 92d7fa1..f3691d7 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -69,7 +69,8 @@ evergreen_sq_setup(ScrnInfoPtr pScrn, sq_config_t *sq_conf)
uint32_t sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
RADEONInfoPtr info = RADEONPTR(pScrn);
- if (info->ChipFamily == CHIP_FAMILY_CEDAR)
+ if ((info->ChipFamily == CHIP_FAMILY_CEDAR) ||
+ (info->ChipFamily == CHIP_FAMILY_PALM))
sq_config = 0;
else
sq_config = VC_ENABLE_bit;
@@ -497,7 +498,8 @@ evergreen_set_vtx_resource(ScrnInfoPtr pScrn, vtx_resource_t *res, uint32_t doma
sq_vtx_constant_word4 = 0;
/* flush vertex cache */
- if (info->ChipFamily == CHIP_FAMILY_CEDAR)
+ if ((info->ChipFamily == CHIP_FAMILY_CEDAR) ||
+ (info->ChipFamily == CHIP_FAMILY_PALM))
evergreen_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit,
accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr,
res->bo,
@@ -834,6 +836,27 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
sq_conf.num_hs_stack_entries = 85;
sq_conf.num_ls_stack_entries = 85;
break;
+ case CHIP_FAMILY_PALM:
+ sq_conf.num_ps_gprs = 93;
+ sq_conf.num_vs_gprs = 46;
+ sq_conf.num_temp_gprs = 4;
+ sq_conf.num_gs_gprs = 31;
+ sq_conf.num_es_gprs = 31;
+ sq_conf.num_hs_gprs = 23;
+ sq_conf.num_ls_gprs = 23;
+ sq_conf.num_ps_threads = 96;
+ sq_conf.num_vs_threads = 16;
+ sq_conf.num_gs_threads = 16;
+ sq_conf.num_es_threads = 16;
+ sq_conf.num_hs_threads = 16;
+ sq_conf.num_ls_threads = 16;
+ sq_conf.num_ps_stack_entries = 42;
+ sq_conf.num_vs_stack_entries = 42;
+ sq_conf.num_gs_stack_entries = 42;
+ sq_conf.num_es_stack_entries = 42;
+ sq_conf.num_hs_stack_entries = 42;
+ sq_conf.num_ls_stack_entries = 42;
+ break;
}
evergreen_sq_setup(pScrn, &sq_conf);
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 7646060..0cd419f 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -263,7 +263,6 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
}
if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
- (info->ChipFamily >= CHIP_FAMILY_PALM) ||
(!RADEONIsAccelWorking(pScrn))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"GPU accel disabled or not working, using shadowfb for KMS\n");
commit 0659f35dfbeda7dd3ff58da1deb6484fabadc332
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Nov 22 13:07:00 2010 -0500
Add Ontario fusion APU pci ids
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 4784d88..80c60a8 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -458,6 +458,10 @@
#define PCI_CHIP_RS880_9713 0x9713
#define PCI_CHIP_RS880_9714 0x9714
#define PCI_CHIP_RS880_9715 0x9715
+#define PCI_CHIP_PALM_9802 0x9802
+#define PCI_CHIP_PALM_9803 0x9803
+#define PCI_CHIP_PALM_9804 0x9804
+#define PCI_CHIP_PALM_9805 0x9805
#define PCI_CHIP_CYPRESS_6880 0x6880
#define PCI_CHIP_CYPRESS_6888 0x6888
#define PCI_CHIP_CYPRESS_6889 0x6889
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 05028fe..060063b 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -459,6 +459,10 @@
"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon 4100"
"0x9714","RS880_9714","RS880",,1,,,1,"ATI Radeon HD 4290"
"0x9715","RS880_9715","RS880",,1,,,1,"ATI Radeon HD 4290"
+"0x9802","PALM_9802","PALM",,1,,,1,"AMD Radeon HD 6310 Graphics"
+"0x9803","PALM_9803","PALM",,1,,,1,"AMD Radeon HD 6310 Graphics"
+"0x9804","PALM_9804","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics"
+"0x9805","PALM_9805","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics"
"0x6880","CYPRESS_6880","CYPRESS",1,,,,,"CYPRESS"
"0x6888","CYPRESS_6888","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
"0x6889","CYPRESS_6889","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index 239c017..42e0d5d 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -378,6 +378,10 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9713, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
{ 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
{ 0x9715, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
+ { 0x9802, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
+ { 0x9803, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
+ { 0x9804, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
+ { 0x9805, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x6880, CHIP_FAMILY_CYPRESS, 1, 0, 0, 0, 0 },
{ 0x6888, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
{ 0x6889, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 1ea8b36..7b7f795 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -378,6 +378,10 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RS880_9713, "ATI Mobility Radeon 4100" },
{ PCI_CHIP_RS880_9714, "ATI Radeon HD 4290" },
{ PCI_CHIP_RS880_9715, "ATI Radeon HD 4290" },
+ { PCI_CHIP_PALM_9802, "AMD Radeon HD 6310 Graphics" },
+ { PCI_CHIP_PALM_9803, "AMD Radeon HD 6310 Graphics" },
+ { PCI_CHIP_PALM_9804, "AMD Radeon HD 6250 Graphics" },
+ { PCI_CHIP_PALM_9805, "AMD Radeon HD 6250 Graphics" },
{ PCI_CHIP_CYPRESS_6880, "CYPRESS" },
{ PCI_CHIP_CYPRESS_6888, "ATI FirePro (FireGL) Graphics Adapter" },
{ PCI_CHIP_CYPRESS_6889, "ATI FirePro (FireGL) Graphics Adapter" },
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index fe9919d..6e6582c 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -378,6 +378,10 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RS880_9713, PCI_CHIP_RS880_9713, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9714, PCI_CHIP_RS880_9714, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9715, PCI_CHIP_RS880_9715, RES_SHARED_VGA },
+ { PCI_CHIP_PALM_9802, PCI_CHIP_PALM_9802, RES_SHARED_VGA },
+ { PCI_CHIP_PALM_9803, PCI_CHIP_PALM_9803, RES_SHARED_VGA },
+ { PCI_CHIP_PALM_9804, PCI_CHIP_PALM_9804, RES_SHARED_VGA },
+ { PCI_CHIP_PALM_9805, PCI_CHIP_PALM_9805, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6880, PCI_CHIP_CYPRESS_6880, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6888, PCI_CHIP_CYPRESS_6888, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6889, PCI_CHIP_CYPRESS_6889, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 14e516f..fe8604a 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -378,6 +378,10 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9713, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9715, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_PALM_9802, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_PALM_9803, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_PALM_9804, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_PALM_9805, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6880, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6888, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6889, 0 ),
commit fa0cec331e6c94cebf82270dcd6c179b15851c5e
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Nov 22 12:56:45 2010 -0500
ontario: add UMS modesetting support
Accel not enabled yet.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 6bcc293..006905b 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -731,9 +731,17 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
else
disp_data.v3.ucLaneNum = 4;
- if (radeon_output->linkb) {
- disp_data.v3.acConfig.ucLinkSel = 1;
- disp_data.v2.acConfig.ucEncoderSel = 1;
+ if (IS_DCE41_VARIANT) {
+ if (radeon_output->dig_encoder)
+ disp_data.v3.acConfig.ucEncoderSel = 1;
+
+ if (radeon_output->linkb)
+ disp_data.v3.acConfig.ucLinkSel = 1;
+ } else {
+ if (radeon_output->linkb) {
+ disp_data.v3.acConfig.ucLinkSel = 1;
+ disp_data.v2.acConfig.ucEncoderSel = 1;
+ }
}
// select the PLL for the UNIPHY
@@ -1630,6 +1638,12 @@ atombios_pick_dig_encoder(xf86OutputPtr output)
mode == ATOM_ENCODER_MODE_CV)
return;
+ if (IS_DCE41_VARIANT) {
+ RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
+ radeon_output->dig_encoder = radeon_crtc->crtc_id;
+ return;
+ }
+
if (IS_DCE4_VARIANT) {
radeon_encoder = radeon_get_encoder(output);
diff --git a/src/radeon.h b/src/radeon.h
index 21c6d1c..84d3563 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -358,6 +358,7 @@ typedef enum {
CHIP_FAMILY_JUNIPER,
CHIP_FAMILY_CYPRESS,
CHIP_FAMILY_HEMLOCK,
+ CHIP_FAMILY_PALM,
CHIP_FAMILY_LAST
} RADEONChipFamily;
@@ -387,6 +388,8 @@ typedef enum {
#define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR))
+#define IS_DCE41_VARIANT ((info->ChipFamily >= CHIP_FAMILY_PALM))
+
#define IS_EVERGREEN_3D (info->ChipFamily >= CHIP_FAMILY_CEDAR)
#define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600)
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 5f4a0a7..550bd39 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -885,7 +885,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
}
/* 6 crtcs on DCE4 chips */
- if (IS_DCE4_VARIANT && ((mask & 3) == 3)) {
+ if (IS_DCE4_VARIANT && ((mask & 3) == 3) && !IS_DCE41_VARIANT) {
for (i = 2; i < RADEON_MAX_CRTC; i++) {
pRADEONEnt->pCrtc[i] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
if (!pRADEONEnt->pCrtc[i])
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 2e7046f..3900b09 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1424,7 +1424,12 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
/* We shouldn't use info->videoRam here which might have been clipped
* but the real video RAM instead
*/
- if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
+ if (info->ChipFamily >= CHIP_FAMILY_PALM) {
+ /* size in bytes on fusion */
+ mem_size = INREG(R600_CONFIG_MEMSIZE);
+ /* size in MB on fusion */
+ aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024;
+ } else if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
/* size in MB on evergreen */
/* XXX watch for overflow!!! */
mem_size = INREG(R600_CONFIG_MEMSIZE) * 1024 * 1024;
@@ -1469,7 +1474,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
(info->ChipFamily != CHIP_FAMILY_RS690) &&
(info->ChipFamily != CHIP_FAMILY_RS740) &&
(info->ChipFamily != CHIP_FAMILY_RS780) &&
- (info->ChipFamily != CHIP_FAMILY_RS880)) {
+ (info->ChipFamily != CHIP_FAMILY_RS880) &&
+ (info->ChipFamily != CHIP_FAMILY_PALM)) {
if (info->IsIGP)
info->mc_fb_location = INREG(RADEON_NB_TOM);
else
@@ -1650,7 +1656,7 @@ static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
unsigned char byte;
if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
- /* size in MB */
+ /* size in MB on evergreen and fusion */
aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024;
else if (info->ChipFamily >= CHIP_FAMILY_R600)
aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
@@ -1735,7 +1741,10 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024);
} else {
- if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
+ if (info->ChipFamily >= CHIP_FAMILY_PALM)
+ /* R600_CONFIG_MEMSIZE is bytes on fusion */
+ pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
+ else if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
/* R600_CONFIG_MEMSIZE is MB on evergreen */
/* XXX watch for overflow!!! */
pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) * 1024;
@@ -3949,21 +3958,23 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
- tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
- OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
- tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
+ if (!IS_DCE41_VARIANT) {
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
- tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
- OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
- tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
- tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
- OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
- tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
- tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
- OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
- tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+ }
usleep(10000);
timeout = 0;
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 0cd419f..7646060 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -263,6 +263,7 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
}
if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
+ (info->ChipFamily >= CHIP_FAMILY_PALM) ||
(!RADEONIsAccelWorking(pScrn))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"GPU accel disabled or not working, using shadowfb for KMS\n");
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