xf86-video-ati: Branch 'master' - 2 commits
Dave Airlie
airlied at kemper.freedesktop.org
Thu Nov 11 00:50:02 PST 2010
src/radeon_driver.c | 540 ++++++++++++++++++++++++++++++++++------------------
src/radeon_probe.h | 18 +
2 files changed, 368 insertions(+), 190 deletions(-)
New commits:
commit abbf73ee990512ac16ca77e8bb23288495e1f9f4
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Nov 11 09:38:15 2010 +1000
evergreen: add UMS VT switch support.
This isn't perfect, but it brings back text VTs here on the
DAC and DVI outputs.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 049c57a..ae2f525 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4484,6 +4484,147 @@ static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore)
}
static void
+evergreen_save_grph(ScrnInfoPtr pScrn, RADEONSavePtr save, int index)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ struct avivo_state *state = &save->avivo;
+ uint32_t grph_offset[] = {0x0, 0xc00, 0x9800, 0xa400, 0xb000, 0xbc00};
+
+ state->grph[index].enable = INREG(grph_offset[index] + EVERGREEN_GRPH_ENABLE);
+ state->grph[index].control = INREG(grph_offset[index] + EVERGREEN_GRPH_CONTROL);
+ state->grph[index].swap_control = INREG(grph_offset[index] + EVERGREEN_GRPH_SWAP_CONTROL);
+ state->grph[index].prim_surf_addr = INREG(grph_offset[index] + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS);
+ state->grph[index].sec_surf_addr = INREG(grph_offset[index] + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS);
+ state->grph[index].pitch = INREG(grph_offset[index] + EVERGREEN_GRPH_PITCH);
+ state->grph[index].prim_surf_addr_hi = INREG(grph_offset[index] + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH);
+ state->grph[index].sec_surf_addr_hi = INREG(grph_offset[index] + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH);
+ state->grph[index].x_offset = INREG(grph_offset[index] + EVERGREEN_GRPH_SURFACE_OFFSET_X);
+ state->grph[index].y_offset = INREG(grph_offset[index] + EVERGREEN_GRPH_SURFACE_OFFSET_Y);
+ state->grph[index].x_start = INREG(grph_offset[index] + EVERGREEN_GRPH_X_START);
+ state->grph[index].y_start = INREG(grph_offset[index] + EVERGREEN_GRPH_Y_START);
+ state->grph[index].x_end = INREG(grph_offset[index] + EVERGREEN_GRPH_X_END);
+ state->grph[index].y_end = INREG(grph_offset[index] + EVERGREEN_GRPH_Y_END);
+
+ state->grph[index].desktop_height = INREG(grph_offset[index] + EVERGREEN_DESKTOP_HEIGHT);
+ state->grph[index].viewport_start = INREG(grph_offset[index] + EVERGREEN_VIEWPORT_START);
+ state->grph[index].viewport_size = INREG(grph_offset[index] + EVERGREEN_VIEWPORT_SIZE);
+ state->grph[index].mode_data_format = INREG(grph_offset[index] + EVERGREEN_DATA_FORMAT);
+}
+
+static void
+evergreen_restore_grph(ScrnInfoPtr pScrn, RADEONSavePtr restore, int index)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ struct avivo_state *state = &restore->avivo;
+ uint32_t grph_offset[] = {0x0, 0xc00, 0x9800, 0xa400, 0xb000, 0xbc00};
+
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_ENABLE, state->grph[index].enable);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_CONTROL, state->grph[index].control);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_SWAP_CONTROL, state->grph[index].swap_control);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS, state->grph[index].prim_surf_addr);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS, state->grph[index].sec_surf_addr);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_PITCH, state->grph[index].pitch);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, state->grph[index].prim_surf_addr_hi);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, state->grph[index].sec_surf_addr_hi);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_SURFACE_OFFSET_X, state->grph[index].x_offset);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_SURFACE_OFFSET_Y, state->grph[index].y_offset);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_X_START, state->grph[index].x_start);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_Y_START, state->grph[index].y_start);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_X_END, state->grph[index].x_end);
+ OUTREG(grph_offset[index] + EVERGREEN_GRPH_Y_END, state->grph[index].y_end);
+
+ OUTREG(grph_offset[index] + EVERGREEN_DESKTOP_HEIGHT, state->grph[index].desktop_height);
+ OUTREG(grph_offset[index] + EVERGREEN_VIEWPORT_START, state->grph[index].viewport_start);
+ OUTREG(grph_offset[index] + EVERGREEN_VIEWPORT_SIZE, state->grph[index].viewport_size);
+ OUTREG(grph_offset[index] + EVERGREEN_DATA_FORMAT, state->grph[index].mode_data_format);
+}
+
+static uint32_t evergreen_dac_regs[] = {
+ 0x6690, 0x6694, 0x66b0, 0x66cc, 0x66d0, 0x66d4, 0x66d8 };
+
+static uint32_t evergreen_scl1_regs[] = {
+ 0x6d08, 0x6d0c, 0x6d14, 0x6d1c };
+
+static uint32_t evergreen_crtc_regs[] = {
+ 0x6e00, 0x6e04, 0x6e08, 0x6e0c, 0x6e1c, 0x6e34, 0x6e38, 0x6e3c, 0x6e70, 0x6e74, 0x6e78};
+
+#define EG_REG_SCL1_NUM (sizeof(evergreen_scl1_regs)/sizeof(uint32_t))
+#define EG_REG_CRTC_NUM (sizeof(evergreen_crtc_regs)/sizeof(uint32_t))
+#define EG_DAC_NUM (sizeof(evergreen_dac_regs)/sizeof(uint32_t))
+
+
+static void
+evergreen_save_crtc(ScrnInfoPtr pScrn, RADEONSavePtr save, int index)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ struct avivo_state *state = &save->avivo;
+ int i;
+
+ uint32_t crtc_offset[] = {EVERGREEN_CRTC0_REGISTER_OFFSET,
+ EVERGREEN_CRTC1_REGISTER_OFFSET,
+ EVERGREEN_CRTC2_REGISTER_OFFSET,
+ EVERGREEN_CRTC3_REGISTER_OFFSET,
+ EVERGREEN_CRTC4_REGISTER_OFFSET,
+ EVERGREEN_CRTC5_REGISTER_OFFSET};
+
+ for (i = 0; i < EG_REG_CRTC_NUM; i++) {
+ state->eg_crtc[index][i] = INREG(crtc_offset[index] + evergreen_crtc_regs[i]);
+ }
+}
+
+static void
+evergreen_restore_crtc(ScrnInfoPtr pScrn, RADEONSavePtr restore, int index)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ struct avivo_state *state = &restore->avivo;
+ int i;
+ uint32_t crtc_offset[] = {EVERGREEN_CRTC0_REGISTER_OFFSET,
+ EVERGREEN_CRTC1_REGISTER_OFFSET,
+ EVERGREEN_CRTC2_REGISTER_OFFSET,
+ EVERGREEN_CRTC3_REGISTER_OFFSET,
+ EVERGREEN_CRTC4_REGISTER_OFFSET,
+ EVERGREEN_CRTC5_REGISTER_OFFSET};
+
+ for (i = 0; i < EG_REG_CRTC_NUM; i++) {
+ OUTREG(crtc_offset[index] + evergreen_crtc_regs[i], state->eg_crtc[index][i]);
+ }
+}
+
+static void
+evergreen_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ struct avivo_state *state = &save->avivo;
+ int i, j;
+
+ state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL);
+ state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL);
+ state->vga3_cntl = INREG(EVERGREEN_D3VGA_CONTROL);
+ state->vga4_cntl = INREG(EVERGREEN_D4VGA_CONTROL);
+ state->vga5_cntl = INREG(EVERGREEN_D5VGA_CONTROL);
+ state->vga6_cntl = INREG(EVERGREEN_D6VGA_CONTROL);
+ state->vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL);
+
+ for (i = 0; i < 6; i++)
+ evergreen_save_grph(pScrn, save, i);
+
+ for (i = 0; i < 6; i++)
+ evergreen_save_crtc(pScrn, save, i);
+
+ for (i = 0; i < EG_DAC_NUM; i++)
+ state->daca[i] = INREG(evergreen_dac_regs[i]);
+
+ for (i = 0; i < EG_REG_SCL1_NUM; i++)
+ state->d1scl[i] = INREG(evergreen_scl1_regs[i]);
+
+}
+
+static void
avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -4842,6 +4983,35 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
static void
+evergreen_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ struct avivo_state *state = &restore->avivo;
+ int i, j;
+
+ OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
+ OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);;
+ OUTREG(EVERGREEN_D3VGA_CONTROL, state->vga3_cntl);
+ OUTREG(EVERGREEN_D4VGA_CONTROL, state->vga4_cntl);
+ OUTREG(EVERGREEN_D5VGA_CONTROL, state->vga5_cntl);
+ OUTREG(EVERGREEN_D6VGA_CONTROL, state->vga6_cntl);
+ OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control);
+
+ for (i = 0; i < 6; i++)
+ evergreen_restore_grph(pScrn, restore, i);
+
+ for (i = 0; i < 6; i++)
+ evergreen_restore_crtc(pScrn, restore, i);
+
+ for (i = 0; i < EG_DAC_NUM; i++)
+ OUTREG(evergreen_dac_regs[i], state->daca[i]);
+
+ for (i = 0; i < EG_REG_SCL1_NUM; i++)
+ OUTREG(evergreen_scl1_regs[i], state->d1scl[i]);
+}
+
+static void
avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -5338,6 +5508,7 @@ static void RADEONSave(ScrnInfoPtr pScrn)
if (IS_DCE4_VARIANT) {
RADEONSaveMemMapRegisters(pScrn, save);
+ evergreen_save(pScrn, save);
//XXX
} else if (IS_AVIVO_VARIANT) {
RADEONSaveMemMapRegisters(pScrn, save);
@@ -5393,6 +5564,7 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
if (IS_DCE4_VARIANT) {
RADEONRestoreMemMapRegisters(pScrn, restore);
+ evergreen_restore(pScrn, restore);
//XXX
} else if (IS_AVIVO_VARIANT) {
RADEONRestoreMemMapRegisters(pScrn, restore);
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 78179ed..2b78a1f 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -344,9 +344,12 @@ struct avivo_crtc_state {
struct avivo_grph_state {
uint32_t enable;
uint32_t control;
+ uint32_t swap_control;
uint32_t prim_surf_addr;
uint32_t sec_surf_addr;
uint32_t pitch;
+ uint32_t prim_surf_addr_hi;
+ uint32_t sec_surf_addr_hi;
uint32_t x_offset;
uint32_t y_offset;
uint32_t x_start;
@@ -385,9 +388,11 @@ struct avivo_state
struct avivo_pll_state vga28_ppll;
struct avivo_pll_state vga41_ppll;
- struct avivo_crtc_state crtc[6];
+ struct avivo_crtc_state crtc[2];
- struct avivo_grph_state grph[2];
+ uint32_t eg_crtc[6][15];
+
+ struct avivo_grph_state grph[6];
/* DDIA block on RS6xx chips */
uint32_t ddia[37];
commit e1dfaf93d06bc5eafdbc2e1823d19204ce8f242c
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Nov 11 09:15:27 2010 +1000
avivo: use arrays to store the crtc/pll info for save/restore
this is just prep work for evergreen VT save/restore
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 428ea22..049c57a 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4501,23 +4501,23 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL);
state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT);
- state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
- state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV);
- state->pll1.fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV);
- state->pll1.post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC);
- state->pll1.post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV);
- state->pll1.ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL);
- state->pll1.pll_cntl = INREG(AVIVO_P1PLL_CNTL);
- state->pll1.int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL);
-
- state->pll2.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
- state->pll2.ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV);
- state->pll2.fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV);
- state->pll2.post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC);
- state->pll2.post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV);
- state->pll2.ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL);
- state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL);
- state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ state->pll[0].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
+ state->pll[0].ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV);
+ state->pll[0].fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV);
+ state->pll[0].post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC);
+ state->pll[0].post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV);
+ state->pll[0].ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL);
+ state->pll[0].pll_cntl = INREG(AVIVO_P1PLL_CNTL);
+ state->pll[0].int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+
+ state->pll[1].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
+ state->pll[1].ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV);
+ state->pll[1].fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV);
+ state->pll[1].post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC);
+ state->pll[1].post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV);
+ state->pll[1].ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL);
+ state->pll[1].pll_cntl = INREG(AVIVO_P2PLL_CNTL);
+ state->pll[1].int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL);
state->vga25_ppll.ref_div_src = INREG(AVIVO_VGA25_PPLL_REF_DIV_SRC);
state->vga25_ppll.ref_div = INREG(AVIVO_VGA25_PPLL_REF_DIV);
@@ -4540,87 +4540,87 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->vga41_ppll.post_div = INREG(AVIVO_VGA41_PPLL_POST_DIV);
state->vga41_ppll.pll_cntl = INREG(AVIVO_VGA41_PPLL_CNTL);
- state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL);
-
- state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL);
- state->crtc1.h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END);
- state->crtc1.h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A);
- state->crtc1.h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL);
- state->crtc1.h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B);
- state->crtc1.h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL);
-
- state->crtc1.v_total = INREG(AVIVO_D1CRTC_V_TOTAL);
- state->crtc1.v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END);
- state->crtc1.v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A);
- state->crtc1.v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL);
- state->crtc1.v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B);
- state->crtc1.v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL);
-
- state->crtc1.control = INREG(AVIVO_D1CRTC_CONTROL);
- state->crtc1.blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL);
- state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL);
- state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL);
-
- state->crtc1.cursor_control = INREG(AVIVO_D1CUR_CONTROL);
-
- state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE);
- state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL);
- state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL);
- state->grph1.prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS);
- state->grph1.sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS);
- state->grph1.pitch = INREG(AVIVO_D1GRPH_PITCH);
- state->grph1.x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X);
- state->grph1.y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y);
- state->grph1.x_start = INREG(AVIVO_D1GRPH_X_START);
- state->grph1.y_start = INREG(AVIVO_D1GRPH_Y_START);
- state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END);
- state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END);
-
- state->grph1.desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT);
- state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
- state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
- state->grph1.mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT);
-
- state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL);
-
- state->crtc2.h_total = INREG(AVIVO_D2CRTC_H_TOTAL);
- state->crtc2.h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END);
- state->crtc2.h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A);
- state->crtc2.h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL);
- state->crtc2.h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B);
- state->crtc2.h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL);
-
- state->crtc2.v_total = INREG(AVIVO_D2CRTC_V_TOTAL);
- state->crtc2.v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END);
- state->crtc2.v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A);
- state->crtc2.v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL);
- state->crtc2.v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B);
- state->crtc2.v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL);
-
- state->crtc2.control = INREG(AVIVO_D2CRTC_CONTROL);
- state->crtc2.blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL);
- state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL);
- state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL);
-
- state->crtc2.cursor_control = INREG(AVIVO_D2CUR_CONTROL);
-
- state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE);
- state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL);
- state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL);
- state->grph2.prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS);
- state->grph2.sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS);
- state->grph2.pitch = INREG(AVIVO_D2GRPH_PITCH);
- state->grph2.x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X);
- state->grph2.y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y);
- state->grph2.x_start = INREG(AVIVO_D2GRPH_X_START);
- state->grph2.y_start = INREG(AVIVO_D2GRPH_Y_START);
- state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END);
- state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END);
-
- state->grph2.desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT);
- state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
- state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
- state->grph2.mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT);
+ state->crtc[0].pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL);
+
+ state->crtc[0].h_total = INREG(AVIVO_D1CRTC_H_TOTAL);
+ state->crtc[0].h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END);
+ state->crtc[0].h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A);
+ state->crtc[0].h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL);
+ state->crtc[0].h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B);
+ state->crtc[0].h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL);
+
+ state->crtc[0].v_total = INREG(AVIVO_D1CRTC_V_TOTAL);
+ state->crtc[0].v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END);
+ state->crtc[0].v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A);
+ state->crtc[0].v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL);
+ state->crtc[0].v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B);
+ state->crtc[0].v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL);
+
+ state->crtc[0].control = INREG(AVIVO_D1CRTC_CONTROL);
+ state->crtc[0].blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL);
+ state->crtc[0].interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL);
+ state->crtc[0].stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL);
+
+ state->crtc[0].cursor_control = INREG(AVIVO_D1CUR_CONTROL);
+
+ state->grph[0].enable = INREG(AVIVO_D1GRPH_ENABLE);
+ state->grph[0].control = INREG(AVIVO_D1GRPH_CONTROL);
+ state->grph[0].control = INREG(AVIVO_D1GRPH_CONTROL);
+ state->grph[0].prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS);
+ state->grph[0].sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS);
+ state->grph[0].pitch = INREG(AVIVO_D1GRPH_PITCH);
+ state->grph[0].x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X);
+ state->grph[0].y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y);
+ state->grph[0].x_start = INREG(AVIVO_D1GRPH_X_START);
+ state->grph[0].y_start = INREG(AVIVO_D1GRPH_Y_START);
+ state->grph[0].x_end = INREG(AVIVO_D1GRPH_X_END);
+ state->grph[0].y_end = INREG(AVIVO_D1GRPH_Y_END);
+
+ state->grph[0].desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT);
+ state->grph[0].viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
+ state->grph[0].viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
+ state->grph[0].mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT);
+
+ state->crtc[1].pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL);
+
+ state->crtc[1].h_total = INREG(AVIVO_D2CRTC_H_TOTAL);
+ state->crtc[1].h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END);
+ state->crtc[1].h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A);
+ state->crtc[1].h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL);
+ state->crtc[1].h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B);
+ state->crtc[1].h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL);
+
+ state->crtc[1].v_total = INREG(AVIVO_D2CRTC_V_TOTAL);
+ state->crtc[1].v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END);
+ state->crtc[1].v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A);
+ state->crtc[1].v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL);
+ state->crtc[1].v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B);
+ state->crtc[1].v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL);
+
+ state->crtc[1].control = INREG(AVIVO_D2CRTC_CONTROL);
+ state->crtc[1].blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL);
+ state->crtc[1].interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL);
+ state->crtc[1].stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL);
+
+ state->crtc[1].cursor_control = INREG(AVIVO_D2CUR_CONTROL);
+
+ state->grph[1].enable = INREG(AVIVO_D2GRPH_ENABLE);
+ state->grph[1].control = INREG(AVIVO_D2GRPH_CONTROL);
+ state->grph[1].control = INREG(AVIVO_D2GRPH_CONTROL);
+ state->grph[1].prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS);
+ state->grph[1].sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS);
+ state->grph[1].pitch = INREG(AVIVO_D2GRPH_PITCH);
+ state->grph[1].x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X);
+ state->grph[1].y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y);
+ state->grph[1].x_start = INREG(AVIVO_D2GRPH_X_START);
+ state->grph[1].y_start = INREG(AVIVO_D2GRPH_Y_START);
+ state->grph[1].x_end = INREG(AVIVO_D2GRPH_X_END);
+ state->grph[1].y_end = INREG(AVIVO_D2GRPH_Y_END);
+
+ state->grph[1].desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT);
+ state->grph[1].viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
+ state->grph[1].viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
+ state->grph[1].mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT);
if (IS_DCE3_VARIANT) {
/* save DVOA regs */
@@ -4833,10 +4833,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->dxscl[6] = INREG(0x6e30);
state->dxscl[7] = INREG(0x6e34);
- if (state->crtc1.control & AVIVO_CRTC_EN)
+ if (state->crtc[0].control & AVIVO_CRTC_EN)
info->crtc_on = TRUE;
- if (state->crtc2.control & AVIVO_CRTC_EN)
+ if (state->crtc[1].control & AVIVO_CRTC_EN)
info->crtc2_on = TRUE;
}
@@ -4871,69 +4871,69 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
/* Lock graph registers */
OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK);
- OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr);
- OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr);
- OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control);
- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset);
- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset);
- OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start);
- OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start);
- OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end);
- OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end);
- OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch);
- OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable);
+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph[0].prim_surf_addr);
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph[0].sec_surf_addr);
+ OUTREG(AVIVO_D1GRPH_CONTROL, state->grph[0].control);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph[0].x_offset);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph[0].y_offset);
+ OUTREG(AVIVO_D1GRPH_X_START, state->grph[0].x_start);
+ OUTREG(AVIVO_D1GRPH_Y_START, state->grph[0].y_start);
+ OUTREG(AVIVO_D1GRPH_X_END, state->grph[0].x_end);
+ OUTREG(AVIVO_D1GRPH_Y_END, state->grph[0].y_end);
+ OUTREG(AVIVO_D1GRPH_PITCH, state->grph[0].pitch);
+ OUTREG(AVIVO_D1GRPH_ENABLE, state->grph[0].enable);
OUTREG(AVIVO_D1GRPH_UPDATE, 0);
OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK);
- OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr);
- OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr);
- OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control);
- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset);
- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset);
- OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start);
- OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start);
- OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end);
- OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end);
- OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch);
- OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable);
+ OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph[1].prim_surf_addr);
+ OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph[1].sec_surf_addr);
+ OUTREG(AVIVO_D2GRPH_CONTROL, state->grph[1].control);
+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph[1].x_offset);
+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph[1].y_offset);
+ OUTREG(AVIVO_D2GRPH_X_START, state->grph[1].x_start);
+ OUTREG(AVIVO_D2GRPH_Y_START, state->grph[1].y_start);
+ OUTREG(AVIVO_D2GRPH_X_END, state->grph[1].x_end);
+ OUTREG(AVIVO_D2GRPH_Y_END, state->grph[1].y_end);
+ OUTREG(AVIVO_D2GRPH_PITCH, state->grph[1].pitch);
+ OUTREG(AVIVO_D2GRPH_ENABLE, state->grph[1].enable);
OUTREG(AVIVO_D2GRPH_UPDATE, 0);
/* Whack some mode regs too */
OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK);
- OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph1.desktop_height);
- OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start);
- OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size);
- OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph1.mode_data_format);
+ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph[0].desktop_height);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph[0].viewport_start);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph[0].viewport_size);
+ OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph[0].mode_data_format);
OUTREG(AVIVO_D1SCL_UPDATE, 0);
OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK);
- OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph2.desktop_height);
- OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start);
- OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size);
- OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph2.mode_data_format);
+ OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph[1].desktop_height);
+ OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph[1].viewport_start);
+ OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph[1].viewport_size);
+ OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph[1].mode_data_format);
OUTREG(AVIVO_D2SCL_UPDATE, 0);
/* Set the PLL */
- OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src);
- OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div);
- OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div);
- OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll1.post_div_src);
- OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll1.post_div);
- OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll1.ext_ppll_cntl);
- OUTREG(AVIVO_P1PLL_CNTL, state->pll1.pll_cntl);
- OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll1.int_ss_cntl);
-
- OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll2.ref_div_src);
- OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll2.ref_div);
- OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll2.fb_div);
- OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll2.post_div_src);
- OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll2.post_div);
- OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll2.ext_ppll_cntl);
- OUTREG(AVIVO_P2PLL_CNTL, state->pll2.pll_cntl);
- OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl);
-
- OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source);
- OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source);
+ OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll[0].ref_div_src);
+ OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll[0].ref_div);
+ OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll[0].fb_div);
+ OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll[0].post_div_src);
+ OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll[0].post_div);
+ OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll[0].ext_ppll_cntl);
+ OUTREG(AVIVO_P1PLL_CNTL, state->pll[0].pll_cntl);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll[0].int_ss_cntl);
+
+ OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll[1].ref_div_src);
+ OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll[1].ref_div);
+ OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll[1].fb_div);
+ OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll[1].post_div_src);
+ OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll[1].post_div);
+ OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll[1].ext_ppll_cntl);
+ OUTREG(AVIVO_P2PLL_CNTL, state->pll[1].pll_cntl);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll[1].int_ss_cntl);
+
+ OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc[0].pll_source);
+ OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc[1].pll_source);
/* Set the vga PLL */
OUTREG(AVIVO_VGA25_PPLL_REF_DIV_SRC, state->vga25_ppll.ref_div_src);
@@ -4958,45 +4958,45 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_VGA41_PPLL_CNTL, state->vga41_ppll.pll_cntl);
/* Set the CRTC */
- OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total);
- OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end);
- OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a);
- OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc1.h_sync_a_cntl);
- OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc1.h_sync_b);
- OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc1.h_sync_b_cntl);
+ OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc[0].h_total);
+ OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc[0].h_blank_start_end);
+ OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc[0].h_sync_a);
+ OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc[0].h_sync_a_cntl);
+ OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc[0].h_sync_b);
+ OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc[0].h_sync_b_cntl);
- OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total);
- OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end);
- OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1.v_sync_a);
- OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl);
- OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b);
- OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl);
+ OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc[0].v_total);
+ OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc[0].v_blank_start_end);
+ OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc[0].v_sync_a);
+ OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc[0].v_sync_a_cntl);
+ OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc[0].v_sync_b);
+ OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc[0].v_sync_b_cntl);
- OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control);
- OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control);
+ OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc[0].interlace_control);
+ OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc[0].stereo_control);
- OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control);
+ OUTREG(AVIVO_D1CUR_CONTROL, state->crtc[0].cursor_control);
/* XXX Fix scaler */
- OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total);
- OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end);
- OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc2.h_sync_a);
- OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc2.h_sync_a_cntl);
- OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc2.h_sync_b);
- OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc2.h_sync_b_cntl);
+ OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc[1].h_total);
+ OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc[1].h_blank_start_end);
+ OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc[1].h_sync_a);
+ OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc[1].h_sync_a_cntl);
+ OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc[1].h_sync_b);
+ OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc[1].h_sync_b_cntl);
- OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total);
- OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end);
- OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2.v_sync_a);
- OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl);
- OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b);
- OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl);
+ OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc[1].v_total);
+ OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc[1].v_blank_start_end);
+ OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc[1].v_sync_a);
+ OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc[1].v_sync_a_cntl);
+ OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc[1].v_sync_b);
+ OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc[1].v_sync_b_cntl);
- OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control);
- OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control);
+ OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc[1].interlace_control);
+ OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc[1].stereo_control);
- OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control);
+ OUTREG(AVIVO_D2CUR_CONTROL, state->crtc[1].cursor_control);
if (IS_DCE3_VARIANT) {
/* DVOA regs */
@@ -5210,12 +5210,12 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(0x6e34, state->dxscl[7]);
/* Enable CRTCs */
- if (state->crtc1.control & 1) {
+ if (state->crtc[0].control & 1) {
OUTREG(AVIVO_D1CRTC_CONTROL, 0x01000101);
INREG(AVIVO_D1CRTC_CONTROL);
OUTREG(AVIVO_D1CRTC_CONTROL, 0x00010101);
}
- if (state->crtc2.control & 1) {
+ if (state->crtc[1].control & 1) {
OUTREG(AVIVO_D2CRTC_CONTROL, 0x01000101);
INREG(AVIVO_D2CRTC_CONTROL);
OUTREG(AVIVO_D2CRTC_CONTROL, 0x00010101);
@@ -5226,8 +5226,8 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, state->dc_lb_memory_split);
/* Need fixing too ? */
- OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control);
- OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control);
+ OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc[0].blank_control);
+ OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc[1].blank_control);
/* Dbl check */
OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control);
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index ce3b4e6..78179ed 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -369,24 +369,25 @@ struct avivo_state
uint32_t vga1_cntl;
uint32_t vga2_cntl;
+ uint32_t vga3_cntl;
+ uint32_t vga4_cntl;
+ uint32_t vga5_cntl;
+ uint32_t vga6_cntl;
uint32_t vga_render_control;
uint32_t crtc_master_en;
uint32_t crtc_tv_control;
uint32_t dc_lb_memory_split;
- struct avivo_pll_state pll1;
- struct avivo_pll_state pll2;
+ struct avivo_pll_state pll[2];
struct avivo_pll_state vga25_ppll;
struct avivo_pll_state vga28_ppll;
struct avivo_pll_state vga41_ppll;
- struct avivo_crtc_state crtc1;
- struct avivo_crtc_state crtc2;
+ struct avivo_crtc_state crtc[6];
- struct avivo_grph_state grph1;
- struct avivo_grph_state grph2;
+ struct avivo_grph_state grph[2];
/* DDIA block on RS6xx chips */
uint32_t ddia[37];
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