xf86-video-intel: 5 commits - src/i965_render.c src/render_program/exa_wm_ca.g6a src/render_program/exa_wm_ca.g6b src/render_program/exa_wm_ca_srcalpha.g6a src/render_program/exa_wm_ca_srcalpha.g6b src/render_program/exa_wm_mask_affine.g6a src/render_program/exa_wm_mask_affine.g6b src/render_program/exa_wm_mask_projective.g6a src/render_program/exa_wm_mask_projective.g6b src/render_program/exa_wm_mask_sample_a.g4a src/render_program/exa_wm_mask_sample_a.g4b src/render_program/exa_wm_mask_sample_a.g4b.gen5 src/render_program/exa_wm_mask_sample_a.g6a src/render_program/exa_wm_mask_sample_a.g6b src/render_program/exa_wm_mask_sample_argb.g4a src/render_program/exa_wm_mask_sample_argb.g4b src/render_program/exa_wm_mask_sample_argb.g4b.gen5 src/render_program/exa_wm_mask_sample_argb.g6a src/render_program/exa_wm_mask_sample_argb.g6b src/render_program/exa_wm_noca.g6a src/render_program/exa_wm_noca.g6b src/render_program/exa_wm_src_projective.g6a src/render_program/exa_wm_s rc_projective.g6b src/render_program/exa_wm_src_sample_a.g4a src/render_program/exa_wm_src_sample_a.g4b src/render_program/exa_wm_src_sample_a.g4b.gen5 src/render_program/exa_wm_src_sample_a.g6a src/render_program/exa_wm_src_sample_a.g6b src/render_program/exa_wm_write.g6a src/render_program/exa_wm_write.g6b src/render_program/Makefile.am
Haihao Xiang
haihao at kemper.freedesktop.org
Tue Nov 2 01:18:46 PDT 2010
src/i965_render.c | 761 ++++++++++++++++++--
src/render_program/Makefile.am | 18
src/render_program/exa_wm_ca.g6a | 1
src/render_program/exa_wm_ca.g6b | 4
src/render_program/exa_wm_ca_srcalpha.g6a | 1
src/render_program/exa_wm_ca_srcalpha.g6b | 4
src/render_program/exa_wm_mask_affine.g6a | 47 +
src/render_program/exa_wm_mask_affine.g6b | 4
src/render_program/exa_wm_mask_projective.g6a | 63 +
src/render_program/exa_wm_mask_projective.g6b | 12
src/render_program/exa_wm_mask_sample_a.g4a | 3
src/render_program/exa_wm_mask_sample_a.g4b | 3
src/render_program/exa_wm_mask_sample_a.g4b.gen5 | 3
src/render_program/exa_wm_mask_sample_a.g6a | 1
src/render_program/exa_wm_mask_sample_a.g6b | 3
src/render_program/exa_wm_mask_sample_argb.g4a | 3
src/render_program/exa_wm_mask_sample_argb.g4b | 3
src/render_program/exa_wm_mask_sample_argb.g4b.gen5 | 3
src/render_program/exa_wm_mask_sample_argb.g6a | 1
src/render_program/exa_wm_mask_sample_argb.g6b | 3
src/render_program/exa_wm_noca.g6a | 1
src/render_program/exa_wm_noca.g6b | 4
src/render_program/exa_wm_src_projective.g6a | 63 +
src/render_program/exa_wm_src_projective.g6b | 12
src/render_program/exa_wm_src_sample_a.g4a | 3
src/render_program/exa_wm_src_sample_a.g4b | 3
src/render_program/exa_wm_src_sample_a.g4b.gen5 | 3
src/render_program/exa_wm_src_sample_a.g6a | 1
src/render_program/exa_wm_src_sample_a.g6b | 3
src/render_program/exa_wm_write.g6a | 12
src/render_program/exa_wm_write.g6b | 4
31 files changed, 964 insertions(+), 86 deletions(-)
New commits:
commit 540c5742186c26c3aeccb7b5d3ff0f374722a20c
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Tue Nov 2 11:05:32 2010 +0800
render: use headerless render target write
It is weird that some rendercheck cases only work fine with headerless write.
Need to update intel-gen4asm to support headerless write
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/src/render_program/exa_wm_write.g6a b/src/render_program/exa_wm_write.g6a
index 27f91b5..c0f3cc1 100644
--- a/src/render_program/exa_wm_write.g6a
+++ b/src/render_program/exa_wm_write.g6a
@@ -36,6 +36,7 @@ define(`slot_b_00', `m6')
define(`slot_b_01', `m7')
define(`slot_a_00', `m8')
define(`slot_a_01', `m9')
+define(`data_port_msg_2_ind', `2')
mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 };
mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 };
@@ -49,22 +50,19 @@ mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 };
mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 };
mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 };
-/* pass payload in m0-m1 */
-mov (8) data_port_msg_0<1>UD g0<8,8,1>UD { align1 };
-mov (8) data_port_msg_1<1>UD g1<8,8,1>UD { align1 };
-
/* write */
send (16)
- data_port_msg_0_ind
+ data_port_msg_2_ind
acc0<1>UW
null
write (
0, /* binding_table */
16, /* pixel scordboard clear, msg type simd16 single source */
12, /* render target write */
- 0 /* no write commit message */
+ 0, /* no write commit message */
+ 0 /* headerless render target write */
)
- mlen 10
+ mlen 8
rlen 0
{ align1 EOT };
diff --git a/src/render_program/exa_wm_write.g6b b/src/render_program/exa_wm_write.g6b
index 9db2129..3cb6bff 100644
--- a/src/render_program/exa_wm_write.g6b
+++ b/src/render_program/exa_wm_write.g6b
@@ -6,9 +6,7 @@
{ 0x00600001, 0x20e003be, 0x008d0260, 0x00000000 },
{ 0x00600001, 0x210003be, 0x008d0280, 0x00000000 },
{ 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 },
- { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
- { 0x00600001, 0x20200022, 0x008d0020, 0x00000000 },
- { 0x05800031, 0x24001cc8, 0x00000000, 0x94099000 },
+ { 0x05800031, 0x24001cc8, 0x00000040, 0x90019000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
commit 7a3109312e43ce4c2f600a65fe6bc821a8f0ebde
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Wed Oct 27 16:51:28 2010 +0800
render: acceleration for composite on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/src/i965_render.c b/src/i965_render.c
index 885889e..e2b67c3 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -208,14 +208,8 @@ i965_check_composite(int op,
int width, int height)
{
ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum];
- intel_screen_private *intel = intel_get_screen_private(scrn);
uint32_t tmp1;
- if (IS_GEN6(intel)) {
- intel_debug_fallback(scrn, "Unsupported hardware\n");
- return FALSE;
- }
-
/* Check for unsupported compositing operations. */
if (op >= sizeof(i965_blend_op) / sizeof(i965_blend_op[0])) {
intel_debug_fallback(scrn,
@@ -522,6 +516,73 @@ static const uint32_t ps_kernel_masknoca_projective_static_gen5[][4] = {
#include "exa_wm_write.g4b.gen5"
};
+/* programs for GEN6 */
+static const uint32_t ps_kernel_nomask_affine_static_gen6[][4] = {
+#include "exa_wm_src_affine.g6b"
+#include "exa_wm_src_sample_argb.g6b"
+#include "exa_wm_write.g6b"
+};
+
+static const uint32_t ps_kernel_nomask_projective_static_gen6[][4] = {
+#include "exa_wm_src_projective.g6b"
+#include "exa_wm_src_sample_argb.g6b"
+#include "exa_wm_write.g6b"
+};
+
+static const uint32_t ps_kernel_maskca_affine_static_gen6[][4] = {
+#include "exa_wm_src_affine.g6b"
+#include "exa_wm_src_sample_argb.g6b"
+#include "exa_wm_mask_affine.g6b"
+#include "exa_wm_mask_sample_argb.g6b"
+#include "exa_wm_ca.g6b"
+#include "exa_wm_write.g6b"
+};
+
+static const uint32_t ps_kernel_maskca_projective_static_gen6[][4] = {
+#include "exa_wm_src_projective.g6b"
+#include "exa_wm_src_sample_argb.g6b"
+#include "exa_wm_mask_projective.g6b"
+#include "exa_wm_mask_sample_argb.g6b"
+#include "exa_wm_ca.g4b.gen5"
+#include "exa_wm_write.g6b"
+};
+
+static const uint32_t ps_kernel_maskca_srcalpha_affine_static_gen6[][4] = {
+#include "exa_wm_src_affine.g6b"
+#include "exa_wm_src_sample_a.g6b"
+#include "exa_wm_mask_affine.g6b"
+#include "exa_wm_mask_sample_argb.g6b"
+#include "exa_wm_ca_srcalpha.g6b"
+#include "exa_wm_write.g6b"
+};
+
+static const uint32_t ps_kernel_maskca_srcalpha_projective_static_gen6[][4] = {
+#include "exa_wm_src_projective.g6b"
+#include "exa_wm_src_sample_a.g6b"
+#include "exa_wm_mask_projective.g6b"
+#include "exa_wm_mask_sample_argb.g6b"
+#include "exa_wm_ca_srcalpha.g6b"
+#include "exa_wm_write.g6b"
+};
+
+static const uint32_t ps_kernel_masknoca_affine_static_gen6[][4] = {
+#include "exa_wm_src_affine.g6b"
+#include "exa_wm_src_sample_argb.g6b"
+#include "exa_wm_mask_affine.g6b"
+#include "exa_wm_mask_sample_a.g6b"
+#include "exa_wm_noca.g6b"
+#include "exa_wm_write.g6b"
+};
+
+static const uint32_t ps_kernel_masknoca_projective_static_gen6[][4] = {
+#include "exa_wm_src_projective.g6b"
+#include "exa_wm_src_sample_argb.g6b"
+#include "exa_wm_mask_projective.g6b"
+#include "exa_wm_mask_sample_a.g6b"
+#include "exa_wm_noca.g6b"
+#include "exa_wm_write.g6b"
+};
+
#define WM_STATE_DECL(kernel) \
struct brw_wm_unit_state wm_state_ ## kernel[SAMPLER_STATE_FILTER_COUNT] \
[SAMPLER_STATE_EXTEND_COUNT] \
@@ -607,6 +668,25 @@ static struct wm_kernel_info wm_kernels_gen5[] = {
ps_kernel_masknoca_projective_static_gen5, TRUE),
};
+static struct wm_kernel_info wm_kernels_gen6[] = {
+ KERNEL(WM_KERNEL_NOMASK_AFFINE,
+ ps_kernel_nomask_affine_static_gen6, FALSE),
+ KERNEL(WM_KERNEL_NOMASK_PROJECTIVE,
+ ps_kernel_nomask_projective_static_gen6, FALSE),
+ KERNEL(WM_KERNEL_MASKCA_AFFINE,
+ ps_kernel_maskca_affine_static_gen6, TRUE),
+ KERNEL(WM_KERNEL_MASKCA_PROJECTIVE,
+ ps_kernel_maskca_projective_static_gen6, TRUE),
+ KERNEL(WM_KERNEL_MASKCA_SRCALPHA_AFFINE,
+ ps_kernel_maskca_srcalpha_affine_static_gen6, TRUE),
+ KERNEL(WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE,
+ ps_kernel_maskca_srcalpha_projective_static_gen6, TRUE),
+ KERNEL(WM_KERNEL_MASKNOCA_AFFINE,
+ ps_kernel_masknoca_affine_static_gen6, TRUE),
+ KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE,
+ ps_kernel_masknoca_projective_static_gen6, TRUE),
+};
+
#undef KERNEL
typedef struct _brw_cc_unit_state_padded {
@@ -656,12 +736,22 @@ struct gen4_render_state {
drm_intel_bo *sip_kernel_bo;
dri_bo *vertex_buffer_bo;
+ drm_intel_bo *cc_vp_bo;
+ drm_intel_bo *gen6_blend_bo;
+ drm_intel_bo *gen6_depth_stencil_bo;
+ drm_intel_bo *ps_sampler_state_bo[SAMPLER_STATE_FILTER_COUNT]
+ [SAMPLER_STATE_EXTEND_COUNT]
+ [SAMPLER_STATE_FILTER_COUNT]
+ [SAMPLER_STATE_EXTEND_COUNT];
gen4_composite_op composite_op;
int vb_offset;
int vertex_size;
};
+static void gen6_emit_composite_state(ScrnInfoPtr scrn);
+static void gen6_render_state_init(ScrnInfoPtr scrn);
+
/**
* Sets up the SF state pointing at an SF kernel.
*
@@ -1489,9 +1579,27 @@ static Bool i965_composite_check_aperture(ScrnInfoPtr scrn)
render_state->cc_state_bo,
render_state->sip_kernel_bo,
};
-
- return drm_intel_bufmgr_check_aperture_space(bo_table,
- ARRAY_SIZE(bo_table)) == 0;
+ drm_intel_bo *gen6_bo_table[] = {
+ intel->batch_bo,
+ composite_op->surface_state_binding_table_bo,
+ render_state->vertex_buffer_bo,
+ render_state->wm_kernel_bo[composite_op->wm_kernel],
+ render_state->ps_sampler_state_bo[composite_op->src_filter]
+ [composite_op->src_extend]
+ [composite_op->mask_filter]
+ [composite_op->mask_extend],
+ render_state->cc_vp_bo,
+ render_state->cc_state_bo,
+ render_state->gen6_blend_bo,
+ render_state->gen6_depth_stencil_bo,
+ };
+
+ if (INTEL_INFO(intel)->gen >= 60)
+ return drm_intel_bufmgr_check_aperture_space(gen6_bo_table,
+ ARRAY_SIZE(gen6_bo_table)) == 0;
+ else
+ return drm_intel_bufmgr_check_aperture_space(bo_table,
+ ARRAY_SIZE(bo_table)) == 0;
}
Bool
@@ -1833,19 +1941,32 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
intel_batch_submit(scrn, FALSE);
intel_batch_start_atomic(scrn, 200);
- if (intel->needs_render_state_emit)
- i965_emit_composite_state(scrn);
+ if (intel->needs_render_state_emit) {
+ if (INTEL_INFO(intel)->gen >= 60)
+ gen6_emit_composite_state(scrn);
+ else
+ i965_emit_composite_state(scrn);
+ } else {
+ OUT_BATCH(MI_FLUSH);
+ }
- OUT_BATCH(MI_FLUSH);
/* Set up the pointer to our (single) vertex buffer */
OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3);
- OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
- VB0_VERTEXDATA |
- (render_state->vertex_size << VB0_BUFFER_PITCH_SHIFT));
+
+ if (INTEL_INFO(intel)->gen >= 60) {
+ OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
+ GEN6_VB0_VERTEXDATA |
+ (render_state->vertex_size << VB0_BUFFER_PITCH_SHIFT));
+ } else {
+ OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
+ VB0_VERTEXDATA |
+ (render_state->vertex_size << VB0_BUFFER_PITCH_SHIFT));
+ }
+
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
render_state->vb_offset * 4);
- if (IS_GEN5(intel))
+ if (INTEL_INFO(intel)->gen >= 50)
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
render_state->vb_offset * 4 + i * 4);
else
@@ -1894,6 +2015,9 @@ void gen4_render_state_init(ScrnInfoPtr scrn)
drm_intel_bo *sf_kernel_bo, *sf_kernel_mask_bo;
drm_intel_bo *border_color_bo;
+ if (INTEL_INFO(intel)->gen >= 60)
+ return gen6_render_state_init(scrn);
+
if (intel->gen4_render_state == NULL)
intel->gen4_render_state = calloc(sizeof(*render_state), 1);
@@ -2031,9 +2155,539 @@ void gen4_render_state_cleanup(ScrnInfoPtr scrn)
wm_state_bo[m][i][j][k]
[l]);
+ for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++)
+ for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++)
+ for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++)
+ for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++)
+ drm_intel_bo_unreference(render_state->ps_sampler_state_bo[i][j][k][l]);
+
drm_intel_bo_unreference(render_state->cc_state_bo);
drm_intel_bo_unreference(render_state->sip_kernel_bo);
+ drm_intel_bo_unreference(render_state->cc_vp_bo);
+ drm_intel_bo_unreference(render_state->gen6_blend_bo);
+ drm_intel_bo_unreference(render_state->gen6_depth_stencil_bo);
+
free(intel->gen4_render_state);
intel->gen4_render_state = NULL;
}
+
+/*
+ * for GEN6+
+ */
+#define GEN6_BLEND_STATE_PADDED_SIZE ALIGN(sizeof(struct gen6_blend_state), 64)
+
+static drm_intel_bo *
+gen6_composite_create_cc_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ struct gen6_color_calc_state *cc_state;
+ drm_intel_bo *cc_bo;
+
+ cc_bo = drm_intel_bo_alloc(intel->bufmgr,
+ "gen6 CC state",
+ sizeof(*cc_state),
+ 4096);
+ drm_intel_bo_map(cc_bo, TRUE);
+ cc_state = cc_bo->virtual;
+ memset(cc_state, 0, sizeof(*cc_state));
+ cc_state->constant_r = 1.0;
+ cc_state->constant_g = 0.0;
+ cc_state->constant_b = 1.0;
+ cc_state->constant_a = 1.0;
+ drm_intel_bo_unmap(cc_bo);
+
+ return cc_bo;
+}
+
+static drm_intel_bo *
+gen6_composite_create_blend_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ struct gen6_blend_state *blend_state;
+ drm_intel_bo *blend_bo;
+ int src_blend, dst_blend;
+
+ blend_bo = drm_intel_bo_alloc(intel->bufmgr,
+ "gen6 BLEND state",
+ BRW_BLENDFACTOR_COUNT * BRW_BLENDFACTOR_COUNT * GEN6_BLEND_STATE_PADDED_SIZE,
+ 4096);
+ drm_intel_bo_map(blend_bo, TRUE);
+ memset(blend_bo->virtual, 0, blend_bo->size);
+
+ for (src_blend = 0; src_blend < BRW_BLENDFACTOR_COUNT; src_blend++) {
+ for (dst_blend = 0; dst_blend < BRW_BLENDFACTOR_COUNT; dst_blend++) {
+ uint32_t blend_state_offset = ((src_blend * BRW_BLENDFACTOR_COUNT) + dst_blend) * GEN6_BLEND_STATE_PADDED_SIZE;
+
+ blend_state = (struct gen6_blend_state *)((char *)blend_bo->virtual + blend_state_offset);
+ blend_state->blend0.dest_blend_factor = dst_blend;
+ blend_state->blend0.source_blend_factor = src_blend;
+ blend_state->blend0.blend_func = BRW_BLENDFUNCTION_ADD;
+ blend_state->blend0.ia_blend_enable = 0;
+ blend_state->blend0.blend_enable = 1;
+
+ blend_state->blend1.post_blend_clamp_enable = 1;
+ blend_state->blend1.pre_blend_clamp_enable = 1;
+ blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
+ blend_state->blend1.dither_enable = 0;
+ blend_state->blend1.logic_op_enable = 0;
+ blend_state->blend1.alpha_test_enable = 0;
+ }
+ }
+
+ drm_intel_bo_unmap(blend_bo);
+ return blend_bo;
+}
+
+static drm_intel_bo *
+gen6_composite_create_depth_stencil_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ struct gen6_depth_stencil_state *depth_stencil_state;
+ drm_intel_bo *depth_stencil_bo;
+
+ depth_stencil_bo = drm_intel_bo_alloc(intel->bufmgr,
+ "gen6 DEPTH_STENCIL state",
+ sizeof(*depth_stencil_state),
+ 4096);
+ drm_intel_bo_map(depth_stencil_bo, TRUE);
+ depth_stencil_state = depth_stencil_bo->virtual;
+ memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
+ drm_intel_bo_unmap(depth_stencil_bo);
+
+ return depth_stencil_bo;
+}
+
+static void
+gen6_composite_invarient_states(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(MI_FLUSH |
+ MI_STATE_INSTRUCTION_CACHE_FLUSH |
+ BRW_MI_GLOBAL_SNAPSHOT_RESET);
+ OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
+ GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
+ OUT_BATCH(1);
+
+ /* Set system instruction pointer */
+ OUT_BATCH(BRW_STATE_SIP | 0);
+ OUT_BATCH(0);
+}
+
+static void
+gen6_composite_state_base_address(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_table_bo)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(BRW_STATE_BASE_ADDRESS | (10 - 2));
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state base address */
+ OUT_RELOC(surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* Dynamic state base address */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* Indirect object base address */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* Instruction base address */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state upper bound */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
+}
+
+static void
+gen6_composite_viewport_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *cc_vp_bo)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
+ GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
+ (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+}
+
+static void
+gen6_composite_urb(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
+ OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
+ (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
+ OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
+ (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
+}
+
+static void
+gen6_composite_cc_state_pointers(ScrnInfoPtr scrn,
+ drm_intel_bo *blend_state_bo,
+ uint32_t blend_state_offset,
+ drm_intel_bo *depth_stencil_state_bo,
+ uint32_t depth_stencil_state_offset,
+ drm_intel_bo *cc_state_bo,
+ uint32_t cc_state_offset)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
+ OUT_RELOC(blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, blend_state_offset | 1);
+ OUT_RELOC(depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, depth_stencil_state_offset | 1);
+ OUT_RELOC(cc_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, cc_state_offset | 1);
+}
+
+static void
+gen6_composite_sampler_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *ps_sampler_state_bo)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
+ GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
+ (4 - 2));
+ OUT_BATCH(0); /* VS */
+ OUT_BATCH(0); /* GS */
+ OUT_RELOC(ps_sampler_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+}
+
+static void
+gen6_composite_vs_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ /* disable VS constant buffer */
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
+ OUT_BATCH(0); /* without VS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+}
+
+static void
+gen6_composite_gs_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ /* disable GS constant buffer */
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
+ OUT_BATCH(0); /* without GS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+}
+
+static void
+gen6_composite_clip_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+ OUT_BATCH(0);
+}
+
+static void
+gen6_composite_sf_state(ScrnInfoPtr scrn, Bool has_mask)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ int num_sf_outputs = has_mask ? 2 : 1;
+
+ OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
+ OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
+ (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
+ (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
+ OUT_BATCH(0);
+ OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
+ OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW9 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW14 */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* DW19 */
+}
+
+static void
+gen6_composite_wm_state(ScrnInfoPtr scrn, Bool has_mask, drm_intel_bo *kernel_bo)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ int num_surfaces = has_mask ? 3 : 2;
+ int num_sf_outputs = has_mask ? 2 : 1;
+
+ /* disable WM constant buffer */
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN6_3DSTATE_WM | (9 - 2));
+ OUT_RELOC(kernel_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+ OUT_BATCH((1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
+ (num_surfaces << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+ OUT_BATCH(0);
+ OUT_BATCH((6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
+ OUT_BATCH(((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
+ GEN6_3DSTATE_WM_DISPATCH_ENABLE |
+ GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
+ OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
+ GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+static void
+gen6_composite_binding_table_pointers(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ /* Binding table pointers */
+ OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS |
+ GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
+ (4 - 2));
+ OUT_BATCH(0); /* vs */
+ OUT_BATCH(0); /* gs */
+ /* Only the PS uses the binding table */
+ OUT_BATCH(PS_BINDING_TABLE_OFFSET);
+}
+
+static void
+gen6_composite_depth_buffer_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
+ OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
+ (BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2));
+ OUT_BATCH(0);
+}
+
+static void
+gen6_composite_drawing_rectangle(ScrnInfoPtr scrn, PixmapPtr dest)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(0x00000000); /* ymin, xmin */
+ OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) | DRAW_XMAX(dest->drawable.width - 1)); /* ymax, xmax */
+ OUT_BATCH(0x00000000); /* yorigin, xorigin */
+}
+
+static void
+gen6_composite_vertex_element_state(ScrnInfoPtr scrn, Bool has_mask, Bool is_affine)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ struct gen4_render_state *render_state = intel->gen4_render_state;
+ /*
+ * vertex data in vertex buffer
+ * position: (x, y)
+ * texture coordinate 0: (u0, v0) if (is_affine is TRUE) else (u0, v0, w0)
+ * texture coordinate 1 if (has_mask is TRUE): same as above
+ */
+ int nelem = has_mask ? 2 : 1;
+ int selem = is_affine ? 2 : 3;
+ uint32_t w_component;
+ uint32_t src_format;
+
+ render_state->vertex_size = 4 * (2 + nelem * selem);
+
+ if (is_affine) {
+ src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
+ w_component = BRW_VFCOMPONENT_STORE_1_FLT;
+ } else {
+ src_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
+ w_component = BRW_VFCOMPONENT_STORE_SRC;
+ }
+
+ /* The VUE layout
+ * dword 0-3: pad (0.0, 0.0, 0.0. 0.0)
+ * dword 4-7: position (x, y, 1.0, 1.0),
+ * dword 8-11: texture coordinate 0 (u0, v0, w0, 1.0)
+ * dword 12-15: texture coordinate 1 (u1, v1, w1, 1.0)
+ *
+ * dword 4-15 are fetched from vertex buffer
+ */
+ OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS |
+ ((2 * (2 + nelem)) + 1 - 2));
+
+ OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ GEN6_VE0_VALID |
+ (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+ (0 << VE0_OFFSET_SHIFT));
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
+
+ /* x,y */
+ OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ GEN6_VE0_VALID |
+ (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+ (0 << VE0_OFFSET_SHIFT)); /* offsets vb in bytes */
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
+
+ /* u0, v0, w0 */
+ OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ GEN6_VE0_VALID |
+ (src_format << VE0_FORMAT_SHIFT) |
+ ((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (w_component << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
+
+ /* u1, v1, w1 */
+ if (has_mask) {
+ OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ GEN6_VE0_VALID |
+ (src_format << VE0_FORMAT_SHIFT) |
+ (((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (w_component << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
+ }
+}
+
+static void
+gen6_emit_composite_state(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ struct gen4_render_state *render_state = intel->gen4_render_state;
+ gen4_composite_op *composite_op = &render_state->composite_op;
+ int op = composite_op->op;
+ PicturePtr mask_picture = intel->render_mask_picture;
+ PicturePtr dest_picture = intel->render_dest_picture;
+ PixmapPtr mask = intel->render_mask;
+ PixmapPtr dest = intel->render_dest;
+ sampler_state_filter_t src_filter = composite_op->src_filter;
+ sampler_state_filter_t mask_filter = composite_op->mask_filter;
+ sampler_state_extend_t src_extend = composite_op->src_extend;
+ sampler_state_extend_t mask_extend = composite_op->mask_extend;
+ Bool is_affine = composite_op->is_affine;
+ uint32_t src_blend, dst_blend;
+ drm_intel_bo *surface_state_binding_table_bo = composite_op->surface_state_binding_table_bo;
+ drm_intel_bo *ps_sampler_state_bo = render_state->ps_sampler_state_bo[src_filter][src_extend][mask_filter][mask_extend];
+
+ intel->needs_render_state_emit = FALSE;
+ IntelEmitInvarientState(scrn);
+ intel->last_3d = LAST_3D_RENDER;
+
+ /* Mark the destination dirty within this batch */
+ intel_batch_mark_pixmap_domains(intel,
+ intel_get_pixmap_private(dest),
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
+ i965_get_blend_cntl(op,
+ mask_picture,
+ dest_picture->format,
+ &src_blend,
+ &dst_blend);
+ assert(intel->in_batch_atomic);
+ gen6_composite_invarient_states(scrn);
+ gen6_composite_state_base_address(scrn, surface_state_binding_table_bo);
+ gen6_composite_viewport_state_pointers(scrn, render_state->cc_vp_bo);
+ gen6_composite_urb(scrn);
+ gen6_composite_cc_state_pointers(scrn,
+ render_state->gen6_blend_bo,
+ ((src_blend * BRW_BLENDFACTOR_COUNT) + dst_blend) * GEN6_BLEND_STATE_PADDED_SIZE,
+ render_state->gen6_depth_stencil_bo,
+ 0,
+ render_state->cc_state_bo,
+ 0);
+ gen6_composite_sampler_state_pointers(scrn, ps_sampler_state_bo);
+ gen6_composite_vs_state(scrn);
+ gen6_composite_gs_state(scrn);
+ gen6_composite_clip_state(scrn);
+ gen6_composite_sf_state(scrn, mask != 0);
+ gen6_composite_wm_state(scrn, mask != 0, render_state->wm_kernel_bo[composite_op->wm_kernel]);
+ gen6_composite_binding_table_pointers(scrn);
+ gen6_composite_depth_buffer_state(scrn);
+ gen6_composite_drawing_rectangle(scrn, dest);
+ gen6_composite_vertex_element_state(scrn, mask != 0, is_affine);
+}
+
+static void
+gen6_render_state_init(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ struct gen4_render_state *render_state;
+ int i, j, k, l, m;
+ drm_intel_bo *border_color_bo;
+
+ if (intel->gen4_render_state == NULL)
+ intel->gen4_render_state = calloc(sizeof(*render_state), 1);
+
+ render_state = intel->gen4_render_state;
+ render_state->vb_offset = 0;
+
+ for (m = 0; m < WM_KERNEL_COUNT; m++) {
+ render_state->wm_kernel_bo[m] =
+ intel_bo_alloc_for_data(scrn,
+ wm_kernels_gen6[m].data,
+ wm_kernels_gen6[m].size,
+ "WM kernel gen6");
+ }
+
+ border_color_bo = sampler_border_color_create(scrn);
+
+ for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) {
+ for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) {
+ for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) {
+ for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++) {
+ render_state->ps_sampler_state_bo[i][j][k][l] =
+ gen4_create_sampler_state(scrn,
+ i, j,
+ k, l,
+ border_color_bo);
+ }
+ }
+ }
+ }
+
+ drm_intel_bo_unreference(border_color_bo);
+ render_state->cc_vp_bo = gen4_create_cc_viewport(scrn);
+ render_state->cc_state_bo = gen6_composite_create_cc_state(scrn);
+ render_state->gen6_blend_bo = gen6_composite_create_blend_state(scrn);
+ render_state->gen6_depth_stencil_bo = gen6_composite_create_depth_stencil_state(scrn);
+}
commit 0ab2c05a291738ee763eb518c46e6dcfe29249a2
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Wed Oct 27 16:49:26 2010 +0800
render: fragments for composite on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am
index 5229ef5..1a19437 100644
--- a/src/render_program/Makefile.am
+++ b/src/render_program/Makefile.am
@@ -63,15 +63,33 @@ INTEL_G4B_GEN5 = \
INTEL_G6A = \
exa_wm_src_affine.g6a \
+ exa_wm_src_projective.g6a \
exa_wm_src_sample_argb.g6a \
exa_wm_src_sample_planar.g6a \
+ exa_wm_src_sample_a.g6a \
+ exa_wm_mask_affine.g6a \
+ exa_wm_mask_projective.g6a \
+ exa_wm_mask_sample_argb.g6a \
+ exa_wm_mask_sample_a.g6a \
+ exa_wm_ca.g6a \
+ exa_wm_ca_srcalpha.g6a \
+ exa_wm_noca.g6a \
exa_wm_write.g6a \
exa_wm_yuv_rgb.g6a
INTEL_G6B = \
exa_wm_src_affine.g6b \
+ exa_wm_src_projective.g6b \
exa_wm_src_sample_argb.g6b \
exa_wm_src_sample_planar.g6b \
+ exa_wm_src_sample_a.g6b \
+ exa_wm_mask_affine.g6b \
+ exa_wm_mask_projective.g6b \
+ exa_wm_mask_sample_argb.g6b \
+ exa_wm_mask_sample_a.g6b \
+ exa_wm_ca.g6b \
+ exa_wm_ca_srcalpha.g6b \
+ exa_wm_noca.g6b \
exa_wm_write.g6b \
exa_wm_yuv_rgb.g6b
diff --git a/src/render_program/exa_wm_ca.g6a b/src/render_program/exa_wm_ca.g6a
new file mode 120000
index 0000000..a29acb1
--- /dev/null
+++ b/src/render_program/exa_wm_ca.g6a
@@ -0,0 +1 @@
+exa_wm_ca.g4a
\ No newline at end of file
diff --git a/src/render_program/exa_wm_ca.g6b b/src/render_program/exa_wm_ca.g6b
new file mode 100644
index 0000000..521a5b6
--- /dev/null
+++ b/src/render_program/exa_wm_ca.g6b
@@ -0,0 +1,4 @@
+ { 0x00800041, 0x21c077bd, 0x008d01c0, 0x008d02c0 },
+ { 0x00800041, 0x220077bd, 0x008d0200, 0x008d0300 },
+ { 0x00800041, 0x224077bd, 0x008d0240, 0x008d0340 },
+ { 0x00800041, 0x228077bd, 0x008d0280, 0x008d0380 },
diff --git a/src/render_program/exa_wm_ca_srcalpha.g6a b/src/render_program/exa_wm_ca_srcalpha.g6a
new file mode 120000
index 0000000..3503521
--- /dev/null
+++ b/src/render_program/exa_wm_ca_srcalpha.g6a
@@ -0,0 +1 @@
+exa_wm_ca_srcalpha.g4a
\ No newline at end of file
diff --git a/src/render_program/exa_wm_ca_srcalpha.g6b b/src/render_program/exa_wm_ca_srcalpha.g6b
new file mode 100644
index 0000000..d5ab7e4
--- /dev/null
+++ b/src/render_program/exa_wm_ca_srcalpha.g6b
@@ -0,0 +1,4 @@
+ { 0x00800041, 0x21c077bd, 0x008d02c0, 0x008d0280 },
+ { 0x00800041, 0x220077bd, 0x008d0300, 0x008d0280 },
+ { 0x00800041, 0x224077bd, 0x008d0340, 0x008d0280 },
+ { 0x00800041, 0x228077bd, 0x008d0380, 0x008d0280 },
diff --git a/src/render_program/exa_wm_mask_affine.g6a b/src/render_program/exa_wm_mask_affine.g6a
new file mode 100644
index 0000000..2daf4e2
--- /dev/null
+++ b/src/render_program/exa_wm_mask_affine.g6a
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * Fragment to compute src u/v values
+ */
+include(`exa_wm.g4i')
+
+define(`ul', `mask_u')
+define(`uh', `m9')
+define(`vl', `mask_v')
+define(`vh', `m11')
+
+define(`bl', `g2.0<8,8,1>F')
+define(`bh', `g4.0<8,8,1>F')
+
+define(`a0_a_x',`g8.0<0,1,0>F')
+define(`a0_a_y',`g8.16<0,1,0>F')
+
+/* U */
+pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
+pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
+
+/* V */
+pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */
+pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */
diff --git a/src/render_program/exa_wm_mask_affine.g6b b/src/render_program/exa_wm_mask_affine.g6b
new file mode 100644
index 0000000..e4bef29
--- /dev/null
+++ b/src/render_program/exa_wm_mask_affine.g6b
@@ -0,0 +1,4 @@
+ { 0x0060005a, 0x210077be, 0x00000100, 0x008d0040 },
+ { 0x0060005a, 0x212077be, 0x00000100, 0x008d0080 },
+ { 0x0060005a, 0x214077be, 0x00000110, 0x008d0040 },
+ { 0x0060005a, 0x216077be, 0x00000110, 0x008d0080 },
diff --git a/src/render_program/exa_wm_mask_projective.g6a b/src/render_program/exa_wm_mask_projective.g6a
new file mode 100644
index 0000000..378c277
--- /dev/null
+++ b/src/render_program/exa_wm_mask_projective.g6a
@@ -0,0 +1,63 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * Fragment to compute src u/v values
+ */
+include(`exa_wm.g4i')
+
+define(`u', `mask_u')
+define(`ul', `mask_u')
+define(`uh', `m9')
+define(`v', `mask_v')
+define(`vl', `mask_v')
+define(`vh', `m11')
+define(`w', `mask_w')
+define(`wl', `mask_w_0')
+define(`wh', `mask_w_1')
+
+define(`bl', `g2.0<8,8,1>F')
+define(`bh', `g4.0<8,8,1>F')
+
+define(`a0_a_x',`g8.0<0,1,0>F')
+define(`a0_a_y',`g8.16<0,1,0>F')
+define(`a0_a_z',`g9.0<0,1,0>F')
+
+/* W */
+pln (8) temp_x_0<1>F a0_a_z bl { align1 }; /* pixel 0-7 */
+pln (8) temp_x_1<1>F a0_a_z bh { align1 }; /* pixel 8-15 */
+math (8) wl<1>F temp_x_0<8,8,1>F null inv { align1 };
+math (8) wh<1>F temp_x_1<8,8,1>F null inv { align1 };
+
+/* U */
+pln (8) temp_x_0<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
+pln (8) temp_x_1<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
+mul (8) ul<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 };
+mul (8) uh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 };
+
+/* V */
+pln (8) temp_x_0<1>F a0_a_y bl { align1 }; /* pixel 0-7 */
+pln (8) temp_x_1<1>F a0_a_y bh { align1 }; /* pixel 8-15 */
+mul (8) vl<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 };
+mul (8) vh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 };
diff --git a/src/render_program/exa_wm_mask_projective.g6b b/src/render_program/exa_wm_mask_projective.g6b
new file mode 100644
index 0000000..dddcb4b
--- /dev/null
+++ b/src/render_program/exa_wm_mask_projective.g6b
@@ -0,0 +1,12 @@
+ { 0x0060005a, 0x23c077bd, 0x00000120, 0x008d0040 },
+ { 0x0060005a, 0x23e077bd, 0x00000120, 0x008d0080 },
+ { 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 },
+ { 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 },
+ { 0x0060005a, 0x23c077bd, 0x00000100, 0x008d0040 },
+ { 0x0060005a, 0x23e077bd, 0x00000100, 0x008d0080 },
+ { 0x00600041, 0x210077be, 0x008d03c0, 0x008d0180 },
+ { 0x00600041, 0x212077be, 0x008d03e0, 0x008d01a0 },
+ { 0x0060005a, 0x23c077bd, 0x00000110, 0x008d0040 },
+ { 0x0060005a, 0x23e077bd, 0x00000110, 0x008d0080 },
+ { 0x00600041, 0x214077be, 0x008d03c0, 0x008d0180 },
+ { 0x00600041, 0x216077be, 0x008d03e0, 0x008d01a0 },
diff --git a/src/render_program/exa_wm_mask_sample_a.g6a b/src/render_program/exa_wm_mask_sample_a.g6a
new file mode 120000
index 0000000..9e34bd1
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_a.g6a
@@ -0,0 +1 @@
+exa_wm_mask_sample_a.g4a
\ No newline at end of file
diff --git a/src/render_program/exa_wm_mask_sample_a.g6b b/src/render_program/exa_wm_mask_sample_a.g6b
new file mode 100644
index 0000000..6d1eae9
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_a.g6b
@@ -0,0 +1,3 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
+ { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 },
+ { 0x02800031, 0x23801cc9, 0x000000e0, 0x0a2a0102 },
diff --git a/src/render_program/exa_wm_mask_sample_argb.g6a b/src/render_program/exa_wm_mask_sample_argb.g6a
new file mode 120000
index 0000000..b7443bd
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_argb.g6a
@@ -0,0 +1 @@
+exa_wm_mask_sample_argb.g4a
\ No newline at end of file
diff --git a/src/render_program/exa_wm_mask_sample_argb.g6b b/src/render_program/exa_wm_mask_sample_argb.g6b
new file mode 100644
index 0000000..e5630bd
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_argb.g6b
@@ -0,0 +1,3 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 },
+ { 0x02800031, 0x22c01cc9, 0x000000e0, 0x0a8a0102 },
diff --git a/src/render_program/exa_wm_noca.g6a b/src/render_program/exa_wm_noca.g6a
new file mode 120000
index 0000000..cbf851e
--- /dev/null
+++ b/src/render_program/exa_wm_noca.g6a
@@ -0,0 +1 @@
+exa_wm_noca.g4a
\ No newline at end of file
diff --git a/src/render_program/exa_wm_noca.g6b b/src/render_program/exa_wm_noca.g6b
new file mode 100644
index 0000000..e77ea2d
--- /dev/null
+++ b/src/render_program/exa_wm_noca.g6b
@@ -0,0 +1,4 @@
+ { 0x00800041, 0x21c077bd, 0x008d01c0, 0x008d0380 },
+ { 0x00800041, 0x220077bd, 0x008d0200, 0x008d0380 },
+ { 0x00800041, 0x224077bd, 0x008d0240, 0x008d0380 },
+ { 0x00800041, 0x228077bd, 0x008d0280, 0x008d0380 },
diff --git a/src/render_program/exa_wm_src_projective.g6a b/src/render_program/exa_wm_src_projective.g6a
new file mode 100644
index 0000000..af08eff
--- /dev/null
+++ b/src/render_program/exa_wm_src_projective.g6a
@@ -0,0 +1,63 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * Fragment to compute src u/v values
+ */
+include(`exa_wm.g4i')
+
+define(`u', `src_u')
+define(`ul', `src_u')
+define(`uh', `m3')
+define(`v', `src_v')
+define(`vl', `src_v')
+define(`vh', `m5')
+define(`w', `src_w')
+define(`wl', `src_w_0')
+define(`wh', `src_w_1')
+
+define(`bl', `g2.0<8,8,1>F')
+define(`bh', `g4.0<8,8,1>F')
+
+define(`a0_a_x',`g6.0<0,1,0>F')
+define(`a0_a_y',`g6.16<0,1,0>F')
+define(`a0_a_z',`g7.0<0,1,0>F')
+
+/* W */
+pln (8) temp_x_0<1>F a0_a_z bl { align1 }; /* pixel 0-7 */
+pln (8) temp_x_1<1>F a0_a_z bh { align1 }; /* pixel 8-15 */
+math (8) wl<1>F temp_x_0<8,8,1>F null inv { align1 };
+math (8) wh<1>F temp_x_1<8,8,1>F null inv { align1 };
+
+/* U */
+pln (8) temp_x_0<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
+pln (8) temp_x_1<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
+mul (8) ul<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 };
+mul (8) uh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 };
+
+/* V */
+pln (8) temp_x_0<1>F a0_a_y bl { align1 }; /* pixel 0-7 */
+pln (8) temp_x_1<1>F a0_a_y bh { align1 }; /* pixel 8-15 */
+mul (8) vl<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 };
+mul (8) vh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 };
diff --git a/src/render_program/exa_wm_src_projective.g6b b/src/render_program/exa_wm_src_projective.g6b
new file mode 100644
index 0000000..8e39bff
--- /dev/null
+++ b/src/render_program/exa_wm_src_projective.g6b
@@ -0,0 +1,12 @@
+ { 0x0060005a, 0x23c077bd, 0x000000e0, 0x008d0040 },
+ { 0x0060005a, 0x23e077bd, 0x000000e0, 0x008d0080 },
+ { 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 },
+ { 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 },
+ { 0x0060005a, 0x23c077bd, 0x000000c0, 0x008d0040 },
+ { 0x0060005a, 0x23e077bd, 0x000000c0, 0x008d0080 },
+ { 0x00600041, 0x204077be, 0x008d03c0, 0x008d0180 },
+ { 0x00600041, 0x206077be, 0x008d03e0, 0x008d01a0 },
+ { 0x0060005a, 0x23c077bd, 0x000000d0, 0x008d0040 },
+ { 0x0060005a, 0x23e077bd, 0x000000d0, 0x008d0080 },
+ { 0x00600041, 0x208077be, 0x008d03c0, 0x008d0180 },
+ { 0x00600041, 0x20a077be, 0x008d03e0, 0x008d01a0 },
diff --git a/src/render_program/exa_wm_src_sample_a.g6a b/src/render_program/exa_wm_src_sample_a.g6a
new file mode 120000
index 0000000..c6e112c
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_a.g6a
@@ -0,0 +1 @@
+exa_wm_src_sample_a.g4a
\ No newline at end of file
diff --git a/src/render_program/exa_wm_src_sample_a.g6b b/src/render_program/exa_wm_src_sample_a.g6b
new file mode 100644
index 0000000..0b4a955
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_a.g6b
@@ -0,0 +1,3 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
+ { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 },
+ { 0x02800031, 0x22801cc9, 0x00000020, 0x0a2a0001 },
commit 21c86548dc2c80632c49ec6ec4da2935a0c99476
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Wed Oct 27 16:47:36 2010 +0800
render: fix send instruction used in sampling fragments
To prepare for composite on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/src/render_program/exa_wm_mask_sample_a.g4a b/src/render_program/exa_wm_mask_sample_a.g4a
index bbb19d7..b1c75af 100644
--- a/src/render_program/exa_wm_mask_sample_a.g4a
+++ b/src/render_program/exa_wm_mask_sample_a.g4a
@@ -36,12 +36,13 @@ include(`exa_wm.g4i')
/* load only alpha */
mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable };
+mov (8) mask_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
/* mask_msg will be copied with g0, as it contains send desc */
/* emit sampler 'send' cmd */
send (16) mask_msg_ind /* msg reg index */
mask_sample_a_01<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
+ null
sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype)
/* here(src->dst) we should use src_sampler and src_surface */
mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/render_program/exa_wm_mask_sample_a.g4b b/src/render_program/exa_wm_mask_sample_a.g4b
index 018bd36..7db47ca 100644
--- a/src/render_program/exa_wm_mask_sample_a.g4b
+++ b/src/render_program/exa_wm_mask_sample_a.g4b
@@ -1,2 +1,3 @@
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
- { 0x07800031, 0x23801d29, 0x008d0000, 0x02520102 },
+ { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 },
+ { 0x07800031, 0x23801c09, 0x00000000, 0x02520102 },
diff --git a/src/render_program/exa_wm_mask_sample_a.g4b.gen5 b/src/render_program/exa_wm_mask_sample_a.g4b.gen5
index d9740ac..472c2bb 100644
--- a/src/render_program/exa_wm_mask_sample_a.g4b.gen5
+++ b/src/render_program/exa_wm_mask_sample_a.g4b.gen5
@@ -1,2 +1,3 @@
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
- { 0x07800031, 0x23801d29, 0x208d0000, 0x0a2a0102 },
+ { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 },
+ { 0x07800031, 0x23801c09, 0x20000000, 0x0a2a0102 },
diff --git a/src/render_program/exa_wm_mask_sample_argb.g4a b/src/render_program/exa_wm_mask_sample_argb.g4a
index def4cfe..78bfc92 100644
--- a/src/render_program/exa_wm_mask_sample_argb.g4a
+++ b/src/render_program/exa_wm_mask_sample_argb.g4a
@@ -36,12 +36,13 @@ include(`exa_wm.g4i')
/* load argb */
mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable };
+mov (8) mask_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
/* mask_msg will be copied with g0, as it contains send desc */
/* emit sampler 'send' cmd */
send (16) mask_msg_ind /* msg reg index */
mask_sample_base<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
+ null
sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype)
/* here(src->dst) we should use src_sampler and src_surface */
mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/render_program/exa_wm_mask_sample_argb.g4b b/src/render_program/exa_wm_mask_sample_argb.g4b
index b159cba..9026ee2 100644
--- a/src/render_program/exa_wm_mask_sample_argb.g4b
+++ b/src/render_program/exa_wm_mask_sample_argb.g4b
@@ -1,2 +1,3 @@
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
- { 0x07800031, 0x22c01d29, 0x008d0000, 0x02580102 },
+ { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 },
+ { 0x07800031, 0x22c01c09, 0x00000000, 0x02580102 },
diff --git a/src/render_program/exa_wm_mask_sample_argb.g4b.gen5 b/src/render_program/exa_wm_mask_sample_argb.g4b.gen5
index f0a6ddd..cb112d5 100644
--- a/src/render_program/exa_wm_mask_sample_argb.g4b.gen5
+++ b/src/render_program/exa_wm_mask_sample_argb.g4b.gen5
@@ -1,2 +1,3 @@
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
- { 0x07800031, 0x22c01d29, 0x208d0000, 0x0a8a0102 },
+ { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 },
+ { 0x07800031, 0x22c01c09, 0x20000000, 0x0a8a0102 },
diff --git a/src/render_program/exa_wm_src_sample_a.g4a b/src/render_program/exa_wm_src_sample_a.g4a
index 552aaee..667bfb3 100644
--- a/src/render_program/exa_wm_src_sample_a.g4a
+++ b/src/render_program/exa_wm_src_sample_a.g4a
@@ -36,12 +36,13 @@ include(`exa_wm.g4i')
/* load alpha */
mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable };
+mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
/* src_msg will be copied with g0, as it contains send desc */
/* emit sampler 'send' cmd */
send (16) src_msg_ind /* msg reg index */
src_sample_a_01<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
+ null
sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
/* here(src->dst) we should use src_sampler and src_surface */
mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/render_program/exa_wm_src_sample_a.g4b b/src/render_program/exa_wm_src_sample_a.g4b
index ce8650a..5e5a11f 100644
--- a/src/render_program/exa_wm_src_sample_a.g4b
+++ b/src/render_program/exa_wm_src_sample_a.g4b
@@ -1,2 +1,3 @@
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
- { 0x01800031, 0x22801d29, 0x008d0000, 0x02520001 },
+ { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 },
+ { 0x01800031, 0x22801c09, 0x00000000, 0x02520001 },
diff --git a/src/render_program/exa_wm_src_sample_a.g4b.gen5 b/src/render_program/exa_wm_src_sample_a.g4b.gen5
index 8cd411c..0e4eebe 100644
--- a/src/render_program/exa_wm_src_sample_a.g4b.gen5
+++ b/src/render_program/exa_wm_src_sample_a.g4b.gen5
@@ -1,2 +1,3 @@
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
- { 0x01800031, 0x22801d29, 0x208d0000, 0x0a2a0001 },
+ { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 },
+ { 0x01800031, 0x22801c09, 0x20000000, 0x0a2a0001 },
commit 8d008ca89d44aa10aeb032d631971aaebb388675
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Mon Oct 25 15:39:39 2010 +0800
render: set the surface state base address
It is the same as commit 73d4c7d7
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
diff --git a/src/i965_render.c b/src/i965_render.c
index c0c5de4..885889e 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -619,6 +619,8 @@ typedef struct brw_surface_state_padded {
char pad[32 - sizeof(struct brw_surface_state)];
} brw_surface_state_padded;
+#define PS_BINDING_TABLE_OFFSET (3 * sizeof(struct brw_surface_state_padded))
+
struct gen4_cc_unit_state {
/* Index by [src_blend][dst_blend] */
brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT]
@@ -629,7 +631,7 @@ typedef float gen4_vertex_buffer[VERTEX_BUFFER_SIZE];
typedef struct gen4_composite_op {
int op;
- drm_intel_bo *binding_table_bo;
+ drm_intel_bo *surface_state_binding_table_bo;
sampler_state_filter_t src_filter;
sampler_state_filter_t mask_filter;
sampler_state_extend_t src_extend;
@@ -1158,7 +1160,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
int urb_sf_start, urb_sf_size;
int urb_cs_start, urb_cs_size;
uint32_t src_blend, dst_blend;
- dri_bo *binding_table_bo = composite_op->binding_table_bo;
+ dri_bo *surface_state_binding_table_bo = composite_op->surface_state_binding_table_bo;
intel->needs_render_state_emit = FALSE;
@@ -1216,7 +1218,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
if (IS_GEN5(intel)) {
OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6);
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
+ OUT_RELOC(surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction base address */
/* general state max addr, disabled */
@@ -1228,7 +1230,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
} else {
OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
+ OUT_RELOC(surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
/* general state max addr, disabled */
OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
@@ -1271,7 +1273,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
/* Only the PS uses the binding table */
- OUT_RELOC(binding_table_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
+ OUT_BATCH(PS_BINDING_TABLE_OFFSET);
/* The drawing rectangle clipping is always on. Set it to values that
* shouldn't do any clipping.
@@ -1474,7 +1476,7 @@ static Bool i965_composite_check_aperture(ScrnInfoPtr scrn)
gen4_composite_op *composite_op = &render_state->composite_op;
drm_intel_bo *bo_table[] = {
intel->batch_bo,
- composite_op->binding_table_bo,
+ composite_op->surface_state_binding_table_bo,
render_state->vertex_buffer_bo,
render_state->vs_state_bo,
render_state->sf_state_bo,
@@ -1502,7 +1504,7 @@ i965_prepare_composite(int op, PicturePtr source_picture,
struct gen4_render_state *render_state = intel->gen4_render_state;
gen4_composite_op *composite_op = &render_state->composite_op;
uint32_t *binding_table;
- drm_intel_bo *binding_table_bo, *surface_state_bo;
+ drm_intel_bo *surface_state_binding_table_bo;
composite_op->src_filter =
sampler_state_filter_from_picture(source_picture->filter);
@@ -1562,65 +1564,36 @@ i965_prepare_composite(int op, PicturePtr source_picture,
/* Set up the surface states. */
- surface_state_bo = dri_bo_alloc(intel->bufmgr, "surface_state",
- 3 * sizeof(brw_surface_state_padded),
+ surface_state_binding_table_bo = dri_bo_alloc(intel->bufmgr, "surface_state",
+ 3 * (sizeof(struct brw_surface_state_padded) + sizeof(uint32_t)),
4096);
- if (dri_bo_map(surface_state_bo, 1) != 0) {
- dri_bo_unreference(surface_state_bo);
+ if (dri_bo_map(surface_state_binding_table_bo, 1) != 0) {
+ dri_bo_unreference(surface_state_binding_table_bo);
return FALSE;
}
/* Set up the state buffer for the destination surface */
- i965_set_picture_surface_state(intel, surface_state_bo, 0,
+ i965_set_picture_surface_state(intel, surface_state_binding_table_bo, 0,
dest_picture, dest, TRUE);
/* Set up the source surface state buffer */
- i965_set_picture_surface_state(intel, surface_state_bo, 1,
+ i965_set_picture_surface_state(intel, surface_state_binding_table_bo, 1,
source_picture, source, FALSE);
if (mask) {
/* Set up the mask surface state buffer */
- i965_set_picture_surface_state(intel, surface_state_bo, 2,
+ i965_set_picture_surface_state(intel, surface_state_binding_table_bo, 2,
mask_picture, mask, FALSE);
}
- dri_bo_unmap(surface_state_bo);
/* Set up the binding table of surface indices to surface state. */
- binding_table_bo = dri_bo_alloc(intel->bufmgr, "binding_table",
- 3 * sizeof(uint32_t), 4096);
- if (dri_bo_map(binding_table_bo, 1) != 0) {
- dri_bo_unreference(binding_table_bo);
- dri_bo_unreference(surface_state_bo);
- return FALSE;
- }
-
- binding_table = binding_table_bo->virtual;
- binding_table[0] = intel_emit_reloc(binding_table_bo,
- 0 * sizeof(uint32_t),
- surface_state_bo,
- 0 *
- sizeof(brw_surface_state_padded),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
-
- binding_table[1] = intel_emit_reloc(binding_table_bo,
- 1 * sizeof(uint32_t),
- surface_state_bo,
- 1 *
- sizeof(brw_surface_state_padded),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ binding_table = (uint32_t *)((char *)surface_state_binding_table_bo->virtual + PS_BINDING_TABLE_OFFSET);
+ binding_table[0] = 0;
+ binding_table[1] = sizeof(struct brw_surface_state_padded);
if (mask) {
- binding_table[2] = intel_emit_reloc(binding_table_bo,
- 2 * sizeof(uint32_t),
- surface_state_bo,
- 2 *
- sizeof
- (brw_surface_state_padded),
- I915_GEM_DOMAIN_INSTRUCTION,
- 0);
+ binding_table[2] = 2 * sizeof(struct brw_surface_state_padded);
} else {
binding_table[2] = 0;
}
- dri_bo_unmap(binding_table_bo);
- /* All refs to surface_state are now contained in binding_table_bo. */
- drm_intel_bo_unreference(surface_state_bo);
+ dri_bo_unmap(surface_state_binding_table_bo);
composite_op->op = op;
intel->render_source_picture = source_picture;
@@ -1629,8 +1602,8 @@ i965_prepare_composite(int op, PicturePtr source_picture,
intel->render_source = source;
intel->render_mask = mask;
intel->render_dest = dest;
- drm_intel_bo_unreference(composite_op->binding_table_bo);
- composite_op->binding_table_bo = binding_table_bo;
+ drm_intel_bo_unreference(composite_op->surface_state_binding_table_bo);
+ composite_op->surface_state_binding_table_bo = surface_state_binding_table_bo;
intel->scale_units[0][0] = source->drawable.width;
intel->scale_units[0][1] = source->drawable.height;
@@ -2038,7 +2011,7 @@ void gen4_render_state_cleanup(ScrnInfoPtr scrn)
int i, j, k, l, m;
gen4_composite_op *composite_op = &render_state->composite_op;
- drm_intel_bo_unreference(composite_op->binding_table_bo);
+ drm_intel_bo_unreference(composite_op->surface_state_binding_table_bo);
drm_intel_bo_unreference(render_state->vertex_buffer_bo);
drm_intel_bo_unreference(render_state->vs_state_bo);
More information about the xorg-commit
mailing list