xf86-video-intel: 3 commits - src/i830_uxa.c uxa/uxa-render.c

[Chris Wilson]

 src/i830_uxa.c   |   25 ++++++++++++++++++++-----
 uxa/uxa-render.c |   22 +++++++++++++++++++++-
 2 files changed, 41 insertions(+), 6 deletions(-)

New commits:
commit 5537079c29a56133446f1874d24d9e6516825edb
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Wed Mar 24 14:59:20 2010 +0000

    uxa: After filling the alpha channel xrgb src is compatible with argb dst.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/uxa/uxa-render.c b/uxa/uxa-render.c
index bcfe20e..30934d0 100644
--- a/uxa/uxa-render.c
+++ b/uxa/uxa-render.c
@@ -963,6 +963,10 @@ compatible_formats (CARD8 op, PicturePtr dst, PicturePtr src)
 
 		if (src->format == PICT_a8b8g8r8 && dst->format == PICT_x8b8g8r8)
 			return 1;
+
+		/* xrgb is promoted to argb during image upload... */
+		if (dst->format == PICT_a8r8g8b8 && src->format == PICT_x8r8g8b8)
+			return 1;
 	} else if (op == PictOpOver) {
 		if (src->alphaMap || dst->alphaMap)
 			return 0;
commit 90a971c60769781f53827b469a9be3aab14cf71c
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Wed Mar 24 14:50:45 2010 +0000

    uxa: Only reduce a composite to a BLT if it is wholly contained
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/uxa/uxa-render.c b/uxa/uxa-render.c
index ca46a2a..bcfe20e 100644
--- a/uxa/uxa-render.c
+++ b/uxa/uxa-render.c
@@ -977,6 +977,21 @@ compatible_formats (CARD8 op, PicturePtr dst, PicturePtr src)
 	return 0;
 }
 
+static int
+drawable_contains (DrawablePtr drawable, int x1, int y1, int x2, int y2)
+{
+	if (x1 < 0 || y1 < 0)
+		return FALSE;
+
+	if (x2 > drawable->width)
+		return FALSE;
+
+	if (y2 > drawable->height)
+		return FALSE;
+
+	return TRUE;
+}
+
 void
 uxa_composite(CARD8 op,
 	      PicturePtr pSrc,
@@ -1026,7 +1041,8 @@ uxa_composite(CARD8 op,
 								width, height);
 				if (ret == 1)
 					goto done;
-			} else if (!pSrc->repeat && !pSrc->transform) {
+			} else if (!pSrc->repeat && !pSrc->transform &&
+				   drawable_contains(pSrc->pDrawable, xSrc, ySrc, xSrc + width, ySrc + height)) {
 				xDst += pDst->pDrawable->x;
 				yDst += pDst->pDrawable->y;
 				xSrc += pSrc->pDrawable->x;
commit 2eec53d0b9232970fe3d03ce6c8940ebeea44bee
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Mar 23 17:28:22 2010 +0000

    uxa: Default to using TILING_X for pixmaps.
    
    On memory constrained hardware, tiling is vital for good performance as
    it minimizes cache misses.  The downside is that for older hardware
    (which often suffers from the lack of bandwidth) requires the use of
    fences for many operations, which are in short supply and so may cause
    shorter batchbuffers. However our batch buffers are typically short and
    so this is unlikely to be a concern and not affect the performance wins.
    
    A quick bit of testing suggests the effect is inconclusive on
    firefox/i945:
                      linear            tiled
      xcb             205.470           206.219
      xcb-render-0.0  404.704           388.413
      xlib            166.410           170.805
    
    A secondary effect of the patch is to workaround a G31 specific hang
    when attempting to use linear 2048x2048 surfaces. Bonus!
    
    Fixes:
      Bug 25375 - Performance issue using texture from pixmap (tfp) glx extension on 945
      http://bugs.freedesktop.org/show_bug.cgi?id=25375
    
      Bug 27100 - GPU Hung copying a 2048x1152 pixmap
      http://bugs.freedesktop.org/show_bug.cgi?id=27100
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
    Tested-by: John <jvinla at gmail.com>

diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index fec5378..22792fe 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -135,8 +135,20 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap,
 		pitch_align = intel->accel_pixmap_pitch_alignment;
 		size = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
 				pitch_align) * ALIGN (h, 2);
-		if (size < 4096)
+		if (!IS_I965G(intel)) {
+			/* Older hardware requires fences to be pot size
+			 * aligned with a minimum of 1 MiB, so causes
+			 * massive overallocation for small textures.
+			 */
+			if (size < 1024*1024/2)
+				*tiling = I915_TILING_NONE;
+		} else if (size <= 4096) {
+			/* Disable tiling beneath a page size, we will not see
+			 * any benefit from reducing TLB misses and instead
+			 * just incur extra cost when we require a fence.
+			 */
 			*tiling = I915_TILING_NONE;
+		}
 	}
 
   repeat:
@@ -863,11 +875,14 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
 			return NullPixmap;
 		}
 
-		if (usage == INTEL_CREATE_PIXMAP_TILING_X)
-			priv->tiling = I915_TILING_X;
-		else if (usage == INTEL_CREATE_PIXMAP_TILING_Y)
+		/* Always attempt to tile, compute_size() will remove the
+		 * tiling for pixmaps that are either too large or too small
+		 * to be effectively tiled.
+		 */
+		priv->tiling = I915_TILING_X;
+		if (usage == INTEL_CREATE_PIXMAP_TILING_Y)
 			priv->tiling = I915_TILING_Y;
-		else
+		if (usage == UXA_CREATE_PIXMAP_FOR_MAP)
 			priv->tiling = I915_TILING_NONE;
 
 		size = i830_uxa_pixmap_compute_size(pixmap, w, h,