xf86-video-intel: 2 commits - src/i830_batchbuffer.c src/i965_render.c

[Chris Wilson]

 src/i830_batchbuffer.c |    2 +-
 src/i965_render.c      |   16 ++++++++++++----
 2 files changed, 13 insertions(+), 5 deletions(-)

New commits:
commit 0203cf91b54ee8a7cea8560e559288ee9b6e8554
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Mon Jun 21 22:25:08 2010 +0100

    Do not clear need_mi_flush within the batch.
    
    This is a situation that should not be possible, need_mi_flush being
    true but the list of pending flush pixmaps being clear. However, an
    earlier bug in doing just that revealed this minor bug. So for
    correctness, be careful not to clear need_mi_flush without emitting a
    MI_FLUSH.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/i830_batchbuffer.c b/src/i830_batchbuffer.c
index b2ee639..2b7227b 100644
--- a/src/i830_batchbuffer.c
+++ b/src/i830_batchbuffer.c
@@ -223,7 +223,7 @@ void intel_batch_submit(ScrnInfoPtr scrn, int flush)
 		list_del(&entry->batch);
 	}
 
-	intel->need_mi_flush = !list_is_empty(&intel->flush_pixmaps);
+	intel->need_mi_flush |= !list_is_empty(&intel->flush_pixmaps);
 	while (!list_is_empty(&intel->flush_pixmaps))
 		list_del(intel->flush_pixmaps.next);
 
commit 5107b6fa26ecfdbdd60b869a86765c9c484db3a2
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Mon Jun 21 22:21:58 2010 +0100

    i965: Mark the render target as dirty within composite_setup()
    
    The key difference between i965 and earlier, is that the surfaces passed
    to the samplers through an indirect table and so the batch and render
    target was not being marked dirty by the relocation (since the
    relocation only happens within prepare_composite() which may have been
    in another batch.) Simply call intel_pixmap_mark_dirty() when binding
    the sampler table into the batch to ensure that the dirty is tracked
    appropriately.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/i965_render.c b/src/i965_render.c
index 7328b6c..e5b0916 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1160,6 +1160,12 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 	IntelEmitInvarientState(scrn);
 	intel->last_3d = LAST_3D_RENDER;
 
+	/* Mark the destination dirty within this batch */
+	intel_batch_mark_pixmap_domains(intel,
+					i830_uxa_get_pixmap_intel(dest_picture),
+					I915_GEM_DOMAIN_RENDER,
+					I915_GEM_DOMAIN_RENDER);
+
 	urb_vs_start = 0;
 	urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
 	urb_gs_start = urb_vs_start + urb_vs_size;
@@ -1544,6 +1550,12 @@ i965_prepare_composite(int op, PicturePtr source_picture,
 		composite_op->mask_extend = SAMPLER_STATE_EXTEND_NONE;
 	}
 
+	/* Flush any pending writes prior to relocating the textures. */
+	if(i830_uxa_pixmap_is_dirty(source) ||
+	   (mask && i830_uxa_pixmap_is_dirty(mask)))
+		intel_batch_emit_flush(scrn);
+
+
 	/* Set up the surface states. */
 	surface_state_bo = dri_bo_alloc(intel->bufmgr, "surface_state",
 					3 * sizeof(brw_surface_state_padded),
@@ -1676,10 +1688,6 @@ i965_prepare_composite(int op, PicturePtr source_picture,
 		}
 	}
 
-	if(i830_uxa_pixmap_is_dirty(source) ||
-	   (mask && i830_uxa_pixmap_is_dirty(mask)))
-		intel_batch_emit_flush(scrn);
-
 	intel->needs_render_state_emit = TRUE;
 
 	return TRUE;