xf86-video-intel: 4 commits - src/common.h src/drmmode_display.c src/i830_batchbuffer.h src/i830.h src/i830_memory.c src/i830_uxa.c src/i965_render.c uxa/uxa-glyphs.c
Chris Wilson
ickle at kemper.freedesktop.org
Fri Jan 8 11:26:16 PST 2010
src/common.h | 11 +++++++++++
src/drmmode_display.c | 3 +--
src/i830.h | 14 +-------------
src/i830_batchbuffer.h | 15 +++++++++++++++
src/i830_memory.c | 16 ++++++++++------
src/i830_uxa.c | 26 +++++++++++---------------
src/i965_render.c | 31 +++++++++++++++++++++----------
uxa/uxa-glyphs.c | 4 +++-
8 files changed, 73 insertions(+), 47 deletions(-)
New commits:
commit 4902f546be19e3d5bb47f6c75e2199dc4856c0f4
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sun Dec 13 10:44:12 2009 +0000
i965: Ensure that URB_FENCE is aligned to 64-bytes
The PRM (Vol 1, p32) specifies that the URB_FENCE command must not cross
a cache-line boundary (64-bytes) in order to workaround a silicon issue.
Ensure that it does not by inserting an alignment point before the atomic
section.
This is a slightly too large hammer, but the easiest method to work with
the current BEGIN_BATCH/ADVANCE_BATCH protections.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i830_batchbuffer.h b/src/i830_batchbuffer.h
index 1beba4f..1fc273b 100644
--- a/src/i830_batchbuffer.h
+++ b/src/i830_batchbuffer.h
@@ -80,6 +80,20 @@ static inline void intel_batch_emit_dword(intel_screen_private *intel, uint32_t
intel->batch_used += 4;
}
+static inline void intel_batch_align(intel_screen_private *intel, uint32_t align)
+{
+ uint32_t delta;
+
+ assert(intel->batch_ptr != NULL);
+ assert(align);
+
+ if ((delta = intel->batch_used & (align - 1))) {
+ delta = align - delta;
+ memset (intel->batch_ptr + intel->batch_used, 0, delta);
+ intel->batch_used += delta;
+ }
+}
+
static inline void
intel_batch_emit_reloc(intel_screen_private *intel,
dri_bo * bo,
@@ -132,6 +146,7 @@ intel_batch_emit_reloc_pixmap(intel_screen_private *intel, PixmapPtr pixmap,
delta);
}
+#define ALIGN_BATCH(align) intel_batch_align(intel, align);
#define OUT_BATCH(dword) intel_batch_emit_dword(intel, dword)
#define OUT_RELOC(bo, read_domains, write_domains, delta) \
diff --git a/src/i965_render.c b/src/i965_render.c
index 066901c..7866dd7 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1160,14 +1160,13 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
/* Begin the long sequence of commands needed to set up the 3D
* rendering pipe
*/
- {
- ATOMIC_BATCH(2);
- OUT_BATCH(MI_FLUSH |
- MI_STATE_INSTRUCTION_CACHE_FLUSH |
- BRW_MI_GLOBAL_SNAPSHOT_RESET);
- OUT_BATCH(MI_NOOP);
- ADVANCE_BATCH();
- }
+
+ /* URB fence. Erratum (Vol 1a, p32): URB_FENCE must not cross a
+ * cache-line (64 bytes). Start by aligning this sequence of ops to
+ * a cache-line...
+ */
+ ALIGN_BATCH(64);
+
{
if (IS_IGDNG(intel))
ATOMIC_BATCH(14);
@@ -1175,6 +1174,9 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
ATOMIC_BATCH(12);
/* Match Mesa driver setup */
+ OUT_BATCH(MI_FLUSH |
+ MI_STATE_INSTRUCTION_CACHE_FLUSH |
+ BRW_MI_GLOBAL_SNAPSHOT_RESET);
if (IS_G4X(intel) || IS_IGDNG(intel))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
@@ -1213,9 +1215,9 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
OUT_BATCH(BRW_STATE_SIP | 0);
OUT_RELOC(render_state->sip_kernel_bo,
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
- OUT_BATCH(MI_NOOP);
ADVANCE_BATCH();
}
+
{
int pipe_ctrl;
ATOMIC_BATCH(26);
@@ -1279,7 +1281,16 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
offsetof(struct gen4_cc_unit_state,
cc_state[src_blend][dst_blend]));
- /* URB fence */
+ /* URB fence. Erratum (Vol 1a, p32): URB_FENCE must not cross a
+ * cache-line (64 bytes).
+ *
+ * 21 preceding dwords since start of section: 84 bytes.
+ * 12 bytes for URB_FENCE, implies that the end-of-instruction
+ * does not cross the cache-line boundary...
+ *
+ * A total of 33 or 35 dwords since alignment: 132, 140 bytes.
+ * Again, the URB_FENCE will not cross a cache-line.
+ */
OUT_BATCH(BRW_URB_FENCE |
UF0_CS_REALLOC |
UF0_SF_REALLOC |
commit 83626aba357ffb4dd7931daaf163c1dd1d08f9d3
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sun Nov 29 21:39:41 2009 +0000
uxa-glyphs: Enable TILING_X on glyph caches.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/common.h b/src/common.h
index b9269b5..3169cdf 100644
--- a/src/common.h
+++ b/src/common.h
@@ -389,4 +389,15 @@ extern int I810_DEBUG;
struct pci_device *
intel_host_bridge (void);
+/**
+ * Hints to CreatePixmap to tell the driver how the pixmap is going to be
+ * used.
+ *
+ * Compare to CREATE_PIXMAP_USAGE_* in the server.
+ */
+enum {
+ INTEL_CREATE_PIXMAP_TILING_X = 0x10000000,
+ INTEL_CREATE_PIXMAP_TILING_Y,
+};
+
#endif /* _INTEL_COMMON_H_ */
diff --git a/src/i830.h b/src/i830.h
index 098ea05..4aba2f7 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -599,17 +599,6 @@ extern const int I830CopyROP[16];
#define ALLOW_SHARING 0x00000010
#define DISABLE_REUSE 0x00000020
-/**
- * Hints to CreatePixmap to tell the driver how the pixmap is going to be
- * used.
- *
- * Compare to CREATE_PIXMAP_USAGE_* in the server.
- */
-enum {
- INTEL_CREATE_PIXMAP_TILING_X = 0x10000000,
- INTEL_CREATE_PIXMAP_TILING_Y,
-};
-
void i830_debug_flush(ScrnInfoPtr scrn);
static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable)
diff --git a/uxa/uxa-glyphs.c b/uxa/uxa-glyphs.c
index ff16781..5c23321 100644
--- a/uxa/uxa-glyphs.c
+++ b/uxa/uxa-glyphs.c
@@ -47,6 +47,7 @@
#include <stdlib.h>
#include "uxa-priv.h"
+#include "../src/common.h"
#include "mipict.h"
@@ -189,7 +190,8 @@ static Bool uxa_realize_glyph_caches(ScreenPtr pScreen, unsigned int format)
pPixmap = (*pScreen->CreatePixmap) (pScreen,
CACHE_PICTURE_WIDTH,
- height, depth, 0);
+ height, depth,
+ INTEL_CREATE_PIXMAP_TILING_X);
if (!pPixmap)
return FALSE;
commit 50e07da8094c8c8c593b6eb8c41fc42444851d04
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sun Dec 13 09:35:36 2009 +0000
i830: Do not use vtSema when chosing mapping type.
The mapping type to use is determined by the tiling of the underlying
object, not by whether or not not we control the vt. This was a
left-over wart that was intended to mean that we had GEM and so could
use GTT mappings.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index 9c381f3..4a892b5 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -575,8 +575,7 @@ static Bool i830_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access)
(access == UXA_ACCESS_RW || priv->batch_write_domain))
intel_batch_submit(scrn);
- /* No VT sema or GEM? No GTT mapping. */
- if (!scrn->vtSema || bo->size > intel->max_gtt_map_size) {
+ if (bo->size > intel->max_gtt_map_size) {
ret = dri_bo_map(bo, access == UXA_ACCESS_RW);
if (ret != 0) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
@@ -604,22 +603,19 @@ static Bool i830_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access)
static void i830_uxa_finish_access(PixmapPtr pixmap)
{
dri_bo *bo = i830_get_pixmap_bo(pixmap);
+ ScreenPtr screen = pixmap->drawable.pScreen;
+ ScrnInfoPtr scrn = xf86Screens[screen->myNum];
+ intel_screen_private *intel = intel_get_screen_private(scrn);
- if (bo) {
- ScreenPtr screen = pixmap->drawable.pScreen;
- ScrnInfoPtr scrn = xf86Screens[screen->myNum];
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- if (bo == intel->front_buffer->bo)
- intel->need_flush = TRUE;
+ if (bo == intel->front_buffer->bo)
+ intel->need_flush = TRUE;
- if (!scrn->vtSema || bo->size > intel->max_gtt_map_size)
- dri_bo_unmap(bo);
- else
- drm_intel_gem_bo_unmap_gtt(bo);
+ if (bo->size > intel->max_gtt_map_size)
+ dri_bo_unmap(bo);
+ else
+ drm_intel_gem_bo_unmap_gtt(bo);
- pixmap->devPrivate.ptr = NULL;
- }
+ pixmap->devPrivate.ptr = NULL;
}
static Bool
commit 7a2b7cfab5cdef277f0feb838683422d9fcb0db3
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sun Dec 13 09:33:45 2009 +0000
Consolidate determining maximum sizes for use with GEM
Add a small wrapper function so that the callsites need only call the
single function when checking the available aperture size for
determining the maximum viable size for operations. This will allow us
to easily extend this set in the future by only needing to adding the
check to a single location.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index a469f6c..b1dee76 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -395,8 +395,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
drmmode_output_dpms(output, DPMSModeOn);
}
- i830_set_max_gtt_map_size(scrn);
- i830_set_max_tiling_size(scrn);
+ i830_set_gem_max_sizes(scrn);
if (scrn->pScreen)
xf86_reload_cursors(scrn->pScreen);
diff --git a/src/i830.h b/src/i830.h
index a66038a..098ea05 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -466,8 +466,7 @@ Bool i830_bind_all_memory(ScrnInfoPtr scrn);
unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long size);
unsigned long i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
uint32_t tiling_mode);
-void i830_set_max_gtt_map_size(ScrnInfoPtr scrn);
-void i830_set_max_tiling_size(ScrnInfoPtr scrn);
+void i830_set_gem_max_sizes(ScrnInfoPtr scrn);
i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn);
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 7abea72..79c9fa7 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -523,8 +523,7 @@ i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn)
return NULL;
}
- i830_set_max_gtt_map_size(scrn);
- i830_set_max_tiling_size(scrn);
+ i830_set_gem_max_sizes(scrn);
return front_buffer;
}
@@ -594,8 +593,7 @@ Bool i830_bind_all_memory(ScrnInfoPtr scrn)
drmmode_crtc_set_cursor_bo(xf86_config->crtc[i],
intel->cursor_mem_argb[i]->bo);
- i830_set_max_gtt_map_size(scrn);
- i830_set_max_tiling_size(scrn);
+ i830_set_gem_max_sizes(scrn);
if (intel->front_buffer)
scrn->fbOffset = intel->front_buffer->offset;
@@ -644,7 +642,7 @@ void i830_free_xvmc_buffer(ScrnInfoPtr scrn, i830_memory * buffer)
#endif
-void i830_set_max_gtt_map_size(ScrnInfoPtr scrn)
+static void i830_set_max_gtt_map_size(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
struct drm_i915_gem_get_aperture aperture;
@@ -665,7 +663,7 @@ void i830_set_max_gtt_map_size(ScrnInfoPtr scrn)
}
}
-void i830_set_max_tiling_size(ScrnInfoPtr scrn)
+static void i830_set_max_tiling_size(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
struct drm_i915_gem_get_aperture aperture;
@@ -685,3 +683,9 @@ void i830_set_max_tiling_size(ScrnInfoPtr scrn)
intel->max_tiling_size /= 2;
}
}
+
+void i830_set_gem_max_sizes(ScrnInfoPtr scrn)
+{
+ i830_set_max_gtt_map_size(scrn);
+ i830_set_max_tiling_size(scrn);
+}
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