xf86-video-ati: Branch 'master'

[Alex Deucher]

 src/r6xx_accel.c |    4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

New commits:
commit 76eea5e02776f7beeb8f4491a374bd36792eda92
Author: Alex Deucher <alexdeucher at gmail.com>
Date:   Thu Feb 4 10:52:14 2010 -0500

    r600: reduce number of cache flushes
    
    We don't need to flush so often. Next step
    would be to move the flushing to the drm and only
    flush after each command buffer rather than each
    draw.

diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 7a225e5..c0be4d5 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -159,7 +159,6 @@ start_3d(ScrnInfoPtr pScrn, drmBufPtr ib)
     E32(ib, 0x80000000);
     END_BATCH();
 
-    wait_3d_idle_clean (pScrn, ib);
 }
 
 /*
@@ -1279,6 +1278,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
 
     draw_auto(pScrn, accel_state->ib, &draw_conf);
 
+    /* XXX drm should handle this in fence submit */
     wait_3d_idle_clean(pScrn, accel_state->ib);
 
     /* sync dst surface */
@@ -1286,8 +1286,6 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
 			accel_state->dst_size, accel_state->dst_mc_addr,
 			accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0);
 
-    wait_3d_idle_clean(pScrn, accel_state->ib);
-
     accel_state->vb_start_op = -1;
     accel_state->ib_reset_op = 0;