xf86-video-ati: Branch 'master' - 10 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Feb 1 09:23:46 PST 2010
src/AtomBios/includes/atombios.h | 1090 +++++++++++++++++++++++++++++++++-----
src/ati_pciids_gen.h | 35 +
src/atombios_crtc.c | 373 ++++++++++++-
src/atombios_output.c | 233 +++++++-
src/pcidb/ati_pciids.csv | 35 +
src/radeon.h | 9
src/radeon_atombios.c | 66 ++
src/radeon_chipinfo_gen.h | 35 +
src/radeon_chipset_gen.h | 35 +
src/radeon_crtc.c | 127 +++-
src/radeon_cursor.c | 68 ++
src/radeon_driver.c | 114 +++
src/radeon_output.c | 17
src/radeon_pci_chipset_gen.h | 35 +
src/radeon_pci_device_match_gen.h | 35 +
src/radeon_probe.h | 6
src/radeon_reg.h | 149 +++++
17 files changed, 2240 insertions(+), 222 deletions(-)
New commits:
commit a887818f491f6c7315c56c4e0d0b702c4c6aa4ac
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Feb 1 11:01:47 2010 -0500
evergreen: add pci ids
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 3f9691e..3dd36da 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -453,3 +453,38 @@
#define PCI_CHIP_RS880_9712 0x9712
#define PCI_CHIP_RS880_9713 0x9713
#define PCI_CHIP_RS880_9714 0x9714
+#define PCI_CHIP_CYPRESS_6880 0x6880
+#define PCI_CHIP_CYPRESS_6888 0x6888
+#define PCI_CHIP_CYPRESS_6889 0x6889
+#define PCI_CHIP_CYPRESS_688A 0x688A
+#define PCI_CHIP_CYPRESS_6898 0x6898
+#define PCI_CHIP_CYPRESS_6899 0x6899
+#define PCI_CHIP_CYPRESS_689E 0x689E
+#define PCI_CHIP_HEMLOCK_689C 0x689C
+#define PCI_CHIP_HEMLOCK_689D 0x689D
+#define PCI_CHIP_JUNIPER_68A0 0x68A0
+#define PCI_CHIP_JUNIPER_68A1 0x68A1
+#define PCI_CHIP_JUNIPER_68A8 0x68A8
+#define PCI_CHIP_JUNIPER_68A9 0x68A9
+#define PCI_CHIP_JUNIPER_68B0 0x68B0
+#define PCI_CHIP_JUNIPER_68B8 0x68B8
+#define PCI_CHIP_JUNIPER_68B9 0x68B9
+#define PCI_CHIP_JUNIPER_68BE 0x68BE
+#define PCI_CHIP_REDWOOD_68C0 0x68C0
+#define PCI_CHIP_REDWOOD_68C1 0x68C1
+#define PCI_CHIP_REDWOOD_68C8 0x68C8
+#define PCI_CHIP_REDWOOD_68C9 0x68C9
+#define PCI_CHIP_REDWOOD_68D8 0x68D8
+#define PCI_CHIP_REDWOOD_68D9 0x68D9
+#define PCI_CHIP_REDWOOD_68DA 0x68DA
+#define PCI_CHIP_REDWOOD_68DE 0x68DE
+#define PCI_CHIP_CEDAR_68E0 0x68E0
+#define PCI_CHIP_CEDAR_68E1 0x68E1
+#define PCI_CHIP_CEDAR_68E4 0x68E4
+#define PCI_CHIP_CEDAR_68E5 0x68E5
+#define PCI_CHIP_CEDAR_68E8 0x68E8
+#define PCI_CHIP_CEDAR_68E9 0x68E9
+#define PCI_CHIP_CEDAR_68F1 0x68F1
+#define PCI_CHIP_CEDAR_68F8 0x68F8
+#define PCI_CHIP_CEDAR_68F9 0x68F9
+#define PCI_CHIP_CEDAR_68FE 0x68FE
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 695d9a6..9c72c40 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -454,3 +454,38 @@
"0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD 4200"
"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon 4100"
"0x9714","RS880_9714","RS880",,1,,,1,"ATI RS880"
+"0x6880","CYPRESS_6880","CYPRESS",1,,,,,"CYPRESS"
+"0x6888","CYPRESS_6888","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x6889","CYPRESS_6889","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x688A","CYPRESS_688A","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x6898","CYPRESS_6898","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
+"0x6899","CYPRESS_6899","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
+"0x689E","CYPRESS_689E","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
+"0x689C","HEMLOCK_689C","HEMLOCK",,,,,,"ATI Radeon HD 5900 Series"
+"0x689D","HEMLOCK_689D","HEMLOCK",,,,,,"ATI Radeon HD 5900 Series"
+"0x68A0","JUNIPER_68A0","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series"
+"0x68A1","JUNIPER_68A1","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series"
+"0x68A8","JUNIPER_68A8","JUNIPER",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68A9","JUNIPER_68A9","JUNIPER",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68B0","JUNIPER_68B0","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series"
+"0x68B8","JUNIPER_68B8","JUNIPER",,,,,,"ATI Radeon HD 5700 Series"
+"0x68B9","JUNIPER_68B9","JUNIPER",,,,,,"ATI Radeon HD 5700 Series"
+"0x68BE","JUNIPER_68BE","JUNIPER",,,,,,"ATI Radeon HD 5700 Series"
+"0x68C0","REDWOOD_68C0","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5000 Series"
+"0x68C1","REDWOOD_68C1","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5000 Series"
+"0x68C8","REDWOOD_68C8","REDWOOD",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68C9","REDWOOD_68C9","REDWOOD",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68D8","REDWOOD_68D8","REDWOOD",,,,,,"ATI Radeon HD 5670"
+"0x68D9","REDWOOD_68D9","REDWOOD",,,,,,"ATI Radeon HD 5570"
+"0x68DA","REDWOOD_68DA","REDWOOD",,,,,,"ATI Radeon HD 5500 Series"
+"0x68DE","REDWOOD_68DE","REDWOOD",,,,,,"REDWOOD"
+"0x68E0","CEDAR_68E0","CEDAR",1,,,,,"ATI Mobility Radeon HD 5000 Series"
+"0x68E1","CEDAR_68E1","CEDAR",1,,,,,"ATI Mobility Radeon HD 5000 Series"
+"0x68E4","CEDAR_68E4","CEDAR",1,,,,,"CEDAR"
+"0x68E5","CEDAR_68E5","CEDAR",1,,,,,"CEDAR"
+"0x68E8","CEDAR_68E8","CEDAR",,,,,,"CEDAR"
+"0x68E9","CEDAR_68E9","CEDAR",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68F1","CEDAR_68F1","CEDAR",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68F8","CEDAR_68F8","CEDAR",,,,,,"CEDAR"
+"0x68F9","CEDAR_68F9","CEDAR",,,,,,"ATI Radeon HD 5450"
+"0x68FE","CEDAR_68FE","CEDAR",,,,,,"CEDAR"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index 41144c7..bdbd358 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -373,4 +373,39 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9712, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
{ 0x9713, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
{ 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
+ { 0x6880, CHIP_FAMILY_CYPRESS, 1, 0, 0, 0, 0 },
+ { 0x6888, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x6889, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x688A, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x6898, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x6899, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x689E, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x689C, CHIP_FAMILY_HEMLOCK, 0, 0, 0, 0, 0 },
+ { 0x689D, CHIP_FAMILY_HEMLOCK, 0, 0, 0, 0, 0 },
+ { 0x68A0, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 },
+ { 0x68A1, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 },
+ { 0x68A8, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68A9, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68B0, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 },
+ { 0x68B8, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68B9, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68BE, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68C0, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 },
+ { 0x68C1, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 },
+ { 0x68C8, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68C9, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68D8, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68D9, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68DA, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68DE, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68E0, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
+ { 0x68E1, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
+ { 0x68E4, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
+ { 0x68E5, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
+ { 0x68E8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68E9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68F1, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68F8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68F9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68FE, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index fc41c3d..da0d3b4 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -373,5 +373,40 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RS880_9712, "ATI Mobility Radeon HD 4200" },
{ PCI_CHIP_RS880_9713, "ATI Mobility Radeon 4100" },
{ PCI_CHIP_RS880_9714, "ATI RS880" },
+ { PCI_CHIP_CYPRESS_6880, "CYPRESS" },
+ { PCI_CHIP_CYPRESS_6888, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CYPRESS_6889, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CYPRESS_688A, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CYPRESS_6898, "ATI Radeon HD 5800 Series" },
+ { PCI_CHIP_CYPRESS_6899, "ATI Radeon HD 5800 Series" },
+ { PCI_CHIP_CYPRESS_689E, "ATI Radeon HD 5800 Series" },
+ { PCI_CHIP_HEMLOCK_689C, "ATI Radeon HD 5900 Series" },
+ { PCI_CHIP_HEMLOCK_689D, "ATI Radeon HD 5900 Series" },
+ { PCI_CHIP_JUNIPER_68A0, "ATI Mobility Radeon HD 5800 Series" },
+ { PCI_CHIP_JUNIPER_68A1, "ATI Mobility Radeon HD 5800 Series" },
+ { PCI_CHIP_JUNIPER_68A8, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_JUNIPER_68A9, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_JUNIPER_68B0, "ATI Mobility Radeon HD 5800 Series" },
+ { PCI_CHIP_JUNIPER_68B8, "ATI Radeon HD 5700 Series" },
+ { PCI_CHIP_JUNIPER_68B9, "ATI Radeon HD 5700 Series" },
+ { PCI_CHIP_JUNIPER_68BE, "ATI Radeon HD 5700 Series" },
+ { PCI_CHIP_REDWOOD_68C0, "ATI Mobility Radeon HD 5000 Series" },
+ { PCI_CHIP_REDWOOD_68C1, "ATI Mobility Radeon HD 5000 Series" },
+ { PCI_CHIP_REDWOOD_68C8, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_REDWOOD_68C9, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_REDWOOD_68D8, "ATI Radeon HD 5670" },
+ { PCI_CHIP_REDWOOD_68D9, "ATI Radeon HD 5570" },
+ { PCI_CHIP_REDWOOD_68DA, "ATI Radeon HD 5500 Series" },
+ { PCI_CHIP_REDWOOD_68DE, "REDWOOD" },
+ { PCI_CHIP_CEDAR_68E0, "ATI Mobility Radeon HD 5000 Series" },
+ { PCI_CHIP_CEDAR_68E1, "ATI Mobility Radeon HD 5000 Series" },
+ { PCI_CHIP_CEDAR_68E4, "CEDAR" },
+ { PCI_CHIP_CEDAR_68E5, "CEDAR" },
+ { PCI_CHIP_CEDAR_68E8, "CEDAR" },
+ { PCI_CHIP_CEDAR_68E9, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CEDAR_68F1, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CEDAR_68F8, "CEDAR" },
+ { PCI_CHIP_CEDAR_68F9, "ATI Radeon HD 5450" },
+ { PCI_CHIP_CEDAR_68FE, "CEDAR" },
{ -1, NULL }
};
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 1b85dcc..1f1b97e 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -373,5 +373,40 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RS880_9712, PCI_CHIP_RS880_9712, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9713, PCI_CHIP_RS880_9713, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9714, PCI_CHIP_RS880_9714, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6880, PCI_CHIP_CYPRESS_6880, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6888, PCI_CHIP_CYPRESS_6888, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6889, PCI_CHIP_CYPRESS_6889, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_688A, PCI_CHIP_CYPRESS_688A, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6898, PCI_CHIP_CYPRESS_6898, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6899, PCI_CHIP_CYPRESS_6899, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_689E, PCI_CHIP_CYPRESS_689E, RES_SHARED_VGA },
+ { PCI_CHIP_HEMLOCK_689C, PCI_CHIP_HEMLOCK_689C, RES_SHARED_VGA },
+ { PCI_CHIP_HEMLOCK_689D, PCI_CHIP_HEMLOCK_689D, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68A0, PCI_CHIP_JUNIPER_68A0, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68A1, PCI_CHIP_JUNIPER_68A1, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68A8, PCI_CHIP_JUNIPER_68A8, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68A9, PCI_CHIP_JUNIPER_68A9, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68B0, PCI_CHIP_JUNIPER_68B0, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68B8, PCI_CHIP_JUNIPER_68B8, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68B9, PCI_CHIP_JUNIPER_68B9, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68BE, PCI_CHIP_JUNIPER_68BE, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68C0, PCI_CHIP_REDWOOD_68C0, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68C1, PCI_CHIP_REDWOOD_68C1, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68C8, PCI_CHIP_REDWOOD_68C8, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68C9, PCI_CHIP_REDWOOD_68C9, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68D8, PCI_CHIP_REDWOOD_68D8, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68D9, PCI_CHIP_REDWOOD_68D9, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68DA, PCI_CHIP_REDWOOD_68DA, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68DE, PCI_CHIP_REDWOOD_68DE, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E0, PCI_CHIP_CEDAR_68E0, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E1, PCI_CHIP_CEDAR_68E1, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E4, PCI_CHIP_CEDAR_68E4, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E5, PCI_CHIP_CEDAR_68E5, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E8, PCI_CHIP_CEDAR_68E8, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E9, PCI_CHIP_CEDAR_68E9, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68F1, PCI_CHIP_CEDAR_68F1, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68F8, PCI_CHIP_CEDAR_68F8, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68F9, PCI_CHIP_CEDAR_68F9, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68FE, PCI_CHIP_CEDAR_68FE, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 64127bd..fa44875 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -373,5 +373,40 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9712, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9713, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6880, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6888, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6889, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_688A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6898, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6899, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_689E, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HEMLOCK_689C, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HEMLOCK_689D, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68BE, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68D8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68D9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68DA, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68DE, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E4, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E5, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68FE, 0 ),
{ 0, 0, 0 }
};
commit cb2772b69480268c059766c4f6b209ce590ede0e
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Jan 29 12:59:46 2010 -0500
evergreen: add atombios crtc/pll functions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index f832374..4044202 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -290,7 +290,146 @@ atombios_set_crtc_dtd_timing(xf86CrtcPtr crtc, DisplayModePtr mode)
return ATOM_NOT_IMPLEMENTED;
}
-void
+static void
+atombios_pick_pll(xf86CrtcPtr crtc)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
+ xf86OutputPtr output;
+ RADEONOutputPrivatePtr radeon_output;
+ int o, c;
+ uint32_t pll_use_mask = 0;
+ Bool is_dp = FALSE;
+
+ if (IS_DCE4_VARIANT) {
+ for (o = 0; o < xf86_config->num_output; o++) {
+ output = xf86_config->output[o];
+ if (output->crtc == crtc) {
+ int mode = atombios_get_encoder_mode(output);
+ radeon_output = output->driver_private;
+
+ if (mode == ATOM_ENCODER_MODE_DP) {
+ is_dp = TRUE;
+ break;
+ } else {
+ for (c = 0; c < xf86_config->num_crtc; c++) {
+ xf86CrtcPtr test_crtc = xf86_config->crtc[c];
+ RADEONCrtcPrivatePtr radeon_test_crtc = test_crtc->driver_private;
+
+ if (crtc != test_crtc && (radeon_test_crtc->pll_id >= 0))
+ pll_use_mask |= (1 << radeon_test_crtc->pll_id);
+
+ }
+ }
+ }
+ }
+ if (is_dp)
+ radeon_crtc->pll_id = 2;
+ else if (!(pll_use_mask & 1))
+ radeon_crtc->pll_id = 0;
+ else
+ radeon_crtc->pll_id = 1;
+ } else
+ radeon_crtc->pll_id = radeon_crtc->crtc_id;
+
+ ErrorF("Picked PLL %d\n", radeon_crtc->pll_id);
+
+ for (o = 0; o < xf86_config->num_output; o++) {
+ output = xf86_config->output[o];
+ if (output->crtc == crtc) {
+ radeon_output = output->driver_private;
+ radeon_output->pll_id = radeon_crtc->pll_id;
+ }
+ }
+}
+
+static void
+atombios_crtc_set_dcpll(xf86CrtcPtr crtc)
+{
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
+ xf86OutputPtr output = NULL;
+ RADEONOutputPrivatePtr radeon_output = NULL;
+ radeon_encoder_ptr radeon_encoder = NULL;
+ int index;
+ int major, minor, i;
+ PIXEL_CLOCK_PARAMETERS_V5 args;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ memset(&args, 0, sizeof(args));
+
+ for (i = 0; i < xf86_config->num_output; i++) {
+ output = xf86_config->output[i];
+ if (output->crtc == crtc) {
+ radeon_output = output->driver_private;
+ radeon_encoder = radeon_get_encoder(output);
+ break;
+ }
+ }
+
+ if (radeon_output == NULL) {
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "No output assigned to crtc!\n");
+ return;
+ }
+
+ if (radeon_encoder == NULL) {
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "No encoder assigned to output!\n");
+ return;
+ }
+
+ index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ /*ErrorF("table is %d %d\n", major, minor);*/
+ switch(major) {
+ case 1:
+ switch(minor) {
+ case 5:
+ args.ucCRTC = ATOM_CRTC_INVALID;
+ args.usPixelClock = 60000; // 600 Mhz
+ args.ucPostDiv = info->pll.pll_out_max / 60000;
+ if (info->pll.reference_freq == 10000) {
+ // 100 Mhz ref clock
+ args.ucRefDiv = 7;
+ args.usFbDiv = cpu_to_le16(84);
+ args.ulFbDivDecFrac = cpu_to_le32(0);
+ } else {
+ // 27 Mhz ref clock
+ args.ucRefDiv = 2;
+ args.usFbDiv = cpu_to_le16(88);
+ args.ulFbDivDecFrac = cpu_to_le32(888889);
+ }
+ args.ucPpll = ATOM_DCPLL;
+ args.ucMiscInfo = 0; //HDMI depth
+ args.ucTransmitterID = radeon_encoder->encoder_id;
+ args.ucEncoderMode = atombios_get_encoder_mode(output);
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &args;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set DCPLL success\n");
+ return;
+ }
+
+ ErrorF("Set DCPLL failed\n");
+ return;
+}
+
+static void
atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
@@ -304,15 +443,18 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
+ PIXEL_CLOCK_PARAMETERS_V5 *spc5_ptr;
xf86OutputPtr output = NULL;
RADEONOutputPrivatePtr radeon_output = NULL;
radeon_encoder_ptr radeon_encoder = NULL;
int pll_flags = 0;
uint32_t temp;
- void *ptr;
AtomBiosArgRec data;
unsigned char *space;
+ if (IS_DCE4_VARIANT)
+ atombios_crtc_set_dcpll(crtc);
+
memset(&spc_param, 0, sizeof(spc_param));
if (IS_AVIVO_VARIANT) {
if ((info->ChipFamily == CHIP_FAMILY_RS600) ||
@@ -338,12 +480,23 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
}
/* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
- if (radeon_crtc->crtc_id == 0) {
- temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
- OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ if (IS_DCE4_VARIANT) {
+ /* XXX 6 crtcs, but only 2 plls */
+ if (radeon_crtc->crtc_id == 0) {
+ temp = INREG(EVERGREEN_P1PLL_SS_CNTL);
+ OUTREG(EVERGREEN_P1PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN);
+ } else {
+ temp = INREG(EVERGREEN_P2PLL_SS_CNTL);
+ OUTREG(EVERGREEN_P2PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN);
+ }
} else {
- temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
- OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ if (radeon_crtc->crtc_id == 0) {
+ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ } else {
+ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ }
}
} else {
pll_flags |= RADEON_PLL_LEGACY;
@@ -369,7 +522,8 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
if (IS_DCE3_VARIANT) {
ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_param;
- index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
+ ADJUST_DISPLAY_PLL_PS_ALLOCATION *adp_ptr;
+ ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 *adp3_ptr;
/* Can't really do cloning easily on DCE3 cards */
for (i = 0; i < xf86_config->num_output; i++) {
@@ -377,6 +531,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
if (output->crtc == crtc) {
radeon_output = output->driver_private;
radeon_encoder = radeon_get_encoder(output);
+ /* no need to set pll for DP */
+ if (IS_DCE4_VARIANT) {
+ if (atombios_get_encoder_mode(output) == ATOM_ENCODER_MODE_DP)
+ return;
+ }
break;
}
}
@@ -392,19 +551,67 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
}
memset(&adjust_pll_param, 0, sizeof(adjust_pll_param));
- adjust_pll_param.usPixelClock = cpu_to_le16(sclock / 10);
- adjust_pll_param.ucTransmitterID = radeon_encoder->encoder_id;
- adjust_pll_param.ucEncodeMode = atombios_get_encoder_mode(output);
+
+ index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
data.exec.index = index;
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &adjust_pll_param;
- ErrorF("before %d\n", adjust_pll_param.usPixelClock);
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- sclock = le16_to_cpu(adjust_pll_param.usPixelClock) * 10;
+ switch(major) {
+ case 1:
+ switch(minor) {
+ case 1:
+ case 2:
+ adp_ptr = (ADJUST_DISPLAY_PLL_PS_ALLOCATION*)&adjust_pll_param.usPixelClock;
+ adp_ptr->usPixelClock = cpu_to_le16(sclock / 10);
+ adp_ptr->ucTransmitterID = radeon_encoder->encoder_id;
+ adp_ptr->ucEncodeMode = atombios_get_encoder_mode(output);
+
+ ErrorF("before %d\n", adp_ptr->usPixelClock);
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ sclock = le16_to_cpu(adp_ptr->usPixelClock) * 10;
+ }
+ ErrorF("after %d\n", adp_ptr->usPixelClock);
+ break;
+ case 3:
+ adp3_ptr = (ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3*)&adjust_pll_param.usPixelClock;
+ adp3_ptr->sInput.usPixelClock = cpu_to_le16(sclock / 10);
+ adp3_ptr->sInput.ucTransmitterID = radeon_encoder->encoder_id;
+ adp3_ptr->sInput.ucEncodeMode = atombios_get_encoder_mode(output);
+ adp3_ptr->sInput.ucDispPllConfig = 0;
+ if (radeon_output->coherent_mode)
+ adp3_ptr->sInput.ucDispPllConfig |= DISPPLL_CONFIG_COHERENT_MODE;
+ if (sclock > 165000)
+ adp3_ptr->sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK;
+ // if SS
+ // adp3_ptr->sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
+
+ ErrorF("before %d 0x%x\n", adp3_ptr->sInput.usPixelClock, adp3_ptr->sInput.ucDispPllConfig);
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ sclock = adp3_ptr->sOutput.ulDispPllFreq * 10;
+ if (adp3_ptr->sOutput.ucRefDiv) {
+ pll_flags |= RADEON_PLL_USE_REF_DIV;
+ info->pll.reference_div = adp3_ptr->sOutput.ucRefDiv;
+ }
+ if (adp3_ptr->sOutput.ucPostDiv) {
+ pll_flags |= RADEON_PLL_USE_POST_DIV;
+ info->pll.post_div = adp3_ptr->sOutput.ucPostDiv;
+ }
+ ErrorF("after %d %d %d\n", adp3_ptr->sOutput.ulDispPllFreq,
+ adp3_ptr->sOutput.ucRefDiv, adp3_ptr->sOutput.ucPostDiv);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
}
- ErrorF("after %d\n", adjust_pll_param.usPixelClock);
}
if (IS_AVIVO_VARIANT) {
@@ -439,10 +646,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
spc2_ptr->ucFracFbDiv = frac_fb_div;
spc2_ptr->ucPostDiv = post_div;
- spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+ spc2_ptr->ucPpll = radeon_crtc->pll_id;
spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
spc2_ptr->ucRefDivSrc = 1;
- ptr = &spc_param;
break;
case 3:
spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput;
@@ -451,12 +657,23 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
spc3_ptr->ucFracFbDiv = frac_fb_div;
spc3_ptr->ucPostDiv = post_div;
- spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+ spc3_ptr->ucPpll = radeon_crtc->pll_id;
spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
spc3_ptr->ucEncoderMode = atombios_get_encoder_mode(output);
-
- ptr = &spc_param;
+ break;
+ case 5:
+ spc5_ptr = (PIXEL_CLOCK_PARAMETERS_V5*)&spc_param.sPCLKInput;
+ spc5_ptr->ucCRTC = radeon_crtc->crtc_id;
+ spc5_ptr->usPixelClock = cpu_to_le16(mode->Clock / 10);
+ spc5_ptr->ucRefDiv = ref_div;
+ spc5_ptr->usFbDiv = cpu_to_le16(fb_div);
+ spc5_ptr->ulFbDivDecFrac = cpu_to_le32(frac_fb_div);
+ spc5_ptr->ucPostDiv = post_div;
+ spc5_ptr->ucPpll = radeon_crtc->pll_id;
+ spc5_ptr->ucMiscInfo = 0; //HDMI depth
+ spc5_ptr->ucTransmitterID = radeon_encoder->encoder_id;
+ spc5_ptr->ucEncoderMode = atombios_get_encoder_mode(output);
break;
default:
ErrorF("Unknown table version\n");
@@ -470,7 +687,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
data.exec.index = index;
data.exec.dataSpace = (void *)&space;
- data.exec.pspace = ptr;
+ data.exec.pspace = &spc_param;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Set CRTC %d PLL success\n", radeon_crtc->crtc_id);
@@ -756,10 +973,15 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+ atombios_pick_pll(crtc);
atombios_crtc_set_pll(crtc, adjusted_mode);
- atombios_set_crtc_timing(crtc, adjusted_mode);
- if (!IS_AVIVO_VARIANT && (radeon_crtc->crtc_id == 0))
+ if (IS_DCE4_VARIANT)
atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
+ else {
+ atombios_set_crtc_timing(crtc, adjusted_mode);
+ if (!IS_AVIVO_VARIANT && (radeon_crtc->crtc_id == 0))
+ atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
+ }
if (IS_DCE4_VARIANT)
evergreen_set_base_format(crtc, mode, adjusted_mode, x, y);
diff --git a/src/atombios_output.c b/src/atombios_output.c
index b56d8a0..d7c396b 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -765,11 +765,8 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
//if (radeon_output->dig_encoder)
// disp_data.v2.acConfig.ucEncoderSel = 1;
- // XXX select the PLL
- if (radeon_output->dig_encoder)
- disp_data.v3.acConfig.ucRefClkSource = 1; // PLL2
- else
- disp_data.v3.acConfig.ucRefClkSource = 0; // PLL1
+ // select the PLL
+ disp_data.v3.acConfig.ucRefClkSource = radeon_output->pll_id;
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index b5ce9f6..556b461 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -773,6 +773,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->Controller[0]->can_tile = 1;
else
pRADEONEnt->Controller[0]->can_tile = 0;
+ pRADEONEnt->Controller[0]->pll_id = -1;
}
if (mask & 2) {
@@ -801,6 +802,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->Controller[1]->can_tile = 1;
else
pRADEONEnt->Controller[1]->can_tile = 0;
+ pRADEONEnt->Controller[1]->pll_id = -1;
}
/* 6 crtcs on DCE4 chips */
@@ -844,6 +846,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->Controller[i]->can_tile = 1;
else
pRADEONEnt->Controller[i]->can_tile = 0;
+ pRADEONEnt->Controller[i]->pll_id = -1;
}
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 7cdf2de..dc02bdf 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -163,6 +163,7 @@ typedef struct _RADEONCrtcPrivateRec {
Bool scaler_enabled;
float vsc;
float hsc;
+ int pll_id;
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct _radeon_encoder {
@@ -299,6 +300,7 @@ typedef struct _RADEONOutputPrivateRec {
int dp_lane_count;
int dp_clock;
uint8_t hpd_id;
+ int pll_id;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
struct avivo_pll_state {
commit bd8e04cb7b39f38b6958273582a9b324a9f0759a
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Feb 1 10:07:43 2010 -0500
evergreen: add atom support for digital outputs
analog is already supported by the existing code.
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 6a769b0..b56d8a0 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -645,9 +645,58 @@ atombios_output_dig_encoder_setup(xf86OutputPtr output, int action)
}
+static int
+atombios_dce4_output_dig_encoder_setup(xf86OutputPtr output, int action)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
+ DIG_ENCODER_CONTROL_PARAMETERS_V3 disp_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+ int index;
+ int clock = radeon_output->pixel_clock;
+
+ if (radeon_encoder == NULL)
+ return ATOM_NOT_IMPLEMENTED;
+
+ memset(&disp_data,0, sizeof(disp_data));
+
+ index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
+
+ disp_data.ucAction = action;
+ disp_data.usPixelClock = cpu_to_le16(clock / 10);
+ disp_data.ucEncoderMode = atombios_get_encoder_mode(output);
+ disp_data.acConfig.ucDigSel = radeon_output->dig_encoder;
+
+ if (disp_data.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
+ if (dp_link_clock_for_mode_clock(radeon_output, clock) == 27000)
+ disp_data.acConfig.ucDPLinkRate = 1;
+ disp_data.ucLaneNum = dp_lanes_for_mode_clock(radeon_output, clock);
+ } else if (clock > 165000)
+ disp_data.ucLaneNum = 8;
+ else
+ disp_data.ucLaneNum = 4;
+
+ disp_data.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output DIG%d encoder setup success\n", radeon_output->dig_encoder);
+ return ATOM_SUCCESS;
+ }
+
+ ErrorF("Output DIG%d setup failed\n", radeon_output->dig_encoder);
+ return ATOM_NOT_IMPLEMENTED;
+}
+
union dig_transmitter_control {
DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
};
static int
@@ -668,7 +717,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
memset(&disp_data,0, sizeof(disp_data));
- if (IS_DCE32_VARIANT)
+ if (IS_DCE32_VARIANT || IS_DCE4_VARIANT)
index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
else {
switch (radeon_encoder->encoder_id) {
@@ -685,7 +734,65 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
disp_data.v1.ucAction = action;
- if (IS_DCE32_VARIANT) {
+ if (IS_DCE4_VARIANT) {
+ if (action == ATOM_TRANSMITTER_ACTION_INIT) {
+ disp_data.v3.usInitInfo = radeon_output->connector_object_id;
+ } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
+ disp_data.v3.asMode.ucLaneSel = lane_num;
+ disp_data.v3.asMode.ucLaneSet = lane_set;
+ } else {
+ if (radeon_output->MonType == MT_DP) {
+ disp_data.v3.usPixelClock =
+ cpu_to_le16(dp_link_clock_for_mode_clock(radeon_output, clock));
+ } else if (clock > 165000) {
+ disp_data.v3.usPixelClock = cpu_to_le16((clock / 2) / 10);
+ disp_data.v3.acConfig.fDualLinkConnector = 1;
+ } else {
+ disp_data.v3.usPixelClock = cpu_to_le16(clock / 10);
+ }
+ }
+
+ if (radeon_output->MonType == MT_DP)
+ disp_data.v3.ucLaneNum = dp_lanes_for_mode_clock(radeon_output, clock);
+ else if (clock > 165000)
+ disp_data.v3.ucLaneNum = 8;
+ else
+ disp_data.v3.ucLaneNum = 4;
+
+ if (radeon_output->linkb)
+ disp_data.v3.acConfig.ucLinkSel = 1;
+
+ //if (radeon_output->dig_encoder)
+ // disp_data.v2.acConfig.ucEncoderSel = 1;
+
+ // XXX select the PLL
+ if (radeon_output->dig_encoder)
+ disp_data.v3.acConfig.ucRefClkSource = 1; // PLL2
+ else
+ disp_data.v3.acConfig.ucRefClkSource = 0; // PLL1
+
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ disp_data.v3.acConfig.ucTransmitterSel = 0;
+ num = 0;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ disp_data.v3.acConfig.ucTransmitterSel = 1;
+ num = 1;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ disp_data.v3.acConfig.ucTransmitterSel = 2;
+ num = 2;
+ break;
+ }
+
+ if (radeon_output->MonType == MT_DP)
+ disp_data.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
+ else if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) {
+ if (radeon_output->coherent_mode)
+ disp_data.v3.acConfig.fCoherentMode = 1;
+ }
+ } else if (IS_DCE32_VARIANT) {
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
disp_data.v2.usInitInfo = radeon_output->connector_object_id;
} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
@@ -736,8 +843,8 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
disp_data.v1.usInitInfo = radeon_output->connector_object_id;
} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
- disp_data.v2.asMode.ucLaneSel = lane_num;
- disp_data.v2.asMode.ucLaneSet = lane_set;
+ disp_data.v1.asMode.ucLaneSel = lane_num;
+ disp_data.v1.asMode.ucLaneSet = lane_set;
} else {
if (radeon_output->MonType == MT_DP)
disp_data.v1.usPixelClock =
@@ -1443,10 +1550,26 @@ atombios_set_output_crtc_source(xf86OutputPtr output)
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
- if (radeon_output->dig_encoder)
- crtc_src_param2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
- else
- crtc_src_param2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
+ switch (radeon_output->dig_encoder) {
+ case 0:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
+ break;
+ case 1:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
+ break;
+ case 2:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
+ break;
+ case 3:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
+ break;
+ case 4:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
+ break;
+ case 5:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
+ break;
+ }
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT))
@@ -1517,7 +1640,9 @@ atombios_apply_output_quirks(xf86OutputPtr output, DisplayModePtr mode)
OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN);
}
- if (IS_DCE32_VARIANT && (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
+ if (IS_DCE32_VARIANT &&
+ (!IS_DCE4_VARIANT) &&
+ (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
if (radeon_encoder == NULL)
return;
@@ -1536,6 +1661,7 @@ atombios_pick_dig_encoder(xf86OutputPtr output)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(output->scrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
+ radeon_encoder_ptr radeon_encoder = NULL;
Bool is_lvtma = FALSE;
int i, mode;
uint32_t dig_enc_use_mask = 0;
@@ -1547,6 +1673,35 @@ atombios_pick_dig_encoder(xf86OutputPtr output)
mode == ATOM_ENCODER_MODE_CV)
return;
+ if (IS_DCE4_VARIANT) {
+ radeon_encoder = radeon_get_encoder(output);
+
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ if (radeon_output->linkb)
+ radeon_output->dig_encoder = 1;
+ else
+ radeon_output->dig_encoder = 0;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ if (radeon_output->linkb)
+ radeon_output->dig_encoder = 3;
+ else
+ radeon_output->dig_encoder = 2;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ if (radeon_output->linkb)
+ radeon_output->dig_encoder = 5;
+ else
+ radeon_output->dig_encoder = 4;
+ break;
+ default:
+ ErrorF("Unknown encoder\n");
+ break;
+ }
+ return;
+ }
+
if (IS_DCE32_VARIANT) {
RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
radeon_output->dig_encoder = radeon_crtc->crtc_id;
@@ -1555,8 +1710,8 @@ atombios_pick_dig_encoder(xf86OutputPtr output)
for (i = 0; i < xf86_config->num_output; i++) {
xf86OutputPtr test = xf86_config->output[i];
- radeon_encoder_ptr radeon_encoder = radeon_get_encoder(test);
RADEONOutputPrivatePtr radeon_test = test->driver_private;
+ radeon_encoder = radeon_get_encoder(test);
if (!radeon_encoder || !test->crtc)
continue;
@@ -1614,10 +1769,14 @@ atombios_output_mode_set(xf86OutputPtr output,
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
/* disable encoder and transmitter */
- atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
- atombios_output_dig_encoder_setup(output, ATOM_DISABLE);
-
/* setup and enable the encoder and transmitter */
+ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
+ if (IS_DCE4_VARIANT)
+ atombios_dce4_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_SETUP);
+ else {
+ atombios_output_dig_encoder_setup(output, ATOM_DISABLE);
+ atombios_output_dig_encoder_setup(output, ATOM_ENABLE);
+ }
atombios_output_dig_encoder_setup(output, ATOM_ENABLE);
atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
@@ -1878,13 +2037,18 @@ static inline int atom_dp_get_encoder_id(xf86OutputPtr output)
return ret;
}
+union aux_channel_transaction {
+ PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
+ PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
+};
+
Bool
RADEONProcessAuxCH(xf86OutputPtr output, uint8_t *req_bytes, uint8_t num_bytes,
uint8_t *read_byte, uint8_t read_buf_len, uint8_t delay)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
- PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
+ union aux_channel_transaction args;
AtomBiosArgRec data;
unsigned char *space;
unsigned char *base;
@@ -1899,29 +2063,31 @@ RADEONProcessAuxCH(xf86OutputPtr output, uint8_t *req_bytes, uint8_t num_bytes,
memcpy(base, req_bytes, num_bytes);
- args.lpAuxRequest = 0;
- args.lpDataOut = 16;
- args.ucDataOutLen = 0;
- args.ucChannelID = radeon_output->ucI2cId;
- args.ucDelay = delay / 10; /* 10 usec */
+ args.v1.lpAuxRequest = 0;
+ args.v1.lpDataOut = 16;
+ args.v1.ucDataOutLen = 0;
+ args.v1.ucChannelID = radeon_output->ucI2cId;
+ args.v1.ucDelay = delay / 10; /* 10 usec */
+ if (IS_DCE4_VARIANT)
+ args.v2.ucHPD_ID = radeon_output->hpd_id;
data.exec.index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &args;
RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data);
- if (args.ucReplyStatus) {
+ if (args.v1.ucReplyStatus) {
ErrorF("failed to get auxch %02x%02x %02x %02x %02x\n",
- req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],args.ucReplyStatus);
+ req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], args.v1.ucReplyStatus);
return FALSE;
}
- if (args.ucDataOutLen && read_byte && read_buf_len) {
- if (read_buf_len < args.ucDataOutLen) {
- ErrorF("%s: Buffer too small for return answer %d %d\n", __func__, read_buf_len, args.ucDataOutLen);
+ if (args.v1.ucDataOutLen && read_byte && read_buf_len) {
+ if (read_buf_len < args.v1.ucDataOutLen) {
+ ErrorF("%s: Buffer too small for return answer %d %d\n", __func__, read_buf_len, args.v1.ucDataOutLen);
return FALSE;
}
{
- int len = read_buf_len < args.ucDataOutLen ? read_buf_len : args.ucDataOutLen;
+ int len = read_buf_len < args.v1.ucDataOutLen ? read_buf_len : args.v1.ucDataOutLen;
memcpy(read_byte, base+16, len);
}
}
@@ -2463,6 +2629,7 @@ static void dp_update_dpvs_emph(xf86OutputPtr output, uint8_t train_set[4])
static void do_displayport_link_train(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
int enc_id = atom_dp_get_encoder_id(output);
Bool clock_recovery;
@@ -2504,8 +2671,13 @@ static void do_displayport_link_train(xf86OutputPtr output)
&ss_cntl);
/* start local training start */
- RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_START, enc_id, 0);
- RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, enc_id, 0);
+ if (IS_DCE4_VARIANT) {
+ atombios_dce4_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START);
+ atombios_dce4_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1);
+ } else {
+ RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_START, enc_id, 0);
+ RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, enc_id, 0);
+ }
usleep(400);
dp_set_training(output, DP_TRAINING_PATTERN_1);
@@ -2560,7 +2732,10 @@ static void do_displayport_link_train(xf86OutputPtr output)
tries = 0;
channel_eq = FALSE;
dp_set_training(output, DP_TRAINING_PATTERN_2);
- RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, enc_id, 1);
+ if (IS_DCE4_VARIANT)
+ atombios_dce4_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2);
+ else
+ RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, enc_id, 1);
for (;;) {
usleep(400);
@@ -2591,7 +2766,10 @@ static void do_displayport_link_train(xf86OutputPtr output)
"channel eq failed\n");
dp_set_training(output, DP_TRAINING_PATTERN_DISABLE);
- RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_COMPLETE, enc_id, 0);
+ if (IS_DCE4_VARIANT)
+ atombios_dce4_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
+ else
+ RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_COMPLETE, enc_id, 0);
}
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index d6c58bc..7bf9815 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1590,6 +1590,69 @@ rhdAtomParseI2CRecord(ScrnInfoPtr pScrn, atomBiosHandlePtr handle,
return RADEONLookupGPIOLineForDDC(pScrn, Record->sucI2cId.bfI2C_LineMux);
}
+static uint8_t
+radeon_lookup_hpd_id(ScrnInfoPtr pScrn, ATOM_HPD_INT_RECORD *record)
+{
+ RADEONInfoPtr info = RADEONPTR (pScrn);
+ unsigned short size;
+ uint8_t hpd = 0;
+ int i, num_indices;
+ struct _ATOM_GPIO_PIN_LUT *gpio_info;
+ ATOM_GPIO_PIN_ASSIGNMENT *pin;
+ atomDataTablesPtr atomDataPtr;
+ uint8_t crev, frev;
+ uint32_t reg;
+
+ atomDataPtr = info->atomBIOS->atomDataPtr;
+
+ if (!rhdAtomGetTableRevisionAndSize(
+ &(atomDataPtr->GPIO_Pin_LUT->sHeader),
+ &crev,&frev,&size)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Pin Table found!\n");
+ return hpd;
+ }
+
+ num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
+
+ if (IS_DCE4_VARIANT)
+ reg = EVERGREEN_DC_GPIO_HPD_A;
+ else
+ reg = AVIVO_DC_GPIO_HPD_A;
+
+ gpio_info = atomDataPtr->GPIO_Pin_LUT;
+ for (i = 0; i < num_indices; i++) {
+ pin = &gpio_info->asGPIO_Pin[i];
+ if (record->ucHPDIntGPIOID == pin->ucGPIO_ID) {
+ if ((pin->usGpioPin_AIndex * 4) == reg) {
+ switch (pin->ucGpioPinBitShift) {
+ case 0:
+ default:
+ hpd = 0;
+ break;
+ case 8:
+ hpd = 1;
+ break;
+ case 16:
+ hpd = 2;
+ break;
+ case 24:
+ hpd = 3;
+ break;
+ case 26:
+ hpd = 4;
+ break;
+ case 28:
+ hpd = 5;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ return hpd;
+}
+
static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
@@ -1935,6 +1998,9 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
(ATOM_I2C_RECORD *)Record, j);
break;
case ATOM_HPD_INT_RECORD_TYPE:
+ info->BiosConnector[i].hpd_id =
+ radeon_lookup_hpd_id(pScrn,
+ (ATOM_HPD_INT_RECORD *)Record);
break;
case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE:
break;
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 3bc2f00..49df82f 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2969,6 +2969,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
radeon_output->connector_id = info->BiosConnector[i].connector_object;
radeon_output->connector_object_id = info->BiosConnector[i].connector_object_id;
radeon_output->ucI2cId = info->BiosConnector[i].ucI2cId;
+ radeon_output->hpd_id = info->BiosConnector[i].hpd_id;
/* Technically HDMI-B is a glorfied DL DVI so the bios is correct,
* but this can be confusing to users when it comes to output names,
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index f374ab0..7cdf2de 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -242,6 +242,7 @@ typedef struct {
uint16_t connector_object;
uint16_t connector_object_id;
uint8_t ucI2cId;
+ uint8_t hpd_id;
} RADEONBIOSConnector;
typedef struct _RADEONOutputPrivateRec {
@@ -297,6 +298,7 @@ typedef struct _RADEONOutputPrivateRec {
uint8_t dpcd[8];
int dp_lane_count;
int dp_clock;
+ uint8_t hpd_id;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
struct avivo_pll_state {
commit 8ad40d3c32ad5b91725bd37fcade6bed504df421
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Tue Jan 26 15:39:44 2010 -0500
evergreen: add crtc set base/format support
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 026d231..f832374 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -481,6 +481,107 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
return;
}
+static void evergreen_set_base_format(xf86CrtcPtr crtc,
+ DisplayModePtr mode,
+ DisplayModePtr adjusted_mode,
+ int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
+ uint32_t fb_format;
+ uint32_t fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
+
+ switch (crtc->scrn->bitsPerPixel) {
+ case 15:
+ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
+ EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
+ break;
+ case 16:
+ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
+ EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
+#endif
+ break;
+ case 24:
+ case 32:
+ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
+ EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+#endif
+ break;
+ default:
+ FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
+ }
+
+ switch (radeon_crtc->crtc_id) {
+ case 0:
+ default:
+ OUTREG(AVIVO_D1VGA_CONTROL, 0);
+ break;
+ case 1:
+ OUTREG(AVIVO_D2VGA_CONTROL, 0);
+ break;
+ case 2:
+ OUTREG(EVERGREEN_D3VGA_CONTROL, 0);
+ break;
+ case 3:
+ OUTREG(EVERGREEN_D4VGA_CONTROL, 0);
+ break;
+ case 4:
+ OUTREG(EVERGREEN_D5VGA_CONTROL, 0);
+ break;
+ case 5:
+ OUTREG(EVERGREEN_D6VGA_CONTROL, 0);
+ break;
+ }
+
+ /* setup fb format and location
+ */
+ if (crtc->rotatedData != NULL) {
+ /* x/y offset is already included */
+ x = 0;
+ y = 0;
+ fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB;
+ }
+
+
+ OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
+ fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
+ OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
+ fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
+ OUTREG(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
+ OUTREG(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
+
+ OUTREG(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, info->virtualX);
+ OUTREG(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, info->virtualY);
+ OUTREG(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,
+ crtc->scrn->displayWidth);
+ OUTREG(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+
+ OUTREG(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, mode->VDisplay);
+ x &= ~3;
+ y &= ~1;
+ OUTREG(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ OUTREG(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, (mode->HDisplay << 16) | mode->VDisplay);
+
+ if (adjusted_mode->Flags & V_INTERLACE)
+ OUTREG(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, EVERGREEN_INTERLEAVE_EN);
+ else
+ OUTREG(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
+
+}
+
static void avivo_set_base_format(xf86CrtcPtr crtc,
DisplayModePtr mode,
DisplayModePtr adjusted_mode,
@@ -660,7 +761,9 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
if (!IS_AVIVO_VARIANT && (radeon_crtc->crtc_id == 0))
atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
- if (IS_AVIVO_VARIANT)
+ if (IS_DCE4_VARIANT)
+ evergreen_set_base_format(crtc, mode, adjusted_mode, x, y);
+ else if (IS_AVIVO_VARIANT)
avivo_set_base_format(crtc, mode, adjusted_mode, x, y);
else
legacy_set_base_format(crtc, mode, adjusted_mode, x, y);
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index b50cf42..b5ce9f6 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -644,7 +644,14 @@ radeon_crtc_set_origin(xf86CrtcPtr crtc, int x, int y)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- if (IS_AVIVO_VARIANT) {
+
+ if (IS_DCE4_VARIANT) {
+ x &= ~3;
+ y &= ~1;
+ atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
+ OUTREG(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
+ } else if (IS_AVIVO_VARIANT) {
x &= ~3;
y &= ~1;
atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
commit 2c9cf0a07ff9e5a4989861bc2fdfd71d841013a8
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Dec 10 15:29:14 2009 -0500
evergreen: add lut support
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 413bad4..b50cf42 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -414,36 +414,57 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc)
if (!crtc->enabled)
return;
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
+ if (IS_DCE4_VARIANT) {
+ OUTREG(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff);
- OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff);
- OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff);
- }
+ OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff);
- PAL_SELECT(radeon_crtc->crtc_id);
+ OUTREG(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_DC_LUT_RW_MODE, 0);
- OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
- }
+ for (i = 0; i < 256; i++) {
+ OUTREG(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, i);
+ OUTREG(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
+ (((radeon_crtc->lut_r[i]) << 20) |
+ ((radeon_crtc->lut_g[i]) << 10) |
+ (radeon_crtc->lut_b[i])));
+ }
+ } else {
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
- for (i = 0; i < 256; i++) {
- OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]);
- }
+ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
+ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff);
+ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff);
+ }
+
+ PAL_SELECT(radeon_crtc->crtc_id);
+
+ if (IS_AVIVO_VARIANT) {
+ OUTREG(AVIVO_DC_LUT_RW_MODE, 0);
+ OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
+ }
+
+ for (i = 0; i < 256; i++) {
+ OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]);
+ }
+
+ if (IS_AVIVO_VARIANT)
+ OUTREG(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
}
}
-
static void
radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green,
uint16_t *blue, int size)
commit 65246545c3dd9bfef73e8a0f200bd5909b89a167
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Tue Jan 26 12:10:02 2010 -0500
evergreen: add hw cursor support
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index cf5e9a0..2e60710 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -137,6 +137,48 @@ avivo_lock_cursor(xf86CrtcPtr crtc, Bool lock)
OUTREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, tmp);
}
+static void
+evergreen_setup_cursor(xf86CrtcPtr crtc, Bool enable)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ /* always use the same cursor mode even if the cursor is disabled,
+ * otherwise you may end up with cursor curruption bands
+ */
+ OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
+ EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
+
+ if (enable) {
+ OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0);
+ OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
+ (info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset)
+ & EVERGREEN_CUR_SURFACE_ADDRESS_MASK);
+ OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
+ EVERGREEN_CURSOR_EN | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
+ }
+}
+
+static void
+evergreen_lock_cursor(xf86CrtcPtr crtc, Bool lock)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ uint32_t tmp;
+
+ tmp = INREG(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
+
+ if (lock)
+ tmp |= EVERGREEN_CURSOR_UPDATE_LOCK;
+ else
+ tmp &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
+
+ OUTREG(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, tmp);
+}
+
void
radeon_crtc_show_cursor (xf86CrtcPtr crtc)
{
@@ -146,7 +188,11 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- if (IS_AVIVO_VARIANT) {
+ if (IS_DCE4_VARIANT) {
+ evergreen_lock_cursor(crtc, TRUE);
+ evergreen_setup_cursor(crtc, TRUE);
+ evergreen_lock_cursor(crtc, FALSE);
+ } else if (IS_AVIVO_VARIANT) {
avivo_lock_cursor(crtc, TRUE);
avivo_setup_cursor(crtc, TRUE);
avivo_lock_cursor(crtc, FALSE);
@@ -162,7 +208,7 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc)
return;
}
- OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20,
+ OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20,
~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
}
}
@@ -176,7 +222,11 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- if (IS_AVIVO_VARIANT) {
+ if (IS_DCE4_VARIANT) {
+ evergreen_lock_cursor(crtc, TRUE);
+ evergreen_setup_cursor(crtc, FALSE);
+ evergreen_lock_cursor(crtc, TRUE);
+ } else if (IS_AVIVO_VARIANT) {
avivo_lock_cursor(crtc, TRUE);
avivo_setup_cursor(crtc, FALSE);
avivo_lock_cursor(crtc, FALSE);
@@ -214,7 +264,16 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1;
if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1;
- if (IS_AVIVO_VARIANT) {
+ if (IS_DCE4_VARIANT) {
+ /* XXX - does evergreen need a similar hack as below? */
+ evergreen_lock_cursor(crtc, TRUE);
+ OUTREG(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16)
+ | (yorigin ? 0 : y));
+ OUTREG(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
+ OUTREG(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
+ ((CURSOR_WIDTH - 1) << 16) | (CURSOR_HEIGHT - 1));
+ evergreen_lock_cursor(crtc, FALSE);
+ } else if (IS_AVIVO_VARIANT) {
int w = CURSOR_WIDTH;
/* avivo cursor spans the full fb width */
@@ -373,6 +432,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
(unsigned int)radeon_crtc->cursor_offset);
}
/* set the cursor mode the same on both crtcs to avoid corruption */
+ /* XXX check if this is needed on evergreen */
if (IS_AVIVO_VARIANT)
OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
commit c05cad56b69d239fa2e69905d15f4f08b9db4c55
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Jan 28 01:28:52 2010 -0500
evergreen: add base asic support
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index fd2c38c..413bad4 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -681,6 +681,10 @@ RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
int pixel_bytes1 = info->CurrentLayout.pixel_bytes;
int pixel_bytes2 = info->CurrentLayout.pixel_bytes;
+ /* XXX fix me */
+ if (IS_DCE4_VARIANT)
+ return;
+
if (xf86_config->num_crtc == 2) {
if (xf86_config->crtc[1]->enabled &&
xf86_config->crtc[0]->enabled) {
@@ -713,6 +717,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
+ int i;
if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
radeon_crtc_funcs.shadow_create = radeon_crtc_shadow_create;
@@ -759,7 +764,10 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
pRADEONEnt->Controller[1]->crtc_id = 1;
- pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
+ if (IS_DCE4_VARIANT)
+ pRADEONEnt->Controller[1]->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
+ else
+ pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
pRADEONEnt->Controller[1]->initialized = FALSE;
if (info->allowColorTiling)
pRADEONEnt->Controller[1]->can_tile = 1;
@@ -767,6 +775,50 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->Controller[1]->can_tile = 0;
}
+ /* 6 crtcs on DCE4 chips */
+ if (IS_DCE4_VARIANT && ((mask & 3) == 3)) {
+ for (i = 2; i < RADEON_MAX_CRTC; i++) {
+ pRADEONEnt->pCrtc[i] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
+ if (!pRADEONEnt->pCrtc[i])
+ return FALSE;
+
+ pRADEONEnt->Controller[i] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
+ if (!pRADEONEnt->Controller[i])
+ {
+ xfree(pRADEONEnt->Controller[i]);
+ return FALSE;
+ }
+
+ pRADEONEnt->pCrtc[i]->driver_private = pRADEONEnt->Controller[i];
+ pRADEONEnt->Controller[i]->crtc_id = i;
+ switch (i) {
+ case 0:
+ pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
+ break;
+ case 1:
+ pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
+ break;
+ case 2:
+ pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
+ break;
+ case 3:
+ pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
+ break;
+ case 4:
+ pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
+ break;
+ case 5:
+ pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
+ break;
+ }
+ pRADEONEnt->Controller[i]->initialized = FALSE;
+ if (info->allowColorTiling)
+ pRADEONEnt->Controller[i]->can_tile = 1;
+ else
+ pRADEONEnt->Controller[i]->can_tile = 0;
+ }
+ }
+
return TRUE;
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index ae4993b..859a709 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -741,7 +741,12 @@ static Bool radeon_get_mc_idle(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
+ if (INREG(R600_SRBM_STATUS) & 0x1f00)
+ return FALSE;
+ else
+ return TRUE;
+ } else if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (INREG(R600_SRBM_STATUS) & 0x3f00)
return FALSE;
else
@@ -787,6 +792,7 @@ static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
+ /* evergreen is same as r7xx */
if (info->ChipFamily >= CHIP_FAMILY_RV770) {
if (mask & LOC_FB)
OUTREG(R700_MC_VM_FB_LOCATION, fb_loc);
@@ -837,6 +843,7 @@ static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
+ /* evergreen is same as r7xx */
if (info->ChipFamily >= CHIP_FAMILY_RV770) {
if (mask & LOC_FB)
*fb_loc = INREG(R700_MC_VM_FB_LOCATION);
@@ -1389,7 +1396,12 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
/* We shouldn't use info->videoRam here which might have been clipped
* but the real video RAM instead
*/
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
+ /* size in MB on evergreen */
+ /* XXX watch for overflow!!! */
+ mem_size = INREG(R600_CONFIG_MEMSIZE) * 1024 * 1024;
+ aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024;
+ } else if (info->ChipFamily >= CHIP_FAMILY_R600) {
mem_size = INREG(R600_CONFIG_MEMSIZE);
aper_size = INREG(R600_CONFIG_APER_SIZE);
} else {
@@ -1609,7 +1621,10 @@ static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
uint32_t aper_size;
unsigned char byte;
- if (info->ChipFamily >= CHIP_FAMILY_R600)
+ if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
+ /* size in MB */
+ aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024;
+ else if (info->ChipFamily >= CHIP_FAMILY_R600)
aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
else
aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
@@ -1671,7 +1686,7 @@ static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
*/
if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
return aper_size * 2;
-
+
return aper_size;
}
@@ -1692,7 +1707,11 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024);
} else {
- if (info->ChipFamily >= CHIP_FAMILY_R600)
+ if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
+ /* R600_CONFIG_MEMSIZE is MB on evergreen */
+ /* XXX watch for overflow!!! */
+ pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) * 1024;
+ else if (info->ChipFamily >= CHIP_FAMILY_R600)
pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
else {
/* Read VRAM size from card */
@@ -2307,6 +2326,12 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
if (info->IsSecondary)
return FALSE;
+ if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "No DRI yet on Evergreen\n");
+ return FALSE;
+ }
+
if (info->Chipset == PCI_CHIP_RN50_515E ||
info->Chipset == PCI_CHIP_RN50_5969) {
if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) {
@@ -3834,8 +3859,75 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
" MC_AGP_LOCATION : 0x%08x\n",
(unsigned)restore->mc_agp_location);
- if (IS_AVIVO_VARIANT) {
+ if (IS_DCE4_VARIANT) {
+ if (mc_fb_loc != restore->mc_fb_location ||
+ mc_agp_loc != restore->mc_agp_location) {
+ uint32_t tmp;
+
+ //XXX
+ //RADEONWaitForIdleMMIO(pScrn);
+
+ /* disable VGA rendering core */
+ OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) & ~AVIVO_VGA_VSTATUS_CNTL_MASK);
+ OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+ OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+ OUTREG(EVERGREEN_D3VGA_CONTROL, INREG(EVERGREEN_D3VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+ OUTREG(EVERGREEN_D4VGA_CONTROL, INREG(EVERGREEN_D4VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+ OUTREG(EVERGREEN_D5VGA_CONTROL, INREG(EVERGREEN_D5VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+ OUTREG(EVERGREEN_D6VGA_CONTROL, INREG(EVERGREEN_D6VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+ /* Stop display & memory access */
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
+
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
+
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
+
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
+
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+ OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN);
+ tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+
+ usleep(10000);
+ timeout = 0;
+ while (!(radeon_get_mc_idle(pScrn))) {
+ if (++timeout > 1000000) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Timeout trying to update memory controller settings !\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "You will probably crash now ... \n");
+ /* Nothing we can do except maybe try to kill the server,
+ * let's wait 2 seconds to leave the above message a chance
+ * to maybe hit the disk and continue trying to setup despite
+ * the MC being non-idle
+ */
+ usleep(2000000);
+ }
+ usleep(10);
+ }
+
+ radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP,
+ restore->mc_fb_location,
+ restore->mc_agp_location,
+ restore->mc_agp_location_hi);
+
+ OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000);
+
+ }
+ } else if (IS_AVIVO_VARIANT) {
if (mc_fb_loc != restore->mc_fb_location ||
mc_agp_loc != restore->mc_agp_location) {
uint32_t tmp;
@@ -5164,7 +5256,10 @@ static void RADEONSave(ScrnInfoPtr pScrn)
}
#endif
- if (IS_AVIVO_VARIANT) {
+ if (IS_DCE4_VARIANT) {
+ RADEONSaveMemMapRegisters(pScrn, save);
+ //XXX
+ } else if (IS_AVIVO_VARIANT) {
RADEONSaveMemMapRegisters(pScrn, save);
avivo_save(pScrn, save);
} else {
@@ -5214,7 +5309,10 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
RADEONBlank(pScrn);
- if (IS_AVIVO_VARIANT) {
+ if (IS_DCE4_VARIANT) {
+ RADEONRestoreMemMapRegisters(pScrn, restore);
+ //XXX
+ } else if (IS_AVIVO_VARIANT) {
RADEONRestoreMemMapRegisters(pScrn, restore);
avivo_restore(pScrn, restore);
} else {
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 3a18302..3bc2f00 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -920,6 +920,10 @@ radeon_bios_output_crtc(xf86OutputPtr output)
xf86CrtcPtr crtc = output->crtc;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ /* no need to update crtc routing scratch regs on DCE4 */
+ if (IS_DCE4_VARIANT)
+ return;
+
if (info->IsAtomBios) {
if (radeon_output->active_device & ATOM_DEVICE_TV1_SUPPORT) {
save->bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
@@ -2992,10 +2996,14 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
return FALSE;
}
output->driver_private = radeon_output;
- output->possible_crtcs = 1;
- /* crtc2 can drive LVDS, it just doesn't have RMX */
- if (!(radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)))
- output->possible_crtcs |= 2;
+ if (IS_DCE4_VARIANT) {
+ output->possible_crtcs = 0x3f;
+ } else {
+ output->possible_crtcs = 1;
+ /* crtc2 can drive LVDS, it just doesn't have RMX */
+ if (!(radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)))
+ output->possible_crtcs |= 2;
+ }
/* we can clone the DACs, and probably TV-out,
but I'm not sure it's worth the trouble */
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 43cf31d..f374ab0 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -52,7 +52,7 @@
extern DriverRec RADEON;
-#define RADEON_MAX_CRTC 2
+#define RADEON_MAX_CRTC 6
#define RADEON_MAX_BIOS_CONNECTOR 16
typedef enum
commit ed63e1b1abe8810b5da6b4140892337eef08a9ea
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Jan 29 12:42:33 2010 -0500
evergreen: add register and utility defines
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 5895da5..377c26b 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4115,6 +4115,155 @@
#define R600_BIOS_6_SCRATCH 0x173c
#define R600_BIOS_7_SCRATCH 0x1740
+/* evergreen */
+#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
+#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
+#define EVERGREEN_D3VGA_CONTROL 0x3e0
+#define EVERGREEN_D4VGA_CONTROL 0x3e4
+#define EVERGREEN_D5VGA_CONTROL 0x3e8
+#define EVERGREEN_D6VGA_CONTROL 0x3ec
+
+#define EVERGREEN_P1PLL_SS_CNTL 0x414
+#define EVERGREEN_P2PLL_SS_CNTL 0x454
+# define EVERGREEN_PxPLL_SS_EN (1 << 12)
+/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */
+#define EVERGREEN_GRPH_ENABLE 0x6800
+#define EVERGREEN_GRPH_CONTROL 0x6804
+# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0)
+# define EVERGREEN_GRPH_DEPTH_8BPP 0
+# define EVERGREEN_GRPH_DEPTH_16BPP 1
+# define EVERGREEN_GRPH_DEPTH_32BPP 2
+# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8)
+/* 8 BPP */
+# define EVERGREEN_GRPH_FORMAT_INDEXED 0
+/* 16 BPP */
+# define EVERGREEN_GRPH_FORMAT_ARGB1555 0
+# define EVERGREEN_GRPH_FORMAT_ARGB565 1
+# define EVERGREEN_GRPH_FORMAT_ARGB4444 2
+# define EVERGREEN_GRPH_FORMAT_AI88 3
+# define EVERGREEN_GRPH_FORMAT_MONO16 4
+# define EVERGREEN_GRPH_FORMAT_BGRA5551 5
+/* 32 BPP */
+# define EVERGREEN_GRPH_FORMAT_ARGB8888 0
+# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1
+# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2
+# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3
+# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4
+# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5
+# define EVERGREEN_GRPH_FORMAT_RGB111110 6
+# define EVERGREEN_GRPH_FORMAT_BGR101111 7
+#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c
+# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
+# define EVERGREEN_GRPH_ENDIAN_NONE 0
+# define EVERGREEN_GRPH_ENDIAN_8IN16 1
+# define EVERGREEN_GRPH_ENDIAN_8IN32 2
+# define EVERGREEN_GRPH_ENDIAN_8IN64 3
+# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
+# define EVERGREEN_GRPH_RED_SEL_R 0
+# define EVERGREEN_GRPH_RED_SEL_G 1
+# define EVERGREEN_GRPH_RED_SEL_B 2
+# define EVERGREEN_GRPH_RED_SEL_A 3
+# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
+# define EVERGREEN_GRPH_GREEN_SEL_G 0
+# define EVERGREEN_GRPH_GREEN_SEL_B 1
+# define EVERGREEN_GRPH_GREEN_SEL_A 2
+# define EVERGREEN_GRPH_GREEN_SEL_R 3
+# define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
+# define EVERGREEN_GRPH_BLUE_SEL_B 0
+# define EVERGREEN_GRPH_BLUE_SEL_A 1
+# define EVERGREEN_GRPH_BLUE_SEL_R 2
+# define EVERGREEN_GRPH_BLUE_SEL_G 3
+# define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
+# define EVERGREEN_GRPH_ALPHA_SEL_A 0
+# define EVERGREEN_GRPH_ALPHA_SEL_R 1
+# define EVERGREEN_GRPH_ALPHA_SEL_G 2
+# define EVERGREEN_GRPH_ALPHA_SEL_B 3
+#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810
+#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814
+# define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0)
+# define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00
+#define EVERGREEN_GRPH_PITCH 0x6818
+#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c
+#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820
+#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824
+#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828
+#define EVERGREEN_GRPH_X_START 0x682c
+#define EVERGREEN_GRPH_Y_START 0x6830
+#define EVERGREEN_GRPH_X_END 0x6834
+#define EVERGREEN_GRPH_Y_END 0x6838
+
+/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
+#define EVERGREEN_CUR_CONTROL 0x6998
+# define EVERGREEN_CURSOR_EN (1 << 0)
+# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8)
+# define EVERGREEN_CURSOR_MONO 0
+# define EVERGREEN_CURSOR_24_1 1
+# define EVERGREEN_CURSOR_24_8_PRE_MULT 2
+# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3
+# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16)
+# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20)
+# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
+# define EVERGREEN_CURSOR_URGENT_ALWAYS 0
+# define EVERGREEN_CURSOR_URGENT_1_8 1
+# define EVERGREEN_CURSOR_URGENT_1_4 2
+# define EVERGREEN_CURSOR_URGENT_3_8 3
+# define EVERGREEN_CURSOR_URGENT_1_2 4
+#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c
+# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000
+#define EVERGREEN_CUR_SIZE 0x69a0
+#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4
+#define EVERGREEN_CUR_POSITION 0x69a8
+#define EVERGREEN_CUR_HOT_SPOT 0x69ac
+#define EVERGREEN_CUR_COLOR1 0x69b0
+#define EVERGREEN_CUR_COLOR2 0x69b4
+#define EVERGREEN_CUR_UPDATE 0x69b8
+# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0)
+# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1)
+# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16)
+# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
+
+/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */
+#define EVERGREEN_DC_LUT_RW_MODE 0x69e0
+#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4
+#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8
+#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec
+#define EVERGREEN_DC_LUT_30_COLOR 0x69f0
+#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4
+#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8
+#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc
+#define EVERGREEN_DC_LUT_CONTROL 0x6a00
+#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04
+#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08
+#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c
+#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10
+#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14
+#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18
+
+#define EVERGREEN_DATA_FORMAT 0x6b00
+# define EVERGREEN_INTERLEAVE_EN (1 << 0)
+#define EVERGREEN_DESKTOP_HEIGHT 0x6b04
+
+#define EVERGREEN_VIEWPORT_START 0x6d70
+#define EVERGREEN_VIEWPORT_SIZE 0x6d74
+
+/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
+#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0)
+#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0)
+#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0)
+#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0)
+#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0)
+#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0)
+
+/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
+#define EVERGREEN_CRTC_CONTROL 0x6e70
+# define EVERGREEN_CRTC_MASTER_EN (1 << 0)
+#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
+
+#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0
+#define EVERGREEN_DC_GPIO_HPD_A 0x64b4
+#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8
+#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc
+
#define R300_GB_TILE_CONFIG 0x4018
# define R300_ENABLE_TILING (1 << 0)
# define R300_PIPE_COUNT_RV350 (0 << 1)
commit 019260ec4a9f9fbf2ac63a2ca3314aa308471f7e
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Dec 10 14:57:39 2009 -0500
evergreen: add chip enums
diff --git a/src/radeon.h b/src/radeon.h
index adc848d..2138b4a 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -347,10 +347,15 @@ typedef enum {
CHIP_FAMILY_RV635,
CHIP_FAMILY_RS780,
CHIP_FAMILY_RS880,
- CHIP_FAMILY_RV770,
+ CHIP_FAMILY_RV770, /* r700 */
CHIP_FAMILY_RV730,
CHIP_FAMILY_RV710,
CHIP_FAMILY_RV740,
+ CHIP_FAMILY_CEDAR, /* evergreen */
+ CHIP_FAMILY_REDWOOD,
+ CHIP_FAMILY_JUNIPER,
+ CHIP_FAMILY_CYPRESS,
+ CHIP_FAMILY_HEMLOCK,
CHIP_FAMILY_LAST
} RADEONChipFamily;
@@ -378,6 +383,8 @@ typedef enum {
#define IS_DCE32_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV730))
+#define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR))
+
#define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600)
#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \
commit e86ae564d8b94d2cc8d3c7cceb452a197ab6387a
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Feb 1 12:03:23 2010 -0500
atom: update to the latest upstream atombios.h changes
diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h
index 4a1f019..66b238f 100644
--- a/src/AtomBios/includes/atombios.h
+++ b/src/AtomBios/includes/atombios.h
@@ -61,12 +61,19 @@
#define ATOM_CRTC1 0
#define ATOM_CRTC2 1
+#define ATOM_CRTC3 2
+#define ATOM_CRTC4 3
+#define ATOM_CRTC5 4
+#define ATOM_CRTC6 5
+#define ATOM_CRTC_INVALID 0xFF
#define ATOM_DIGA 0
#define ATOM_DIGB 1
#define ATOM_PPLL1 0
#define ATOM_PPLL2 1
+#define ATOM_DCPLL 2
+#define ATOM_PPLL_INVALID 0xFF
#define ATOM_SCALER1 0
#define ATOM_SCALER2 1
@@ -84,6 +91,7 @@
#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
+#define ATOM_GET_STATUS (ATOM_DISABLE+8)
#define ATOM_BLANKING 1
#define ATOM_BLANKING_OFF 0
@@ -241,18 +249,18 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT CV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
USHORT GetConditionalGoldenSetting; //only used by Bios
USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3
USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3
- USHORT TV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
+ USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
USHORT EnableScaler; //Atomic Table, used only by Bios
USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
- USHORT EnableVGA_Access; //Obsolete , only used by Bios
+ USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
USHORT SetCRTC_Replication; //Atomic Table, used only by Bios
@@ -302,6 +310,8 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
#define LVTMATransmitterControl DIG2TransmitterControl
#define SetCRTC_DPM_State GetConditionalGoldenSetting
#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange
+#define HPDInterruptService ReadHWAssistedI2CStatus
+#define EnableVGA_Access GetSCLKOverMCLKRatio
typedef struct _ATOM_MASTER_COMMAND_TABLE
{
@@ -415,6 +425,20 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
+#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
+
+
+// V4 are only used for APU which PLL outside GPU
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
+{
+#if ATOM_BIG_ENDIAN
+ ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
+ ULONG ulClock:24; //Input= target clock, output = actual clock
+#else
+ ULONG ulClock:24; //Input= target clock, output = actual clock
+ ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
+#endif
+}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
{
@@ -580,6 +604,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
#define ATOM_ENCODER_MODE_DVI 2
#define ATOM_ENCODER_MODE_HDMI 3
#define ATOM_ENCODER_MODE_SDVO 4
+#define ATOM_ENCODER_MODE_DP_AUDIO 5
#define ATOM_ENCODER_MODE_TV 13
#define ATOM_ENCODER_MODE_CV 14
#define ATOM_ENCODER_MODE_CRT 15
@@ -614,7 +639,8 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
// =3: HDMI encoder
// =4: SDVO encoder
UCHAR ucLaneNum; // how many lanes to enable
- UCHAR ucReserved[2];
+ UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
+ UCHAR ucReserved;
}DIG_ENCODER_CONTROL_PARAMETERS_V2;
//ucConfig
@@ -629,6 +655,67 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
+// ucAction:
+// ATOM_DISABLE
+// ATOM_ENABLE
+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
+#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
+#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
+#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
+#define ATOM_ENCODER_CMD_SETUP 0x0f
+
+// ucStatus
+#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
+#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
+
+// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
+typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
+{
+#if ATOM_BIG_ENDIAN
+ UCHAR ucReserved1:1;
+ UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F
+ UCHAR ucReserved:3;
+ UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
+#else
+ UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
+ UCHAR ucReserved:3;
+ UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F
+ UCHAR ucReserved1:1;
+#endif
+}ATOM_DIG_ENCODER_CONFIG_V3;
+
+#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
+
+
+typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
+{
+ USHORT usPixelClock; // in 10KHz; for bios convenient
+ ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
+ UCHAR ucAction;
+ UCHAR ucEncoderMode;
+ // =0: DP encoder
+ // =1: LVDS encoder
+ // =2: DVI encoder
+ // =3: HDMI encoder
+ // =4: SDVO encoder
+ // =5: DP audio
+ UCHAR ucLaneNum; // how many lanes to enable
+ UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
+ UCHAR ucReserved;
+}DIG_ENCODER_CONTROL_PARAMETERS_V3;
+
+
+// define ucBitPerColor:
+#define PANEL_BPC_UNDEFINE 0x00
+#define PANEL_6BIT_PER_COLOR 0x01
+#define PANEL_8BIT_PER_COLOR 0x02
+#define PANEL_10BIT_PER_COLOR 0x03
+#define PANEL_12BIT_PER_COLOR 0x04
+#define PANEL_16BIT_PER_COLOR 0x05
+
/****************************************************************************/
// Structures used by UNIPHYTransmitterControlTable
// LVTMATransmitterControlTable
@@ -710,7 +797,8 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
#define ATOM_TRANSMITTER_ACTION_SETUP 10
#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
-
+#define ATOM_TRANSMITTER_ACTION_POWER_ON 12
+#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
// Following are used for DigTransmitterControlTable ver1.2
typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
@@ -750,7 +838,7 @@ typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
//Bit2
#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
-#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
+#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
// Bit3
@@ -776,10 +864,77 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
};
ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
- UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
+ UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
UCHAR ucReserved[4];
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
+typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
+{
+#if ATOM_BIG_ENDIAN
+ UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
+ // =1 Dig Transmitter 2 ( Uniphy CD )
+ // =2 Dig Transmitter 3 ( Uniphy EF )
+ UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
+ UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
+ UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
+ // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
+ UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
+ UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
+#else
+ UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
+ UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
+ UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
+ // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
+ UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
+ UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
+ UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
+ // =1 Dig Transmitter 2 ( Uniphy CD )
+ // =2 Dig Transmitter 3 ( Uniphy EF )
+#endif
+}ATOM_DIG_TRANSMITTER_CONFIG_V3;
+
+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
+{
+ union
+ {
+ USHORT usPixelClock; // in 10KHz; for bios convenient
+ USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
+ ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
+ };
+ ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
+ UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
+ UCHAR ucLaneNum;
+ UCHAR ucReserved[3];
+}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
+
+//ucConfig
+//Bit0
+#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
+
+//Bit1
+#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
+
+//Bit2
+#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
+#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
+#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
+
+// Bit3
+#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
+#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
+#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
+
+// Bit5:4
+#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
+#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
+#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
+#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
+
+// Bit7:6
+#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
+#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
+#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
+#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
/****************************************************************************/
// Structures used by DAC1OuputControlTable
@@ -982,6 +1137,10 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V2
#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
+#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
+// V1.4 for RoadRunner
+#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
+#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
typedef struct _PIXEL_CLOCK_PARAMETERS_V3
{
@@ -1000,11 +1159,66 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V3
};
UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
// bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
+ // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
}PIXEL_CLOCK_PARAMETERS_V3;
#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
+typedef struct _PIXEL_CLOCK_PARAMETERS_V5
+{
+ UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
+ // drive the pixel clock. not used for DCPLL case.
+ union{
+ UCHAR ucReserved;
+ UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
+ };
+ USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
+ // 0 means disable PPLL/DCPLL.
+ USHORT usFbDiv; // feedback divider integer part.
+ UCHAR ucPostDiv; // post divider.
+ UCHAR ucRefDiv; // Reference divider
+ UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
+ UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
+ // indicate which graphic encoder will be used.
+ UCHAR ucEncoderMode; // Encoder mode:
+ UCHAR ucMiscInfo; // bit[0]= Force program PPLL
+ // bit[1]= when VGA timing is used.
+ // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
+ // bit[4]= RefClock source for PPLL.
+ // =0: XTLAIN( default mode )
+ // =1: other external clock source, which is pre-defined
+ // by VBIOS depend on the feature required.
+ // bit[7:5]: reserved.
+ ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
+
+}PIXEL_CLOCK_PARAMETERS_V5;
+
+#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
+#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
+#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
+#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
+#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
+#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
+#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
+
+typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
+{
+ PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
+}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
+
+typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
+{
+ UCHAR ucStatus;
+ UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
+ UCHAR ucReserved[2];
+}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
+
+typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
+{
+ PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
+}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
+
/****************************************************************************/
// Structures used by AdjustDisplayPllTable
/****************************************************************************/
@@ -1022,9 +1236,47 @@ typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
}ADJUST_DISPLAY_PLL_PARAMETERS;
#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
-
#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
+typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
+{
+ USHORT usPixelClock; // target pixel clock
+ UCHAR ucTransmitterID; // transmitter id defined in objectid.h
+ UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
+ UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
+ UCHAR ucReserved[3];
+}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
+
+// usDispPllConfig v1.2 for RoadRunner
+#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
+#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
+#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
+
+
+typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
+{
+ ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
+ UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
+ UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
+ UCHAR ucReserved[2];
+}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
+
+typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
+{
+ union
+ {
+ ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;
+ ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
+ };
+} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
+
/****************************************************************************/
// Structures used by EnableYUVTable
/****************************************************************************/
@@ -1162,6 +1414,30 @@ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
+typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
+{
+ USHORT usSpreadSpectrumPercentage;
+ UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
+ // Bit[1]: 1-Ext. 0-Int.
+ // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
+ // Bits[7:4] reserved
+ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
+ USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
+ USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
+}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
+
+#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
+#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
+#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
+#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
+#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
+#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
+#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
+#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
+#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
+#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
+#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
+
#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
/**************************************************************************/
@@ -1419,11 +1695,6 @@ typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
//==============================Data Table Portion====================================
-#ifdef UEFI_BUILD
- #define UTEMP USHORT
- #define USHORT void*
-#endif
-
/****************************************************************************/
// Structure used in Data.mtb
/****************************************************************************/
@@ -1465,10 +1736,6 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
}ATOM_MASTER_LIST_OF_DATA_TABLES;
-#ifdef UEFI_BUILD
- #define USHORT UTEMP
-#endif
-
typedef struct _ATOM_MASTER_DATA_TABLE
{
ATOM_COMMON_TABLE_HEADER sHeader;
@@ -1521,8 +1788,8 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
-#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008
-#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010
+#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
+#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
@@ -1530,7 +1797,8 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
-
+#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
+#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
#ifndef _H2INC
@@ -1724,7 +1992,47 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_4
UCHAR ucMemoryModule_ID; //Indicate what is the board design
}ATOM_FIRMWARE_INFO_V1_4;
-#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4
+//the structure below to be used from Cypress
+typedef struct _ATOM_FIRMWARE_INFO_V2_1
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulFirmwareRevision;
+ ULONG ulDefaultEngineClock; //In 10Khz unit
+ ULONG ulDefaultMemoryClock; //In 10Khz unit
+ ULONG ulReserved1;
+ ULONG ulReserved2;
+ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
+ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
+ ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
+ ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
+ UCHAR ucReserved1; //Was ucASICMaxTemperature;
+ UCHAR ucMinAllowedBL_Level;
+ USHORT usBootUpVDDCVoltage; //In MV unit
+ USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
+ USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
+ ULONG ulReserved4; //Was ulAsicMaximumVoltage
+ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
+ USHORT usMinEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
+ USHORT usMinEngineClockPLL_Output; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
+ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
+ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
+ USHORT usMinPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
+ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
+ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+ USHORT usCoreReferenceClock; //In 10Khz unit
+ USHORT usMemoryReferenceClock; //In 10Khz unit
+ USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
+ UCHAR ucMemoryModule_ID; //Indicate what is the board design
+ UCHAR ucReserved4[3];
+}ATOM_FIRMWARE_INFO_V2_1;
+
+
+#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_1
/****************************************************************************/
// Structures used in IntegratedSystemInfoTable
@@ -1836,14 +2144,16 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
USHORT usUMASyncStartDelay;
USHORT usUMADataReturnTime;
USHORT usLinkStatusZeroTime;
- USHORT usReserved;
+ USHORT usDACEfuse; //for storing badgap value (for RS880 only)
ULONG ulHighVoltageHTLinkFreq; // in 10Khz
ULONG ulLowVoltageHTLinkFreq; // in 10Khz
USHORT usMaxUpStreamHTLinkWidth;
USHORT usMaxDownStreamHTLinkWidth;
USHORT usMinUpStreamHTLinkWidth;
USHORT usMinDownStreamHTLinkWidth;
- ULONG ulReserved3[97]; //must be 0x0
+ USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
+ USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
+ ULONG ulReserved3[96]; //must be 0x0
}ATOM_INTEGRATED_SYSTEM_INFO_V2;
/*
@@ -1866,21 +2176,30 @@ Bit[6]=1: High Voltage requested for all power states. In this case, voltage wil
=0: Voltage settings is determined by powerplay table.
Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
=0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
+Bit[8]=1: CDLF is supported and enabled on current system.
+ =0: CDLF is not supported or enabled on current system.
+Bit[9]=1: DLL Shut Down feature is enabled on current system.
+ =0: DLL Shut Down feature is not enabled or supported on current system.
ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
- [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
+ [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
- [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
+ [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
+ When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
+ in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
+ one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
+
[15:8] - Lane configuration attribute;
[23:16]- Connector type, possible value:
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
CONNECTOR_OBJECT_ID_HDMI_TYPE_A
CONNECTOR_OBJECT_ID_DISPLAYPORT
+ CONNECTOR_OBJECT_ID_eDP
[31:24]- Reserved
ulDDISlot2Config: Same as Slot1.
@@ -1896,11 +2215,13 @@ ucDockingPinPolarity:Polarity of the pin when docked;
ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0
usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
+
usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
+
usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
@@ -1938,6 +2259,8 @@ usMinDownStreamHTLinkWidth: same as above.
#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
+#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100
+#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200
#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
@@ -1954,6 +2277,41 @@ usMinDownStreamHTLinkWidth: same as above.
#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
+// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulBootUpEngineClock; //in 10kHz unit
+ ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
+ ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
+ ULONG ulBootUpUMAClock; //in 10kHz unit
+ ULONG ulReserved1[8]; //must be 0x0 for the reserved
+ ULONG ulBootUpReqDisplayVector;
+ ULONG ulOtherDisplayMisc;
+ ULONG ulReserved2[4]; //must be 0x0 for the reserved
+ ULONG ulSystemConfig; //TBD
+ ULONG ulCPUCapInfo; //TBD
+ USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
+ USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
+ USHORT usBootUpNBVoltage; //boot up NB voltage
+ UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
+ UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
+ ULONG ulReserved3[4]; //must be 0x0 for the reserved
+ ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
+ ULONG ulDDISlot2Config;
+ ULONG ulDDISlot3Config;
+ ULONG ulDDISlot4Config;
+ ULONG ulReserved4[4]; //must be 0x0 for the reserved
+ UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
+ UCHAR ucUMAChannelNumber;
+ USHORT usReserved;
+ ULONG ulReserved5[4]; //must be 0x0 for the reserved
+ ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
+ ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
+ ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
+ ULONG ulReserved6[61]; //must be 0x0
+}ATOM_INTEGRATED_SYSTEM_INFO_V5;
+
#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
@@ -1969,7 +2327,7 @@ usMinDownStreamHTLinkWidth: same as above.
#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
-// define ASIC internal encoder id ( bit vector )
+// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
#define ASIC_INT_DAC1_ENCODER_ID 0x00
#define ASIC_INT_TV_ENCODER_ID 0x02
#define ASIC_INT_DIG1_ENCODER_ID 0x03
@@ -1978,10 +2336,24 @@ usMinDownStreamHTLinkWidth: same as above.
#define ASIC_INT_DVO_ENCODER_ID 0x07
#define ASIC_INT_DIG2_ENCODER_ID 0x09
#define ASIC_EXT_DIG_ENCODER_ID 0x05
+#define ASIC_EXT_DIG2_ENCODER_ID 0x08
+#define ASIC_INT_DIG3_ENCODER_ID 0x0a
+#define ASIC_INT_DIG4_ENCODER_ID 0x0b
+#define ASIC_INT_DIG5_ENCODER_ID 0x0c
+#define ASIC_INT_DIG6_ENCODER_ID 0x0d
//define Encoder attribute
#define ATOM_ANALOG_ENCODER 0
#define ATOM_DIGITAL_ENCODER 1
+#define ATOM_DP_ENCODER 2
+
+#define ATOM_ENCODER_ENUM_MASK 0x70
+#define ATOM_ENCODER_ENUM_ID1 0x00
+#define ATOM_ENCODER_ENUM_ID2 0x10
+#define ATOM_ENCODER_ENUM_ID3 0x20
+#define ATOM_ENCODER_ENUM_ID4 0x30
+#define ATOM_ENCODER_ENUM_ID5 0x40
+#define ATOM_ENCODER_ENUM_ID6 0x50
#define ATOM_DEVICE_CRT1_INDEX 0x00000000
#define ATOM_DEVICE_LCD1_INDEX 0x00000001
@@ -1989,12 +2361,13 @@ usMinDownStreamHTLinkWidth: same as above.
#define ATOM_DEVICE_DFP1_INDEX 0x00000003
#define ATOM_DEVICE_CRT2_INDEX 0x00000004
#define ATOM_DEVICE_LCD2_INDEX 0x00000005
-#define ATOM_DEVICE_TV2_INDEX 0x00000006
+#define ATOM_DEVICE_DFP6_INDEX 0x00000006
#define ATOM_DEVICE_DFP2_INDEX 0x00000007
#define ATOM_DEVICE_CV_INDEX 0x00000008
-#define ATOM_DEVICE_DFP3_INDEX 0x00000009
-#define ATOM_DEVICE_DFP4_INDEX 0x0000000A
-#define ATOM_DEVICE_DFP5_INDEX 0x0000000B
+#define ATOM_DEVICE_DFP3_INDEX 0x00000009
+#define ATOM_DEVICE_DFP4_INDEX 0x0000000A
+#define ATOM_DEVICE_DFP5_INDEX 0x0000000B
+
#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
@@ -2008,19 +2381,19 @@ usMinDownStreamHTLinkWidth: same as above.
#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
-#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX)
+#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )
#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
-#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX )
-#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX)
+#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )
+#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )
#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
-#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
-#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
-#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
+#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
+#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
+#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
#define ATOM_DEVICE_CRT_SUPPORT ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT
-#define ATOM_DEVICE_DFP_SUPPORT ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT
-#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT
+#define ATOM_DEVICE_DFP_SUPPORT ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT
+#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT
#define ATOM_DEVICE_LCD_SUPPORT ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT
#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
@@ -2071,15 +2444,18 @@ usMinDownStreamHTLinkWidth: same as above.
// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
-// Bit 6 = 0 - no TV2 support= 1- TV2 is supported
+// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
// Bit 8 = 0 - no CV support= 1- CV is supported
// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
-// Byte1 (Supported Device Info)
-// Bit 0 = = 0 - no CV support= 1- CV is supported
+// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
+// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
//
//
+/****************************************************************************/
+/* Structure used in MclkSS_InfoTable */
+/****************************************************************************/
// ucI2C_ConfigID
// [7:0] - I2C LINE Associate ID
// = 0 - no I2C
@@ -2325,10 +2701,6 @@ typedef struct _ATOM_DTD_FORMAT
#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
-//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
-//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
-#define LCDPANEL_CAP_READ_EDID 0x1
-
//ucTableFormatRevision=1
//ucTableContentRevision=1
typedef struct _ATOM_LVDS_INFO
@@ -2374,6 +2746,39 @@ typedef struct _ATOM_LVDS_INFO_V12
UCHAR ucReserved[2];
}ATOM_LVDS_INFO_V12;
+//Definitions for ucLCDPanel_SpecialHandlingCap:
+
+//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
+//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
+#define LCDPANEL_CAP_READ_EDID 0x1
+
+//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
+//with multiple supported refresh rates at usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
+//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
+#define LCDPANEL_CAP_DRR_SUPPORTED 0x2
+
+//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
+#define LCDPANEL_CAP_eDP 0x4
+
+
+//Color Bit Depth definition in EDID V1.4 @BYTE 14h
+//Bit 6 5 4
+ // 0 0 0 - Color bit depth is undefined
+ // 0 0 1 - 6 Bits per Primary Color
+ // 0 1 0 - 8 Bits per Primary Color
+ // 0 1 1 - 10 Bits per Primary Color
+ // 1 0 0 - 12 Bits per Primary Color
+ // 1 0 1 - 14 Bits per Primary Color
+ // 1 1 0 - 16 Bits per Primary Color
+ // 1 1 1 - Reserved
+
+#define PANEL_COLOR_BIT_DEPTH_MASK 0x70
+
+// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
+#define PANEL_RANDOM_DITHER 0x80
+#define PANEL_RANDOM_DITHER_MASK 0x80
+
+
#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12
typedef struct _ATOM_PATCH_RECORD_MODE
@@ -2390,6 +2795,7 @@ typedef struct _ATOM_LCD_RTS_RECORD
}ATOM_LCD_RTS_RECORD;
//!! If the record below exits, it shoud always be the first record for easy use in command table!!!
+// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
typedef struct _ATOM_LCD_MODE_CONTROL_CAP
{
UCHAR ucRecordType;
@@ -2428,7 +2834,7 @@ typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
{
USHORT usSpreadSpectrumPercentage;
- UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
+ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
UCHAR ucSS_Step;
UCHAR ucSS_Delay;
UCHAR ucSS_Id;
@@ -2437,8 +2843,10 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
#define ATOM_MAX_SS_ENTRY 16
-#define ATOM_DP_SS_ID1 0x0f1 // SS modulation freq=30k
-#define ATOM_DP_SS_ID2 0x0f2 // SS modulation freq=33k
+#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
+#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
+#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
+#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
@@ -2471,7 +2879,7 @@ typedef struct _ATOM_SPREAD_SPECTRUM_INFO
//ATOM_TV_PAL60 7
//ATOM_TV_SECAM 8
-//ucTVSuppportedStd definition:
+//ucTVSupportedStd definition:
#define NTSC_SUPPORT 0x1
#define NTSCJ_SUPPORT 0x2
@@ -2507,6 +2915,16 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2
ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];
}ATOM_ANALOG_TV_INFO_V1_2;
+typedef struct _ATOM_DPCD_INFO
+{
+ UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
+ UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
+ UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
+ UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
+}ATOM_DPCD_INFO;
+
+#define ATOM_DPCD_MAX_LANE_MASK 0x1F
+
/**************************************************************************/
// VRAM usage and their defintions
@@ -2555,11 +2973,11 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2
#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
@@ -2601,6 +3019,21 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2
// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
// (in offset to start of memory address) is KB aligned instead of byte aligend.
/***********************************************************************************/
+// Note3:
+/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter,
+for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:
+
+If (ulStartAddrUsedByFirmware!=0)
+FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
+Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
+else //Non VGA case
+ if (FB_Size<=2Gb)
+ FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
+ else
+ FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
+
+CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
+
#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
@@ -2616,6 +3049,20 @@ typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
}ATOM_VRAM_USAGE_BY_FIRMWARE;
+// change verion to 1.5, when allow driver to allocate the vram area for command table access.
+typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
+{
+ ULONG ulStartAddrUsedByFirmware;
+ USHORT usFirmwareUseInKb;
+ USHORT usFBUsedByDrvInKb;
+}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
+
+typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
+}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
+
/****************************************************************************/
// Structure used in GPIO_Pin_LUTTable
/****************************************************************************/
@@ -2738,6 +3185,17 @@ typedef struct _ATOM_OBJECT_HEADER
USHORT usDisplayPathTableOffset;
}ATOM_OBJECT_HEADER;
+typedef struct _ATOM_OBJECT_HEADER_V3
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT usDeviceSupport;
+ USHORT usConnectorObjectTableOffset;
+ USHORT usRouterObjectTableOffset;
+ USHORT usEncoderObjectTableOffset;
+ USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
+ USHORT usDisplayPathTableOffset;
+ USHORT usMiscObjectTableOffset;
+}ATOM_OBJECT_HEADER_V3;
typedef struct _ATOM_DISPLAY_OBJECT_PATH
{
@@ -2781,6 +3239,51 @@ typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset
}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
+//Two definitions below are for OPM on MXM module designs
+
+#define EXT_HPDPIN_LUTINDEX_0 0
+#define EXT_HPDPIN_LUTINDEX_1 1
+#define EXT_HPDPIN_LUTINDEX_2 2
+#define EXT_HPDPIN_LUTINDEX_3 3
+#define EXT_HPDPIN_LUTINDEX_4 4
+#define EXT_HPDPIN_LUTINDEX_5 5
+#define EXT_HPDPIN_LUTINDEX_6 6
+#define EXT_HPDPIN_LUTINDEX_7 7
+#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)
+
+#define EXT_AUXDDC_LUTINDEX_0 0
+#define EXT_AUXDDC_LUTINDEX_1 1
+#define EXT_AUXDDC_LUTINDEX_2 2
+#define EXT_AUXDDC_LUTINDEX_3 3
+#define EXT_AUXDDC_LUTINDEX_4 4
+#define EXT_AUXDDC_LUTINDEX_5 5
+#define EXT_AUXDDC_LUTINDEX_6 6
+#define EXT_AUXDDC_LUTINDEX_7 7
+#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
+
+typedef struct _EXT_DISPLAY_PATH
+{
+ USHORT usDeviceTag; //A bit vector to show what devices are supported
+ USHORT usDeviceACPIEnum; //16bit device ACPI id.
+ USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions
+ UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
+ UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
+ USHORT usExtEncoderObjId; //external encoder object id
+ USHORT usReserved[3];
+}EXT_DISPLAY_PATH;
+
+#define NUMBER_OF_UCHAR_FOR_GUID 16
+#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
+
+typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
+ EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
+ UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
+ UCHAR Reserved [7]; // for potential expansion
+}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
+
//Related definitions, all records are differnt but they have a commond header
typedef struct _ATOM_COMMON_RECORD_HEADER
{
@@ -2802,11 +3305,16 @@ typedef struct _ATOM_COMMON_RECORD_HEADER
#define ATOM_CONNECTOR_CF_RECORD_TYPE 11
#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
-#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
-#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
+#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
+#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
+#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table
+#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table
+#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
+#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
+
//Must be updated when new record type is added,equal to that record definition!
-#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE
+#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE
typedef struct _ATOM_I2C_RECORD
{
@@ -2819,7 +3327,7 @@ typedef struct _ATOM_HPD_INT_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
- UCHAR ucPluggged_PinState;
+ UCHAR ucPlugged_PinState;
}ATOM_HPD_INT_RECORD;
@@ -2916,6 +3424,16 @@ typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD
#define GPIO_PIN_STATE_ACTIVE_LOW 0x0
#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
+// Indexes to GPIO array in GLSync record
+#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0
+#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1
+#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2
+#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3
+#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4
+#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
+#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6
+#define ATOM_GPIO_INDEX_GLSYNC_MAX 7
+
typedef struct _ATOM_ENCODER_DVO_CF_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
@@ -2971,6 +3489,30 @@ typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
+typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
+}ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
+
+typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID
+}ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
+
+typedef struct _ATOM_OBJECT_LINK_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ USHORT usObjectID; //could be connector, encorder or other object in object.h
+}ATOM_OBJECT_LINK_RECORD;
+
+typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
+{
+ ATOM_COMMON_RECORD_HEADER sheader;
+ USHORT usReserved;
+}ATOM_CONNECTOR_REMOTE_CAP_RECORD;
+
/****************************************************************************/
// ASIC voltage data table
/****************************************************************************/
@@ -3006,6 +3548,19 @@ typedef struct _ATOM_VOLTAGE_FORMULA
UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
}ATOM_VOLTAGE_FORMULA;
+typedef struct _VOLTAGE_LUT_ENTRY
+{
+ USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code
+ USHORT usVoltageValue; // The corresponding Voltage Value, in mV
+}VOLTAGE_LUT_ENTRY;
+
+typedef struct _ATOM_VOLTAGE_FORMULA_V2
+{
+ UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
+ UCHAR ucReserved[3];
+ VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
+}ATOM_VOLTAGE_FORMULA_V2;
+
typedef struct _ATOM_VOLTAGE_CONTROL
{
UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
@@ -3034,12 +3589,26 @@ typedef struct _ATOM_VOLTAGE_OBJECT
ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
}ATOM_VOLTAGE_OBJECT;
+typedef struct _ATOM_VOLTAGE_OBJECT_V2
+{
+ UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
+ UCHAR ucSize; //Size of Object
+ ATOM_VOLTAGE_CONTROL asControl; //describ how to control
+ ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID
+}ATOM_VOLTAGE_OBJECT_V2;
+
typedef struct _ATOM_VOLTAGE_OBJECT_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
}ATOM_VOLTAGE_OBJECT_INFO;
+typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control
+}ATOM_VOLTAGE_OBJECT_INFO_V2;
+
typedef struct _ATOM_LEAKID_VOLTAGE
{
UCHAR ucLeakageId;
@@ -3101,6 +3670,68 @@ typedef struct _ATOM_POWER_SOURCE_INFO
#define POWER_SENSOR_GPIO 0x01
#define POWER_SENSOR_I2C 0x02
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ULONG ulBootUpEngineClock;
+ ULONG ulDentistVCOFreq;
+ ULONG ulBootUpUMAClock;
+ ULONG ulReserved1[8];
+ ULONG ulBootUpReqDisplayVector;
+ ULONG ulOtherDisplayMisc;
+ ULONG ulGPUCapInfo;
+ ULONG ulReserved2[3];
+ ULONG ulSystemConfig;
+ ULONG ulCPUCapInfo;
+ USHORT usMaxNBVoltage;
+ USHORT usMinNBVoltage;
+ USHORT usBootUpNBVoltage;
+ USHORT usExtDispConnInfoOffset;
+ UCHAR ucHtcTmpLmt;
+ UCHAR ucTjOffset;
+ UCHAR ucMemoryType;
+ UCHAR ucUMAChannelNumber;
+ ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
+ ULONG ulCSR_M3_ARB_CNTL_UVD[10];
+ ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
+ ULONG ulReserved3[42];
+ ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
+}ATOM_INTEGRATED_SYSTEM_INFO_V6;
+
+/**********************************************************************************************************************
+// ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
+//ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit.
+//ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
+//ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
+//ulReserved1[8] Reserved by now, must be 0x0.
+//ulBootUpReqDisplayVector VBIOS boot up display IDs
+// ATOM_DEVICE_CRT1_SUPPORT 0x0001
+// ATOM_DEVICE_CRT2_SUPPORT 0x0010
+// ATOM_DEVICE_DFP1_SUPPORT 0x0008
+// ATOM_DEVICE_DFP6_SUPPORT 0x0040
+// ATOM_DEVICE_DFP2_SUPPORT 0x0080
+// ATOM_DEVICE_DFP3_SUPPORT 0x0200
+// ATOM_DEVICE_DFP4_SUPPORT 0x0400
+// ATOM_DEVICE_DFP5_SUPPORT 0x0800
+// ATOM_DEVICE_LCD1_SUPPORT 0x0002
+//ulOtherDisplayMisc Other display related flags, not defined yet.
+//ulGPUCapInfo TBD
+//ulReserved2[3] must be 0x0 for the reserved.
+//ulSystemConfig TBD
+//ulCPUCapInfo TBD
+//usMaxNBVoltage High NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse.
+//usMinNBVoltage Low NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse.
+//usBootUpNBVoltage Boot up NB voltage in unit of mv.
+//ucHtcTmpLmt Bit [22:16] of D24F3x64 Thermal Control (HTC) Register.
+//ucTjOffset Bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed.
+//ucMemoryType [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
+//ucUMAChannelNumber System memory channel numbers.
+//usExtDispConnectionInfoOffset ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO offset relative to beginning of this table.
+//ulCSR_M3_ARB_CNTL_DEFAULT[10] Arrays with values for CSR M3 arbiter for default
+//ulCSR_M3_ARB_CNTL_UVD[10] Arrays with values for CSR M3 arbiter for UVD playback.
+//ulCSR_M3_ARB_CNTL_FS3D[10] Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
+**********************************************************************************************************************/
+
/**************************************************************************/
// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
//Memory SS Info Table
@@ -3149,16 +3780,66 @@ typedef struct _ATOM_ASIC_SS_ASSIGNMENT
UCHAR ucReserved[2];
}ATOM_ASIC_SS_ASSIGNMENT;
-//Define ucSpreadSpectrumType
+//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type.
+//SS is not required or enabled if a match is not found.
#define ASIC_INTERNAL_MEMORY_SS 1
#define ASIC_INTERNAL_ENGINE_SS 2
-#define ASIC_INTERNAL_UVD_SS 3
+#define ASIC_INTERNAL_UVD_SS 3
+#define ASIC_INTERNAL_SS_ON_TMDS 4
+#define ASIC_INTERNAL_SS_ON_HDMI 5
+#define ASIC_INTERNAL_SS_ON_LVDS 6
+#define ASIC_INTERNAL_SS_ON_DP 7
+#define ASIC_INTERNAL_SS_ON_DCPLL 8
-typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
+typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
+{
+ ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
+ //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
+ USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
+ USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
+ UCHAR ucClockIndication; //Indicate which clock source needs SS
+ UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
+ UCHAR ucReserved[2];
+}ATOM_ASIC_SS_ASSIGNMENT_V2;
+
+//ucSpreadSpectrumMode
+//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
+//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
+//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
+//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
+//#define ATOM_INTERNAL_SS_MASK 0x00000000
+//#define ATOM_EXTERNAL_SS_MASK 0x00000002
+
+typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
+{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
}ATOM_ASIC_INTERNAL_SS_INFO;
+typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only.
+}ATOM_ASIC_INTERNAL_SS_INFO_V2;
+
+typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
+{
+ ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
+ //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
+ USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
+ USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
+ UCHAR ucClockIndication; //Indicate which clock source needs SS
+ UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
+ UCHAR ucReserved[2];
+}ATOM_ASIC_SS_ASSIGNMENT_V3;
+
+typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only.
+}ATOM_ASIC_INTERNAL_SS_INFO_V3;
+
+
//==============================Scratch Pad Definition Portion===============================
#define ATOM_DEVICE_CONNECT_INFO_DEF 0
#define ATOM_ROM_LOCATION_DEF 1
@@ -3203,15 +3884,15 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S0_DFP2 0x00020000L
#define ATOM_S0_LCD1 0x00040000L
#define ATOM_S0_LCD2 0x00080000L
-#define ATOM_S0_TV2 0x00100000L
-#define ATOM_S0_DFP3 0x00200000L
-#define ATOM_S0_DFP4 0x00400000L
-#define ATOM_S0_DFP5 0x00800000L
+#define ATOM_S0_DFP6 0x00100000L
+#define ATOM_S0_DFP3 0x00200000L
+#define ATOM_S0_DFP4 0x00400000L
+#define ATOM_S0_DFP5 0x00800000L
-#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5
+#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with
- // the FAD/HDP reg access bug. Bit is read by DAL
+ // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
#define ATOM_S0_THERMAL_STATE_SHIFT 26
@@ -3253,8 +3934,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S0_DFP2b2 0x02
#define ATOM_S0_LCD1b2 0x04
#define ATOM_S0_LCD2b2 0x08
-#define ATOM_S0_TV2b2 0x10
-#define ATOM_S0_DFP3b2 0x20
+#define ATOM_S0_DFP6b2 0x10
+#define ATOM_S0_DFP3b2 0x20
+#define ATOM_S0_DFP4b2 0x40
+#define ATOM_S0_DFP5b2 0x80
+
#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
#define ATOM_S0_THERMAL_STATE_SHIFTb3 2
@@ -3271,29 +3955,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
-#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
-#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L
-#define ATOM_S2_TV1_DPMS_STATE 0x00040000L
-#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L
-#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L
-#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L
-#define ATOM_S2_TV2_DPMS_STATE 0x00400000L
-#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L
-#define ATOM_S2_CV_DPMS_STATE 0x01000000L
-#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L
-#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L
-#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L
-
-#define ATOM_S2_DFP_DPM_STATE ATOM_S2_DFP1_DPMS_STATE | ATOM_S2_DFP2_DPMS_STATE | ATOM_S2_DFP3_DPMS_STATE | ATOM_S2_DFP4_DPMS_STATE | ATOM_S2_DFP5_DPMS_STATE
-
-#define ATOM_S2_DEVICE_DPMS_STATE (ATOM_S2_CRT1_DPMS_STATE+ATOM_S2_LCD1_DPMS_STATE+ATOM_S2_TV1_DPMS_STATE+\
- ATOM_S2_DFP_DPMS_STATE+ATOM_S2_CRT2_DPMS_STATE+ATOM_S2_LCD2_DPMS_STATE+\
- ATOM_S2_TV2_DPMS_STATE+ATOM_S2_CV_DPMS_STATE
-
#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
+#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L
#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
@@ -3307,18 +3973,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
//Byte aligned defintion for BIOS usage
#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
-#define ATOM_S2_CRT1_DPMS_STATEb2 0x01
-#define ATOM_S2_LCD1_DPMS_STATEb2 0x02
-#define ATOM_S2_TV1_DPMS_STATEb2 0x04
-#define ATOM_S2_DFP1_DPMS_STATEb2 0x08
-#define ATOM_S2_CRT2_DPMS_STATEb2 0x10
-#define ATOM_S2_LCD2_DPMS_STATEb2 0x20
-#define ATOM_S2_TV2_DPMS_STATEb2 0x40
-#define ATOM_S2_DFP2_DPMS_STATEb2 0x80
-#define ATOM_S2_CV_DPMS_STATEb3 0x01
-#define ATOM_S2_DFP3_DPMS_STATEb3 0x02
-#define ATOM_S2_DFP4_DPMS_STATEb3 0x04
-#define ATOM_S2_DFP5_DPMS_STATEb3 0x08
+#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01
#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF
#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C
@@ -3334,14 +3989,14 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S3_DFP1_ACTIVE 0x00000008L
#define ATOM_S3_CRT2_ACTIVE 0x00000010L
#define ATOM_S3_LCD2_ACTIVE 0x00000020L
-#define ATOM_S3_TV2_ACTIVE 0x00000040L
+#define ATOM_S3_DFP6_ACTIVE 0x00000040L
#define ATOM_S3_DFP2_ACTIVE 0x00000080L
#define ATOM_S3_CV_ACTIVE 0x00000100L
#define ATOM_S3_DFP3_ACTIVE 0x00000200L
#define ATOM_S3_DFP4_ACTIVE 0x00000400L
#define ATOM_S3_DFP5_ACTIVE 0x00000800L
-#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL
+#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL
#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L
#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
@@ -3352,7 +4007,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
-#define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L
+#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L
#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
@@ -3361,6 +4016,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
+//Below two definitions are not supported in pplib, but in the old powerplay in DAL
#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
@@ -3371,7 +4027,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S3_DFP1_ACTIVEb0 0x08
#define ATOM_S3_CRT2_ACTIVEb0 0x10
#define ATOM_S3_LCD2_ACTIVEb0 0x20
-#define ATOM_S3_TV2_ACTIVEb0 0x40
+#define ATOM_S3_DFP6_ACTIVEb0 0x40
#define ATOM_S3_DFP2_ACTIVEb0 0x80
#define ATOM_S3_CV_ACTIVEb1 0x01
#define ATOM_S3_DFP3_ACTIVEb1 0x02
@@ -3386,7 +4042,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
-#define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40
+#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40
#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
@@ -3395,10 +4051,6 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF
-#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20
-#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
-#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80
-
// BIOS_4_SCRATCH Definition
#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
@@ -3416,14 +4068,14 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S5_DOS_REQ_DFP1b0 0x08
#define ATOM_S5_DOS_REQ_CRT2b0 0x10
#define ATOM_S5_DOS_REQ_LCD2b0 0x20
-#define ATOM_S5_DOS_REQ_TV2b0 0x40
+#define ATOM_S5_DOS_REQ_DFP6b0 0x40
#define ATOM_S5_DOS_REQ_DFP2b0 0x80
#define ATOM_S5_DOS_REQ_CVb1 0x01
#define ATOM_S5_DOS_REQ_DFP3b1 0x02
#define ATOM_S5_DOS_REQ_DFP4b1 0x04
#define ATOM_S5_DOS_REQ_DFP5b1 0x08
-#define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF
+#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF
#define ATOM_S5_DOS_REQ_CRT1 0x0001
#define ATOM_S5_DOS_REQ_LCD1 0x0002
@@ -3431,12 +4083,12 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S5_DOS_REQ_DFP1 0x0008
#define ATOM_S5_DOS_REQ_CRT2 0x0010
#define ATOM_S5_DOS_REQ_LCD2 0x0020
-#define ATOM_S5_DOS_REQ_TV2 0x0040
+#define ATOM_S5_DOS_REQ_DFP6 0x0040
#define ATOM_S5_DOS_REQ_DFP2 0x0080
#define ATOM_S5_DOS_REQ_CV 0x0100
-#define ATOM_S5_DOS_REQ_DFP3 0x0200
-#define ATOM_S5_DOS_REQ_DFP4 0x0400
-#define ATOM_S5_DOS_REQ_DFP5 0x0800
+#define ATOM_S5_DOS_REQ_DFP3 0x0200
+#define ATOM_S5_DOS_REQ_DFP4 0x0400
+#define ATOM_S5_DOS_REQ_DFP5 0x0800
#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
@@ -3470,7 +4122,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S6_ACC_REQ_DFP1 0x00080000L
#define ATOM_S6_ACC_REQ_CRT2 0x00100000L
#define ATOM_S6_ACC_REQ_LCD2 0x00200000L
-#define ATOM_S6_ACC_REQ_TV2 0x00400000L
+#define ATOM_S6_ACC_REQ_DFP6 0x00400000L
#define ATOM_S6_ACC_REQ_DFP2 0x00800000L
#define ATOM_S6_ACC_REQ_CV 0x01000000L
#define ATOM_S6_ACC_REQ_DFP3 0x02000000L
@@ -3505,12 +4157,12 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_S6_ACC_REQ_DFP1b2 0x08
#define ATOM_S6_ACC_REQ_CRT2b2 0x10
#define ATOM_S6_ACC_REQ_LCD2b2 0x20
-#define ATOM_S6_ACC_REQ_TV2b2 0x40
+#define ATOM_S6_ACC_REQ_DFP6b2 0x40
#define ATOM_S6_ACC_REQ_DFP2b2 0x80
#define ATOM_S6_ACC_REQ_CVb3 0x01
-#define ATOM_S6_ACC_REQ_DFP3b3 0x02
-#define ATOM_S6_ACC_REQ_DFP4b3 0x04
-#define ATOM_S6_ACC_REQ_DFP5b3 0x08
+#define ATOM_S6_ACC_REQ_DFP3b3 0x02
+#define ATOM_S6_ACC_REQ_DFP4b3 0x04
+#define ATOM_S6_ACC_REQ_DFP5b3 0x08
#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
@@ -3615,11 +4267,17 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
/****************************************************************************/
// Macros used by driver
+#ifdef __cplusplus
+#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
+#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
+#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
+#else // not __cplusplus
#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
+#endif // __cplusplus
#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
@@ -3631,11 +4289,6 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
#define ATOM_SRC_DAC1 0
#define ATOM_SRC_DAC2 0x80
-
-#ifdef UEFI_BUILD
- #define USHORT UTEMP
-#endif
-
typedef struct _MEMORY_PLLINIT_PARAMETERS
{
ULONG ulTargetMemoryClock; //In 10Khz unit
@@ -3706,6 +4359,15 @@ typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
UCHAR ucPadding[2];
}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
+typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
+{
+ USHORT usHight; // Image Hight
+ USHORT usWidth; // Image Width
+ UCHAR ucSurface; // Surface 1 or 2
+ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
+ USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.
+}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
+
typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
{
ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
@@ -3906,6 +4568,7 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE
#define QIMONDA INFINEON
#define PROMOS MOSEL
+#define KRETON INFINEON
/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
@@ -4046,11 +4709,46 @@ typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
UCHAR uctCKRSE; //
UCHAR uctCKRSX; //
UCHAR uctFAW32; //
- UCHAR ucReserved1; //
- UCHAR ucReserved2; //
+ UCHAR ucMR5lo; //
+ UCHAR ucMR5hi; //
UCHAR ucTerminator;
}ATOM_MEMORY_TIMING_FORMAT_V1;
+typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
+{
+ ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
+ USHORT usMRS; // mode register
+ USHORT usEMRS; // extended mode register
+ UCHAR ucCL; // CAS latency
+ UCHAR ucWL; // WRITE Latency
+ UCHAR uctRAS; // tRAS
+ UCHAR uctRC; // tRC
+ UCHAR uctRFC; // tRFC
+ UCHAR uctRCDR; // tRCDR
+ UCHAR uctRCDW; // tRCDW
+ UCHAR uctRP; // tRP
+ UCHAR uctRRD; // tRRD
+ UCHAR uctWR; // tWR
+ UCHAR uctWTR; // tWTR
+ UCHAR uctPDIX; // tPDIX
+ UCHAR uctFAW; // tFAW
+ UCHAR uctAOND; // tAOND
+ UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
+////////////////////////////////////GDDR parameters///////////////////////////////////
+ UCHAR uctCCDL; //
+ UCHAR uctCRCRL; //
+ UCHAR uctCRCWL; //
+ UCHAR uctCKE; //
+ UCHAR uctCKRSE; //
+ UCHAR uctCKRSX; //
+ UCHAR uctFAW32; //
+ UCHAR ucMR4lo; //
+ UCHAR ucMR4hi; //
+ UCHAR ucMR5lo; //
+ UCHAR ucMR5hi; //
+ UCHAR ucTerminator;
+ UCHAR ucReserved;
+}ATOM_MEMORY_TIMING_FORMAT_V2;
typedef struct _ATOM_MEMORY_FORMAT
{
@@ -4174,6 +4872,39 @@ typedef struct _ATOM_VRAM_MODULE_V5
ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
}ATOM_VRAM_MODULE_V5;
+typedef struct _ATOM_VRAM_MODULE_V6
+{
+ ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
+ USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
+ USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
+ // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
+ USHORT usReserved;
+ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
+ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
+ UCHAR ucChannelNum; // Number of channels present in this module config
+ UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
+ UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
+ UCHAR ucFlag; // To enable/disable functionalities based on memory type
+ UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
+ UCHAR ucVREFI; // board dependent parameter
+ UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
+ UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
+ UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
+ // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
+ UCHAR ucReserved[3];
+
+//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
+ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
+ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
+ UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
+ UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
+ UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
+ UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
+ ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
+}ATOM_VRAM_MODULE_V6;
+
+
+
typedef struct _ATOM_VRAM_INFO_V2
{
ATOM_COMMON_TABLE_HEADER sHeader;
@@ -4467,6 +5198,16 @@ typedef struct _ATOM_DISP_OUT_INFO
ASIC_ENCODER_INFO asEncoderInfo[1];
}ATOM_DISP_OUT_INFO;
+typedef struct _ATOM_DISP_OUT_INFO_V2
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+ USHORT ptrTransmitterInfo;
+ USHORT ptrEncoderInfo;
+ USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
+ ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
+ ASIC_ENCODER_INFO asEncoderInfo[1];
+}ATOM_DISP_OUT_INFO_V2;
+
// DispDevicePriorityInfo
typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
{
@@ -4489,6 +5230,21 @@ typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
UCHAR ucReserved;
}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
+//ProcessAuxChannelTransactionTable
+typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
+{
+ USHORT lpAuxRequest;
+ USHORT lpDataOut;
+ UCHAR ucChannelID;
+ union
+ {
+ UCHAR ucReplyStatus;
+ UCHAR ucDelay;
+ };
+ UCHAR ucDataOutLen;
+ UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
+}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
+
#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
//GetSinkType
@@ -4509,6 +5265,7 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS
// ucAction
#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
+/* obselete */
#define ATOM_DP_ACTION_TRAINING_START 0x02
#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03
#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04
@@ -4524,7 +5281,7 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS
#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04
#define ATOM_DP_CONFIG_LINK_A 0x00
#define ATOM_DP_CONFIG_LINK_B 0x04
-
+/* /obselete */
#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
// DP_TRAINING_TABLE
@@ -4539,8 +5296,8 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS
#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
-#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
-
+#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
+#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84)
typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
{
@@ -4562,7 +5319,38 @@ typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
//ucFlag
#define HW_I2C_WRITE 1
#define HW_I2C_READ 0
+#define I2C_2BYTE_ADDR 0x02
+typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
+{
+ UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
+ UCHAR ucReserved[3];
+}SET_HWBLOCK_INSTANCE_PARAMETER_V2;
+
+#define HWBLKINST_INSTANCE_MASK 0x07
+#define HWBLKINST_HWBLK_MASK 0xF0
+#define HWBLKINST_HWBLK_SHIFT 0x04
+
+//ucHWBlock
+#define SELECT_DISP_ENGINE 0
+#define SELECT_DISP_PLL 1
+#define SELECT_DCIO_UNIPHY_LINK0 2
+#define SELECT_DCIO_UNIPHY_LINK1 3
+#define SELECT_DCIO_IMPCAL 4
+#define SELECT_DCIO_DIG 6
+#define SELECT_CRTC_PIXEL_RATE 7
+
+/****************************************************************************/
+//Portion VI: Definitinos for vbios MC scratch registers that driver used
+/****************************************************************************/
+
+#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000
+#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000
+#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000
+#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000
+#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000
+#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000
+#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000
/****************************************************************************/
//Portion VI: Definitinos being oboselete
@@ -5226,6 +6014,50 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
+//#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
+//#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
+//#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
+//#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
+//#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
+
+#define ATOM_S6_ACC_REQ_TV2 0x00400000L
+#define ATOM_DEVICE_TV2_INDEX 0x00000006
+#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX)
+#define ATOM_S0_TV2 0x00100000L
+#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE
+#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE
+
+//
+#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
+#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L
+#define ATOM_S2_TV1_DPMS_STATE 0x00040000L
+#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L
+#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L
+#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L
+#define ATOM_S2_TV2_DPMS_STATE 0x00400000L
+#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L
+#define ATOM_S2_CV_DPMS_STATE 0x01000000L
+#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L
+#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L
+#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L
+
+#define ATOM_S2_CRT1_DPMS_STATEb2 0x01
+#define ATOM_S2_LCD1_DPMS_STATEb2 0x02
+#define ATOM_S2_TV1_DPMS_STATEb2 0x04
+#define ATOM_S2_DFP1_DPMS_STATEb2 0x08
+#define ATOM_S2_CRT2_DPMS_STATEb2 0x10
+#define ATOM_S2_LCD2_DPMS_STATEb2 0x20
+#define ATOM_S2_TV2_DPMS_STATEb2 0x40
+#define ATOM_S2_DFP2_DPMS_STATEb2 0x80
+#define ATOM_S2_CV_DPMS_STATEb3 0x01
+#define ATOM_S2_DFP3_DPMS_STATEb3 0x02
+#define ATOM_S2_DFP4_DPMS_STATEb3 0x04
+#define ATOM_S2_DFP5_DPMS_STATEb3 0x08
+
+#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20
+#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
+#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80
+
/*********************************************************************************/
#pragma pack() // BIOS data must use byte aligment
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