xf86-video-intel: 2 commits - src/i965_render.c

[Chris Wilson]

 src/i965_render.c |   37 +++++++++++++++++--------------------
 1 file changed, 17 insertions(+), 20 deletions(-)

New commits:
commit 27e33928f87ecb806d1f8c459d4a4ada76b0e30e
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Dec 7 20:42:24 2010 +0000

    i965: Mark sure we mark reused render targets as dirty
    
    ... or else we may forget to flush them again.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/i965_render.c b/src/i965_render.c
index 3141394..ebaa10e 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1123,9 +1123,19 @@ i965_set_picture_surface_state(intel_screen_private *intel,
 {
 	struct intel_pixmap *priv = intel_get_pixmap_private(pixmap);
 	struct brw_surface_state *ss;
+	uint32_t write_domain, read_domains;
 	int offset;
 
 	if (is_dst) {
+		write_domain = I915_GEM_DOMAIN_RENDER;
+		read_domains = I915_GEM_DOMAIN_RENDER;
+	} else {
+		write_domain = 0;
+		read_domains = I915_GEM_DOMAIN_SAMPLER;
+	}
+	intel_batch_mark_pixmap_domains(intel, priv,
+					read_domains, write_domain);
+	if (is_dst) {
 		if (priv->dst_bound)
 			return priv->dst_bound;
 	} else {
@@ -1159,25 +1169,12 @@ i965_set_picture_surface_state(intel_screen_private *intel,
 	ss->ss3.tile_walk = 0;	/* Tiled X */
 	ss->ss3.tiled_surface = intel_pixmap_tiled(pixmap) ? 1 : 0;
 
-	if (priv->bo != NULL) {
-		uint32_t write_domain, read_domains;
-
-		if (is_dst) {
-			write_domain = I915_GEM_DOMAIN_RENDER;
-			read_domains = I915_GEM_DOMAIN_RENDER;
-		} else {
-			write_domain = 0;
-			read_domains = I915_GEM_DOMAIN_SAMPLER;
-		}
-
-		intel_batch_mark_pixmap_domains(intel, priv, read_domains, write_domain);
-		dri_bo_emit_reloc(intel->surface_bo,
-				  read_domains, write_domain,
-				  0,
-				  intel->surface_used +
-				  offsetof(struct brw_surface_state, ss1),
-				  priv->bo);
-	}
+	dri_bo_emit_reloc(intel->surface_bo,
+			  read_domains, write_domain,
+			  0,
+			  intel->surface_used +
+			  offsetof(struct brw_surface_state, ss1),
+			  priv->bo);
 
 	offset = intel->surface_used;
 	intel->surface_used += sizeof(struct brw_surface_state_padded);
commit 03e8351179b1c25d219842ef3e01ee8e176f594f
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Dec 7 19:27:57 2010 +0000

    i965: The RenderCache flush after every glyph is required for compiz
    
    ... now who can explain why.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/i965_render.c b/src/i965_render.c
index fe14cd6..3141394 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1927,7 +1927,7 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
 	if (INTEL_INFO(intel)->gen < 50) {
 	    /* XXX OMG! */
 	    i965_vertex_flush(intel);
-	    OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
+	    OUT_BATCH(MI_FLUSH);
 	}
 
 	intel_batch_end_atomic(scrn);