xf86-video-intel: 3 commits - src/i965_render.c src/intel.h
Chris Wilson
ickle at kemper.freedesktop.org
Mon Dec 6 06:21:19 PST 2010
src/i965_render.c | 223 ++++++++++++++++++++++++++++++++++--------------------
src/intel.h | 11 ++
2 files changed, 154 insertions(+), 80 deletions(-)
New commits:
commit f3a47d7f235d18e4529e3898a48673c7c3cbd489
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Mon Dec 6 14:11:05 2010 +0000
snb: Cache pixmap binding locations
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i965_render.c b/src/i965_render.c
index 6afbc4e..8574c8e 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1125,6 +1125,14 @@ i965_set_picture_surface_state(intel_screen_private *intel,
struct brw_surface_state *ss;
int offset;
+ if (is_dst) {
+ if (priv->dst_bound)
+ return priv->dst_bound;
+ } else {
+ if (priv->src_bound)
+ return priv->src_bound;
+ }
+
ss = (struct brw_surface_state *)
(intel->surface_data + intel->surface_used);
@@ -1174,6 +1182,11 @@ i965_set_picture_surface_state(intel_screen_private *intel,
offset = intel->surface_used;
intel->surface_used += sizeof(struct brw_surface_state_padded);
+ if (is_dst)
+ priv->dst_bound = offset;
+ else
+ priv->src_bound = offset;
+
return offset;
}
@@ -1515,6 +1528,8 @@ static Bool i965_composite_check_aperture(ScrnInfoPtr scrn)
static void i965_surface_flush(struct intel_screen_private *intel)
{
+ struct intel_pixmap *priv;
+
drm_intel_bo_subdata(intel->surface_bo,
0, intel->surface_used,
intel->surface_data);
@@ -1531,6 +1546,9 @@ static void i965_surface_flush(struct intel_screen_private *intel)
intel->surface_bo =
drm_intel_bo_alloc(intel->bufmgr, "surface data",
sizeof(intel->surface_data), 4096);
+
+ list_foreach_entry(priv, struct intel_pixmap, &intel->batch_pixmaps, batch)
+ priv->dst_bound = priv->src_bound = 0;
}
Bool
diff --git a/src/intel.h b/src/intel.h
index cabc316..dc88d74 100644
--- a/src/intel.h
+++ b/src/intel.h
@@ -178,6 +178,7 @@ struct intel_pixmap {
struct list flush, batch, in_flight;
+ uint16_t src_bound, dst_bound;
uint16_t stride;
uint8_t tiling;
int8_t busy :2;
commit 4d48fed9aa0c3c7b84e74b4f72f298f580a8973c
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Mon Dec 6 13:50:43 2010 +0000
snb: Cache state between composite ops
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i965_render.c b/src/i965_render.c
index accd5a2..6afbc4e 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1921,6 +1921,14 @@ void i965_batch_commit_notify(intel_screen_private *intel)
intel->needs_3d_invariant = TRUE;
intel->last_floats_per_vertex = 0;
intel->vertex_index = 0;
+
+ intel->gen6_render_state.num_sf_outputs = 0;
+ intel->gen6_render_state.samplers = NULL;
+ intel->gen6_render_state.blend = -1;
+ intel->gen6_render_state.kernel = NULL;
+ intel->gen6_render_state.vertex_size = 0;
+ intel->gen6_render_state.vertex_type = 0;
+ intel->gen6_render_state.drawrect = -1;
}
/**
@@ -2234,29 +2242,42 @@ gen6_composite_urb(intel_screen_private *intel)
static void
gen6_composite_cc_state_pointers(intel_screen_private *intel,
- drm_intel_bo *blend_state_bo,
- uint32_t blend_state_offset,
- drm_intel_bo *depth_stencil_state_bo,
- uint32_t depth_stencil_state_offset,
- drm_intel_bo *cc_state_bo,
- uint32_t cc_state_offset)
+ drm_intel_bo *blend_bo, uint32_t blend_offset,
+ drm_intel_bo *depth_bo, uint32_t depth_offset,
+ drm_intel_bo *cc_bo, uint32_t cc_offset)
{
+ if (intel->gen6_render_state.blend == blend_offset)
+ return;
+
+ intel->gen6_render_state.blend = blend_offset;
+
OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
- OUT_RELOC(blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, blend_state_offset | 1);
- OUT_RELOC(depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, depth_stencil_state_offset | 1);
- OUT_RELOC(cc_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, cc_state_offset | 1);
+ OUT_RELOC(blend_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ blend_offset | 1);
+ OUT_RELOC(depth_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ depth_offset | 1);
+ OUT_RELOC(cc_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ cc_offset | 1);
}
static void
gen6_composite_sampler_state_pointers(intel_screen_private *intel,
- drm_intel_bo *ps_sampler_state_bo)
+ drm_intel_bo *bo)
{
+ if (intel->gen6_render_state.samplers == bo)
+ return;
+
+ intel->gen6_render_state.samplers = bo;
+
OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
- GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
- (4 - 2));
+ GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
+ (4 - 2));
OUT_BATCH(0); /* VS */
OUT_BATCH(0); /* GS */
- OUT_RELOC(ps_sampler_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
}
static void
@@ -2311,6 +2332,11 @@ gen6_composite_sf_state(intel_screen_private *intel,
{
int num_sf_outputs = has_mask ? 2 : 1;
+ if (intel->gen6_render_state.num_sf_outputs == num_sf_outputs)
+ return;
+
+ intel->gen6_render_state.num_sf_outputs = num_sf_outputs;
+
OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
(1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
@@ -2338,11 +2364,16 @@ gen6_composite_sf_state(intel_screen_private *intel,
static void
gen6_composite_wm_state(intel_screen_private *intel,
Bool has_mask,
- drm_intel_bo *kernel_bo)
+ drm_intel_bo *bo)
{
int num_surfaces = has_mask ? 3 : 2;
int num_sf_outputs = has_mask ? 2 : 1;
+ if (intel->gen6_render_state.kernel == bo)
+ return;
+
+ intel->gen6_render_state.kernel = bo;
+
/* disable WM constant buffer */
OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (5 - 2));
OUT_BATCH(0);
@@ -2351,7 +2382,7 @@ gen6_composite_wm_state(intel_screen_private *intel,
OUT_BATCH(0);
OUT_BATCH(GEN6_3DSTATE_WM | (9 - 2));
- OUT_RELOC(kernel_bo,
+ OUT_RELOC(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
0);
OUT_BATCH((1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
@@ -2399,10 +2430,19 @@ gen6_composite_depth_buffer_state(intel_screen_private *intel)
static void
gen6_composite_drawing_rectangle(intel_screen_private *intel,
PixmapPtr dest)
+
{
+ uint32_t dw =
+ DRAW_YMAX(dest->drawable.height - 1) |
+ DRAW_XMAX(dest->drawable.width - 1);
+
+ if (intel->gen6_render_state.drawrect == dw)
+ return;
+ intel->gen6_render_state.drawrect = dw;
+
OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
OUT_BATCH(0x00000000); /* ymin, xmin */
- OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) | DRAW_XMAX(dest->drawable.width - 1)); /* ymax, xmax */
+ OUT_BATCH(dw); /* ymax, xmax */
OUT_BATCH(0x00000000); /* yorigin, xorigin */
}
@@ -2422,6 +2462,13 @@ gen6_composite_vertex_element_state(intel_screen_private *intel,
uint32_t w_component;
uint32_t src_format;
+ if (intel->gen6_render_state.vertex_size == nelem &&
+ intel->gen6_render_state.vertex_type == selem)
+ return;
+
+ intel->gen6_render_state.vertex_size = nelem;
+ intel->gen6_render_state.vertex_type = selem;
+
if (is_affine) {
src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
w_component = BRW_VFCOMPONENT_STORE_1_FLT;
@@ -2552,6 +2599,14 @@ gen6_render_state_init(ScrnInfoPtr scrn)
int i, j, k, l, m;
drm_intel_bo *border_color_bo;
+ intel->gen6_render_state.num_sf_outputs = 0;
+ intel->gen6_render_state.samplers = NULL;
+ intel->gen6_render_state.blend = -1;
+ intel->gen6_render_state.kernel = NULL;
+ intel->gen6_render_state.vertex_size = 0;
+ intel->gen6_render_state.vertex_type = 0;
+ intel->gen6_render_state.drawrect = -1;
+
if (intel->gen4_render_state == NULL)
intel->gen4_render_state = calloc(sizeof(*render_state), 1);
diff --git a/src/intel.h b/src/intel.h
index 97fc497..cabc316 100644
--- a/src/intel.h
+++ b/src/intel.h
@@ -421,6 +421,16 @@ typedef struct intel_screen_private {
uint32_t dst_format;
} i915_render_state;
+ struct {
+ int num_sf_outputs;
+ int vertex_size;
+ int vertex_type;
+ int drawrect;
+ uint32_t blend;
+ dri_bo *samplers;
+ dri_bo *kernel;
+ } gen6_render_state;
+
uint32_t prim_offset;
void (*prim_emit)(PixmapPtr dest,
int srcX, int srcY,
commit a58e5a1bdf10be3b96ecaa3d5e3ee288eab1063f
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Mon Dec 6 13:34:53 2010 +0000
snb: Emit more invariants only once
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i965_render.c b/src/i965_render.c
index 75b6eb6..accd5a2 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -2175,10 +2175,8 @@ gen6_composite_create_depth_stencil_state(ScrnInfoPtr scrn)
}
static void
-gen6_composite_invarient_states(ScrnInfoPtr scrn)
+gen6_composite_invariant_states(intel_screen_private *intel)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
@@ -2195,10 +2193,8 @@ gen6_composite_invarient_states(ScrnInfoPtr scrn)
}
static void
-gen6_composite_state_base_address(ScrnInfoPtr scrn)
+gen6_composite_state_base_address(intel_screen_private *intel)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
OUT_BATCH(BRW_STATE_BASE_ADDRESS | (10 - 2));
OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state base address */
intel->surface_reloc = intel->batch_used;
@@ -2214,9 +2210,9 @@ gen6_composite_state_base_address(ScrnInfoPtr scrn)
}
static void
-gen6_composite_viewport_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *cc_vp_bo)
+gen6_composite_viewport_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *cc_vp_bo)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
@@ -2227,10 +2223,8 @@ gen6_composite_viewport_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *cc_vp_bo)
}
static void
-gen6_composite_urb(ScrnInfoPtr scrn)
+gen6_composite_urb(intel_screen_private *intel)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
(24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
@@ -2239,16 +2233,14 @@ gen6_composite_urb(ScrnInfoPtr scrn)
}
static void
-gen6_composite_cc_state_pointers(ScrnInfoPtr scrn,
- drm_intel_bo *blend_state_bo,
- uint32_t blend_state_offset,
- drm_intel_bo *depth_stencil_state_bo,
- uint32_t depth_stencil_state_offset,
- drm_intel_bo *cc_state_bo,
- uint32_t cc_state_offset)
+gen6_composite_cc_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *blend_state_bo,
+ uint32_t blend_state_offset,
+ drm_intel_bo *depth_stencil_state_bo,
+ uint32_t depth_stencil_state_offset,
+ drm_intel_bo *cc_state_bo,
+ uint32_t cc_state_offset)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
OUT_RELOC(blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, blend_state_offset | 1);
OUT_RELOC(depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, depth_stencil_state_offset | 1);
@@ -2256,10 +2248,9 @@ gen6_composite_cc_state_pointers(ScrnInfoPtr scrn,
}
static void
-gen6_composite_sampler_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *ps_sampler_state_bo)
+gen6_composite_sampler_state_pointers(intel_screen_private *intel,
+ drm_intel_bo *ps_sampler_state_bo)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
(4 - 2));
@@ -2268,18 +2259,16 @@ gen6_composite_sampler_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *ps_sampler
OUT_RELOC(ps_sampler_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
}
-static void
-gen6_composite_vs_state(ScrnInfoPtr scrn)
+static void
+gen6_composite_vs_state(intel_screen_private *intel)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
/* disable VS constant buffer */
OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
-
+
OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
OUT_BATCH(0); /* without VS kernel */
OUT_BATCH(0);
@@ -2288,18 +2277,16 @@ gen6_composite_vs_state(ScrnInfoPtr scrn)
OUT_BATCH(0); /* pass-through */
}
-static void
-gen6_composite_gs_state(ScrnInfoPtr scrn)
+static void
+gen6_composite_gs_state(intel_screen_private *intel)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
/* disable GS constant buffer */
OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
-
+
OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
OUT_BATCH(0); /* without GS kernel */
OUT_BATCH(0);
@@ -2309,21 +2296,19 @@ gen6_composite_gs_state(ScrnInfoPtr scrn)
OUT_BATCH(0); /* pass-through */
}
-static void
-gen6_composite_clip_state(ScrnInfoPtr scrn)
+static void
+gen6_composite_clip_state(intel_screen_private *intel)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0); /* pass-through */
OUT_BATCH(0);
}
-static void
-gen6_composite_sf_state(ScrnInfoPtr scrn, Bool has_mask)
+static void
+gen6_composite_sf_state(intel_screen_private *intel,
+ Bool has_mask)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
int num_sf_outputs = has_mask ? 2 : 1;
OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
@@ -2350,10 +2335,11 @@ gen6_composite_sf_state(ScrnInfoPtr scrn, Bool has_mask)
OUT_BATCH(0); /* DW19 */
}
-static void
-gen6_composite_wm_state(ScrnInfoPtr scrn, Bool has_mask, drm_intel_bo *kernel_bo)
+static void
+gen6_composite_wm_state(intel_screen_private *intel,
+ Bool has_mask,
+ drm_intel_bo *kernel_bo)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
int num_surfaces = has_mask ? 3 : 2;
int num_sf_outputs = has_mask ? 2 : 1;
@@ -2373,19 +2359,17 @@ gen6_composite_wm_state(ScrnInfoPtr scrn, Bool has_mask, drm_intel_bo *kernel_bo
OUT_BATCH(0);
OUT_BATCH((6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
OUT_BATCH(((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
- GEN6_3DSTATE_WM_DISPATCH_ENABLE |
- GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
+ GEN6_3DSTATE_WM_DISPATCH_ENABLE |
+ GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
- GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
+ GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
OUT_BATCH(0);
OUT_BATCH(0);
}
static void
-gen6_composite_binding_table_pointers(ScrnInfoPtr scrn)
+gen6_composite_binding_table_pointers(intel_screen_private *intel)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
/* Binding table pointers */
OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS |
GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
@@ -2397,10 +2381,8 @@ gen6_composite_binding_table_pointers(ScrnInfoPtr scrn)
}
static void
-gen6_composite_depth_buffer_state(ScrnInfoPtr scrn)
+gen6_composite_depth_buffer_state(intel_screen_private *intel)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
(BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
@@ -2415,10 +2397,9 @@ gen6_composite_depth_buffer_state(ScrnInfoPtr scrn)
}
static void
-gen6_composite_drawing_rectangle(ScrnInfoPtr scrn, PixmapPtr dest)
+gen6_composite_drawing_rectangle(intel_screen_private *intel,
+ PixmapPtr dest)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
OUT_BATCH(0x00000000); /* ymin, xmin */
OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) | DRAW_XMAX(dest->drawable.width - 1)); /* ymax, xmax */
@@ -2426,9 +2407,10 @@ gen6_composite_drawing_rectangle(ScrnInfoPtr scrn, PixmapPtr dest)
}
static void
-gen6_composite_vertex_element_state(ScrnInfoPtr scrn, Bool has_mask, Bool is_affine)
+gen6_composite_vertex_element_state(intel_screen_private *intel,
+ Bool has_mask,
+ Bool is_affine)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
/*
* vertex data in vertex buffer
* position: (x, y)
@@ -2521,37 +2503,45 @@ gen6_emit_composite_state(ScrnInfoPtr scrn)
drm_intel_bo *ps_sampler_state_bo = render_state->ps_sampler_state_bo[src_filter][src_extend][mask_filter][mask_extend];
intel->needs_render_state_emit = FALSE;
- IntelEmitInvarientState(scrn);
- intel->last_3d = LAST_3D_RENDER;
+ if (intel->needs_3d_invariant) {
+ gen6_composite_invariant_states(intel);
+ gen6_composite_viewport_state_pointers(intel,
+ render_state->cc_vp_bo);
+ gen6_composite_urb(intel);
+
+ gen6_composite_vs_state(intel);
+ gen6_composite_gs_state(intel);
+ gen6_composite_clip_state(intel);
+ gen6_composite_depth_buffer_state(intel);
+
+ intel->needs_3d_invariant = FALSE;
+ }
i965_get_blend_cntl(op,
mask_picture,
dest_picture->format,
&src_blend,
&dst_blend);
- assert(intel->in_batch_atomic);
- gen6_composite_invarient_states(scrn);
+
if (intel->surface_reloc == 0)
- gen6_composite_state_base_address(scrn);
- gen6_composite_viewport_state_pointers(scrn, render_state->cc_vp_bo);
- gen6_composite_urb(scrn);
- gen6_composite_cc_state_pointers(scrn,
+ gen6_composite_state_base_address(intel);
+
+ gen6_composite_cc_state_pointers(intel,
render_state->gen6_blend_bo,
((src_blend * BRW_BLENDFACTOR_COUNT) + dst_blend) * GEN6_BLEND_STATE_PADDED_SIZE,
render_state->gen6_depth_stencil_bo,
0,
render_state->cc_state_bo,
0);
- gen6_composite_sampler_state_pointers(scrn, ps_sampler_state_bo);
- gen6_composite_vs_state(scrn);
- gen6_composite_gs_state(scrn);
- gen6_composite_clip_state(scrn);
- gen6_composite_sf_state(scrn, mask != 0);
- gen6_composite_wm_state(scrn, mask != 0, render_state->wm_kernel_bo[composite_op->wm_kernel]);
- gen6_composite_binding_table_pointers(scrn);
- gen6_composite_depth_buffer_state(scrn);
- gen6_composite_drawing_rectangle(scrn, dest);
- gen6_composite_vertex_element_state(scrn, mask != 0, is_affine);
+ gen6_composite_sampler_state_pointers(intel, ps_sampler_state_bo);
+ gen6_composite_sf_state(intel, mask != 0);
+ gen6_composite_wm_state(intel,
+ mask != 0,
+ render_state->wm_kernel_bo[composite_op->wm_kernel]);
+ gen6_composite_binding_table_pointers(intel);
+
+ gen6_composite_drawing_rectangle(intel, dest);
+ gen6_composite_vertex_element_state(intel, mask != 0, is_affine);
}
static void
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