xf86-video-ati: Branch 'evergreen_accel' - 2 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Aug 23 15:59:01 PDT 2010
src/evergreen_accel.c | 22 ++--
src/evergreen_exa.c | 164 +++++++++++++++---------------------
src/evergreen_textured_videofuncs.c | 122 ++++++++++----------------
src/r600_exa.c | 38 ++++----
src/r600_textured_videofuncs.c | 6 -
src/r6xx_accel.c | 20 ++--
src/radeon.h | 25 +++--
src/radeon_exa_shared.c | 50 ++++++----
src/radeon_exa_shared.h | 4
src/radeon_kms.c | 22 +++-
src/radeon_vbo.c | 38 +++-----
src/radeon_vbo.h | 40 ++++----
12 files changed, 266 insertions(+), 285 deletions(-)
New commits:
commit f170dddd3538a587f2363ef5fa10a4b484e762da
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Aug 23 18:58:12 2010 -0400
evergreen: use vbo pool for constant buffers
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index 31e460d..1b40aca 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -1062,6 +1062,7 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size)
radeon_ib_discard(pScrn);
radeon_cs_flush_indirect(pScrn);
radeon_vb_discard(pScrn, &accel_state->vbo);
+ radeon_vb_discard(pScrn, &accel_state->cbuf);
return;
}
@@ -1093,6 +1094,7 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size)
accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
accel_state->vbo.vb_start_op = -1;
+ accel_state->cbuf.vb_start_op = -1;
accel_state->ib_reset_op = 0;
}
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 434516b..7b2a65e 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -158,7 +158,6 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_config_t cb_conf;
shader_config_t vs_conf, ps_conf;
int pmask = 0;
- int ret;
uint32_t a, r, g, b;
float *ps_alu_consts;
const_config_t ps_const_conf;
@@ -193,53 +192,8 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
CLEAR (ps_conf);
CLEAR (ps_const_conf);
- ps_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
- RADEON_GEM_DOMAIN_GTT, 0);
- if (ps_const_conf.bo == NULL)
- RADEON_FALLBACK(("ps const buffer alloc failed\n"));
- ret = radeon_bo_map(ps_const_conf.bo, 0);
- if (ret)
- RADEON_FALLBACK(("ps const buffer map failed\n"));
-
- /* PS alu constants */
- ps_const_conf.size_bytes = 256;
- ps_const_conf.const_addr = 0;
- ps_const_conf.type = SHADER_TYPE_PS;
- ps_alu_consts = (float *)ps_const_conf.bo->ptr;
- if (accel_state->dst_obj.bpp == 16) {
- r = (fg >> 11) & 0x1f;
- g = (fg >> 5) & 0x3f;
- b = (fg >> 0) & 0x1f;
- ps_alu_consts[0] = (float)r / 31; /* R */
- ps_alu_consts[1] = (float)g / 63; /* G */
- ps_alu_consts[2] = (float)b / 31; /* B */
- ps_alu_consts[3] = 1.0; /* A */
- } else if (accel_state->dst_obj.bpp == 8) {
- a = (fg >> 0) & 0xff;
- ps_alu_consts[0] = 0.0; /* R */
- ps_alu_consts[1] = 0.0; /* G */
- ps_alu_consts[2] = 0.0; /* B */
- ps_alu_consts[3] = (float)a / 255; /* A */
- } else {
- a = (fg >> 24) & 0xff;
- r = (fg >> 16) & 0xff;
- g = (fg >> 8) & 0xff;
- b = (fg >> 0) & 0xff;
- ps_alu_consts[0] = (float)r / 255; /* R */
- ps_alu_consts[1] = (float)g / 255; /* G */
- ps_alu_consts[2] = (float)b / 255; /* B */
- ps_alu_consts[3] = (float)a / 255; /* A */
- }
- radeon_bo_unmap(ps_const_conf.bo);
-
- radeon_cs_space_add_persistent_bo(info->cs, ps_const_conf.bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- if (radeon_cs_space_check(info->cs)) {
- radeon_bo_unref(ps_const_conf.bo);
- RADEON_FALLBACK(("ps const buffer size check failed\n"));
- }
-
radeon_vbo_check(pScrn, &accel_state->vbo, 16);
+ radeon_vbo_check(pScrn, &accel_state->cbuf, 256);
radeon_cp_start(pScrn);
evergreen_set_default_state(pScrn);
@@ -320,6 +274,39 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
E32(FLAT_SHADE_ENA_bit); // SPI_INTERP_CONTROL_0
END_BATCH();
+
+ /* PS alu constants */
+ ps_const_conf.size_bytes = 256;
+ ps_const_conf.type = SHADER_TYPE_PS;
+ ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+ if (accel_state->dst_obj.bpp == 16) {
+ r = (fg >> 11) & 0x1f;
+ g = (fg >> 5) & 0x3f;
+ b = (fg >> 0) & 0x1f;
+ ps_alu_consts[0] = (float)r / 31; /* R */
+ ps_alu_consts[1] = (float)g / 63; /* G */
+ ps_alu_consts[2] = (float)b / 31; /* B */
+ ps_alu_consts[3] = 1.0; /* A */
+ } else if (accel_state->dst_obj.bpp == 8) {
+ a = (fg >> 0) & 0xff;
+ ps_alu_consts[0] = 0.0; /* R */
+ ps_alu_consts[1] = 0.0; /* G */
+ ps_alu_consts[2] = 0.0; /* B */
+ ps_alu_consts[3] = (float)a / 255; /* A */
+ } else {
+ a = (fg >> 24) & 0xff;
+ r = (fg >> 16) & 0xff;
+ g = (fg >> 8) & 0xff;
+ b = (fg >> 0) & 0xff;
+ ps_alu_consts[0] = (float)r / 255; /* R */
+ ps_alu_consts[1] = (float)g / 255; /* G */
+ ps_alu_consts[2] = (float)b / 255; /* B */
+ ps_alu_consts[3] = (float)a / 255; /* A */
+ }
+ radeon_vbo_commit(pScrn, &accel_state->cbuf);
+
+ ps_const_conf.bo = accel_state->cbuf.vb_bo;
+ ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_start_op;
evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
if (accel_state->vsync)
@@ -1208,7 +1195,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
shader_config_t vs_conf, ps_conf;
const_config_t vs_const_conf;
struct r600_accel_object src_obj, mask_obj, dst_obj;
- int ret;
+ float *cbuf;
//return FALSE;
@@ -1284,37 +1271,13 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
CLEAR (ps_conf);
CLEAR (vs_const_conf);
- vs_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
- RADEON_GEM_DOMAIN_GTT, 0);
- if (vs_const_conf.bo == NULL)
- RADEON_FALLBACK(("vs const buffer alloc failed\n"));
- ret = radeon_bo_map(vs_const_conf.bo, 0);
- if (ret)
- RADEON_FALLBACK(("vs const buffer map failed\n"));
-
- /* VS alu constants */
- vs_const_conf.size_bytes = 256;
- vs_const_conf.const_addr = 0;
- vs_const_conf.type = SHADER_TYPE_VS;
-
- EVERGREENXFormSetup(pSrcPicture, pSrc, 0, (float *)vs_const_conf.bo->ptr);
- if (pMask)
- EVERGREENXFormSetup(pMaskPicture, pMask, 1, (float *)vs_const_conf.bo->ptr);
-
- radeon_bo_unmap(vs_const_conf.bo);
-
- radeon_cs_space_add_persistent_bo(info->cs, vs_const_conf.bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- if (radeon_cs_space_check(info->cs)) {
- radeon_bo_unref(vs_const_conf.bo);
- RADEON_FALLBACK(("vs const buffer size check failed\n"));
- }
-
if (pMask)
radeon_vbo_check(pScrn, &accel_state->vbo, 24);
else
radeon_vbo_check(pScrn, &accel_state->vbo, 16);
+ radeon_vbo_check(pScrn, &accel_state->cbuf, 256);
+
radeon_cp_start(pScrn);
evergreen_set_default_state(pScrn);
@@ -1327,6 +1290,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
radeon_ib_discard(pScrn);
radeon_cs_flush_indirect(pScrn);
radeon_vb_discard(pScrn, &accel_state->vbo);
+ radeon_vb_discard(pScrn, &accel_state->cbuf);
return FALSE;
}
@@ -1335,6 +1299,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
radeon_ib_discard(pScrn);
radeon_cs_flush_indirect(pScrn);
radeon_vb_discard(pScrn, &accel_state->vbo);
+ radeon_vb_discard(pScrn, &accel_state->cbuf);
return FALSE;
}
} else
@@ -1446,6 +1411,19 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
END_BATCH();
/* VS alu constants */
+ vs_const_conf.size_bytes = 256;
+ vs_const_conf.type = SHADER_TYPE_VS;
+ cbuf = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+
+ EVERGREENXFormSetup(pSrcPicture, pSrc, 0, cbuf);
+ if (pMask)
+ EVERGREENXFormSetup(pMaskPicture, pMask, 1, cbuf);
+
+ radeon_vbo_commit(pScrn, &accel_state->cbuf);
+
+ /* VS alu constants */
+ vs_const_conf.bo = accel_state->cbuf.vb_bo;
+ vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_start_op;
evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT);
if (accel_state->vsync)
@@ -1907,8 +1885,10 @@ EVERGREENDrawInit(ScreenPtr pScreen)
info->accel_state->dst_obj.bo = NULL;
info->accel_state->copy_area_bo = NULL;
info->accel_state->vbo.vb_start_op = -1;
+ info->accel_state->cbuf.vb_start_op = -1;
info->accel_state->finish_op = evergreen_finish_op;
info->accel_state->vbo.verts_per_op = 3;
+ info->accel_state->cbuf.verts_per_op = 1;
RADEONVlineHelperClear(pScrn);
radeon_vbo_init_lists(pScrn);
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index 6a2041b..3ff4d61 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -111,7 +111,6 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
const_config_t ps_const_conf;
float *vs_alu_consts;
const_config_t vs_const_conf;
- int ret;
cont = RTFContrast(pPriv->contrast);
bright = RTFBrightness(pPriv->brightness);
@@ -153,75 +152,6 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
CLEAR (vs_const_conf);
CLEAR (ps_const_conf);
- /* setup the ps consts */
- ps_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
- RADEON_GEM_DOMAIN_GTT, 0);
- if (ps_const_conf.bo == NULL) {
- ErrorF("ps const buffer alloc failed\n");
- return;
- }
- ret = radeon_bo_map(ps_const_conf.bo, 0);
- if (ret) {
- ErrorF("ps const buffer map failed\n");
- return;
- }
-
- /* PS alu constants */
- ps_const_conf.size_bytes = 256;
- ps_const_conf.const_addr = 0;
- ps_const_conf.type = SHADER_TYPE_PS;
- ps_alu_consts = (float *)ps_const_conf.bo->ptr;
-
- ps_alu_consts[0] = off[0];
- ps_alu_consts[1] = off[1];
- ps_alu_consts[2] = off[2];
- ps_alu_consts[3] = yco;
-
- ps_alu_consts[4] = uco[0];
- ps_alu_consts[5] = uco[1];
- ps_alu_consts[6] = uco[2];
- ps_alu_consts[7] = gamma;
-
- ps_alu_consts[8] = vco[0];
- ps_alu_consts[9] = vco[1];
- ps_alu_consts[10] = vco[2];
- ps_alu_consts[11] = 0.0;
- radeon_bo_unmap(ps_const_conf.bo);
-
- vs_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
- RADEON_GEM_DOMAIN_GTT, 0);
- if (vs_const_conf.bo == NULL) {
- ErrorF("vs const buffer alloc failed\n");
- return;
- }
- ret = radeon_bo_map(vs_const_conf.bo, 0);
- if (ret) {
- ErrorF("vs const buffer map failed\n");
- return;
- }
-
- /* PS alu constants */
- vs_const_conf.size_bytes = 256;
- vs_const_conf.const_addr = 0;
- vs_const_conf.type = SHADER_TYPE_VS;
- vs_alu_consts = (float *)vs_const_conf.bo->ptr;
- vs_alu_consts[0] = 1.0 / pPriv->w;
- vs_alu_consts[1] = 1.0 / pPriv->h;
- vs_alu_consts[2] = 0.0;
- vs_alu_consts[3] = 0.0;
- radeon_bo_unmap(vs_const_conf.bo);
-
- radeon_cs_space_add_persistent_bo(info->cs, ps_const_conf.bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- radeon_cs_space_add_persistent_bo(info->cs, vs_const_conf.bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- if (radeon_cs_space_check(info->cs)) {
- radeon_bo_unref(ps_const_conf.bo);
- radeon_bo_unref(vs_const_conf.bo);
- ErrorF("const buffer size check failed\n");
- return;
- }
-
#if defined(XF86DRM_MODE)
if (info->cs) {
dst_obj.offset = 0;
@@ -265,6 +195,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
#endif
radeon_vbo_check(pScrn, &accel_state->vbo, 16);
+ radeon_vbo_check(pScrn, &accel_state->cbuf, 512);
radeon_cp_start(pScrn);
evergreen_set_default_state(pScrn);
@@ -303,9 +234,6 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
ps_conf.bo = accel_state->shaders_bo;
evergreen_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
- /* PS alu constants */
- evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
-
/* Texture */
switch(pPriv->id) {
case FOURCC_YV12:
@@ -518,7 +446,49 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
E32(0); // SPI_INTERP_CONTROL_0
END_BATCH();
+ /* PS alu constants */
+ ps_const_conf.size_bytes = 256;
+ ps_const_conf.type = SHADER_TYPE_PS;
+ ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+
+ ps_alu_consts[0] = off[0];
+ ps_alu_consts[1] = off[1];
+ ps_alu_consts[2] = off[2];
+ ps_alu_consts[3] = yco;
+
+ ps_alu_consts[4] = uco[0];
+ ps_alu_consts[5] = uco[1];
+ ps_alu_consts[6] = uco[2];
+ ps_alu_consts[7] = gamma;
+
+ ps_alu_consts[8] = vco[0];
+ ps_alu_consts[9] = vco[1];
+ ps_alu_consts[10] = vco[2];
+ ps_alu_consts[11] = 0.0;
+
+ radeon_vbo_commit(pScrn, &accel_state->cbuf);
+
+ /* PS alu constants */
+ ps_const_conf.bo = accel_state->cbuf.vb_bo;
+ ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_start_op;
+ evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
+
+ /* VS alu constants */
+ vs_const_conf.size_bytes = 256;
+ vs_const_conf.type = SHADER_TYPE_VS;
+ vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+
+ vs_alu_consts = (float *)vs_const_conf.bo->ptr;
+ vs_alu_consts[0] = 1.0 / pPriv->w;
+ vs_alu_consts[1] = 1.0 / pPriv->h;
+ vs_alu_consts[2] = 0.0;
+ vs_alu_consts[3] = 0.0;
+
+ radeon_vbo_commit(pScrn, &accel_state->cbuf);
+
/* VS alu constants */
+ vs_const_conf.bo = accel_state->cbuf.vb_bo;
+ vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_start_op;
evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT);
if (pPriv->vsync) {
diff --git a/src/radeon.h b/src/radeon.h
index a6a9dd2..e85d941 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -740,6 +740,7 @@ struct radeon_accel_state {
drmBufPtr ib;
struct radeon_vbo_object vbo;
+ struct radeon_vbo_object cbuf;
/* where to discard IB from if we cancel operation */
uint32_t ib_reset_op;
diff --git a/src/radeon_exa_shared.c b/src/radeon_exa_shared.c
index 9aa4f39..2ef0751 100644
--- a/src/radeon_exa_shared.c
+++ b/src/radeon_exa_shared.c
@@ -166,6 +166,7 @@ int radeon_cp_start(ScrnInfoPtr pScrn)
}
}
accel_state->vbo.vb_start_op = accel_state->vbo.vb_offset;
+ accel_state->cbuf.vb_start_op = accel_state->cbuf.vb_offset;
return 0;
}
@@ -214,6 +215,8 @@ void radeon_ib_discard(ScrnInfoPtr pScrn)
info->accel_state->vbo.vb_offset = 0;
info->accel_state->vbo.vb_start_op = -1;
+ info->accel_state->cbuf.vb_offset = 0;
+ info->accel_state->cbuf.vb_start_op = -1;
if (CS_FULL(info->cs)) {
radeon_cs_flush_indirect(pScrn);
@@ -226,6 +229,14 @@ void radeon_ib_discard(ScrnInfoPtr pScrn)
if (ret)
ErrorF("space check failed in flush\n");
+ if (info->accel_state->cbuf.vb_bo) {
+ ret = radeon_cs_space_check_with_bo(info->cs,
+ info->accel_state->cbuf.vb_bo,
+ RADEON_GEM_DOMAIN_GTT, 0);
+ if (ret)
+ ErrorF("space check failed in flush\n");
+ }
+
out:
if (info->dri2.enabled) {
info->accel_state->XInited3D = FALSE;
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index c372661..deecdc9 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -88,6 +88,12 @@ void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
info->accel_state->vbo.vb_start_op = -1;
}
+ /* release the current VBO so we don't block on mapping it later */
+ if (info->accel_state->cbuf.vb_offset && info->accel_state->cbuf.vb_bo) {
+ radeon_vbo_put(pScrn, &info->accel_state->cbuf);
+ info->accel_state->cbuf.vb_start_op = -1;
+ }
+
radeon_cs_emit(info->cs);
radeon_cs_erase(info->cs);
@@ -100,6 +106,14 @@ void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
if (ret)
ErrorF("space check failed in flush\n");
+ if (accel_state->cbuf.vb_bo) {
+ ret = radeon_cs_space_check_with_bo(info->cs,
+ accel_state->cbuf.vb_bo,
+ RADEON_GEM_DOMAIN_GTT, 0);
+ if (ret)
+ ErrorF("space check failed in flush\n");
+ }
+
if (info->reemit_current2d && info->state_2d.op)
info->reemit_current2d(pScrn, info->state_2d.op);
commit eede93b057bbdddcde5da3220a3f8c6f73784a7e
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Aug 23 13:16:27 2010 -0400
radeon: move vbo data to a separate struct
this way we can share the vbo code with const buffers
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index 748ff12..31e460d 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -495,12 +495,12 @@ evergreen_set_vtx_resource(ScrnInfoPtr pScrn, vtx_resource_t *res, uint32_t doma
/* flush vertex cache */
if (info->ChipFamily == CHIP_FAMILY_CEDAR)
evergreen_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit,
- accel_state->vb_offset, accel_state->vb_mc_addr,
+ accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr,
res->bo,
domain, 0);
else
evergreen_cp_set_surface_sync(pScrn, VC_ACTION_ENA_bit,
- accel_state->vb_offset, accel_state->vb_mc_addr,
+ accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr,
res->bo,
domain, 0);
@@ -1052,26 +1052,26 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size)
draw_config_t draw_conf;
vtx_resource_t vtx_res;
- if (accel_state->vb_start_op == -1)
+ if (accel_state->vbo.vb_start_op == -1)
return;
CLEAR (draw_conf);
CLEAR (vtx_res);
- if (accel_state->vb_offset == accel_state->vb_start_op) {
+ if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) {
radeon_ib_discard(pScrn);
radeon_cs_flush_indirect(pScrn);
- radeon_vb_discard(pScrn);
+ radeon_vb_discard(pScrn, &accel_state->vbo);
return;
}
/* Vertex buffer setup */
- accel_state->vb_size = accel_state->vb_offset - accel_state->vb_start_op;
+ accel_state->vbo.vb_size = accel_state->vbo.vb_offset - accel_state->vbo.vb_start_op;
vtx_res.id = SQ_FETCH_RESOURCE_vs;
vtx_res.vtx_size_dw = vtx_size / 4;
- vtx_res.vtx_num_entries = accel_state->vb_size / 4;
- vtx_res.vb_addr = accel_state->vb_mc_addr + accel_state->vb_start_op;
- vtx_res.bo = accel_state->vb_bo;
+ vtx_res.vtx_num_entries = accel_state->vbo.vb_size / 4;
+ vtx_res.vb_addr = accel_state->vbo.vb_mc_addr + accel_state->vbo.vb_start_op;
+ vtx_res.bo = accel_state->vbo.vb_bo;
vtx_res.dst_sel_x = SQ_SEL_X;
vtx_res.dst_sel_y = SQ_SEL_Y;
vtx_res.dst_sel_z = SQ_SEL_Z;
@@ -1092,7 +1092,7 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size)
accel_state->dst_size, accel_state->dst_obj.offset,
accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
- accel_state->vb_start_op = -1;
+ accel_state->vbo.vb_start_op = -1;
accel_state->ib_reset_op = 0;
}
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 7eb1b72..434516b 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -41,8 +41,6 @@
#include "radeon_exa_shared.h"
#include "radeon_vbo.h"
-/* #define SHOW_VERTEXES */
-
uint32_t EVERGREEN_ROP[16] = {
RADEON_ROP3_ZERO, /* GXclear */
RADEON_ROP3_DSa, /* Gxand */
@@ -241,7 +239,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
RADEON_FALLBACK(("ps const buffer size check failed\n"));
}
- radeon_vbo_check(pScrn, 16);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 16);
radeon_cp_start(pScrn);
evergreen_set_default_state(pScrn);
@@ -342,7 +340,7 @@ EVERGREENSolid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
if (accel_state->vsync)
RADEONVlineHelperSet(pScrn, x1, y1, x2, y2);
- vb = radeon_vbo_space(pScrn, 8);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 8);
vb[0] = (float)x1;
vb[1] = (float)y1;
@@ -353,7 +351,7 @@ EVERGREENSolid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
vb[4] = (float)x2;
vb[5] = (float)y2;
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
}
static void
@@ -389,7 +387,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
CLEAR (vs_conf);
CLEAR (ps_conf);
- radeon_vbo_check(pScrn, 16);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 16);
radeon_cp_start(pScrn);
evergreen_set_default_state(pScrn);
@@ -545,9 +543,11 @@ EVERGREENAppendCopyVertex(ScrnInfoPtr pScrn,
int dstX, int dstY,
int w, int h)
{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
float *vb;
- vb = radeon_vbo_space(pScrn, 16);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
vb[0] = (float)dstX;
vb[1] = (float)dstY;
@@ -564,7 +564,7 @@ EVERGREENAppendCopyVertex(ScrnInfoPtr pScrn,
vb[10] = (float)(srcX + w);
vb[11] = (float)(srcY + h);
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
}
static Bool
@@ -1311,9 +1311,9 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
}
if (pMask)
- radeon_vbo_check(pScrn, 24);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 24);
else
- radeon_vbo_check(pScrn, 16);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 16);
radeon_cp_start(pScrn);
@@ -1326,7 +1326,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
if (!EVERGREENTextureSetup(pSrcPicture, pSrc, 0)) {
radeon_ib_discard(pScrn);
radeon_cs_flush_indirect(pScrn);
- radeon_vb_discard(pScrn);
+ radeon_vb_discard(pScrn, &accel_state->vbo);
return FALSE;
}
@@ -1334,7 +1334,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
if (!EVERGREENTextureSetup(pMaskPicture, pMask, 1)) {
radeon_ib_discard(pScrn);
radeon_cs_flush_indirect(pScrn);
- radeon_vb_discard(pScrn);
+ radeon_vb_discard(pScrn, &accel_state->vbo);
return FALSE;
}
} else
@@ -1470,7 +1470,7 @@ static void EVERGREENComposite(PixmapPtr pDst,
if (accel_state->msk_pic) {
- vb = radeon_vbo_space(pScrn, 24);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 24);
vb[0] = (float)dstX;
vb[1] = (float)dstY;
@@ -1493,11 +1493,11 @@ static void EVERGREENComposite(PixmapPtr pDst,
vb[16] = (float)(maskX + w);
vb[17] = (float)(maskY + h);
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
} else {
- vb = radeon_vbo_space(pScrn, 16);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
vb[0] = (float)dstX;
vb[1] = (float)dstY;
@@ -1514,7 +1514,7 @@ static void EVERGREENComposite(PixmapPtr pDst,
vb[10] = (float)(srcX + w);
vb[11] = (float)(srcY + h);
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
}
@@ -1906,9 +1906,9 @@ EVERGREENDrawInit(ScreenPtr pScreen)
info->accel_state->src_obj[1].bo = NULL;
info->accel_state->dst_obj.bo = NULL;
info->accel_state->copy_area_bo = NULL;
- info->accel_state->vb_start_op = -1;
+ info->accel_state->vbo.vb_start_op = -1;
info->accel_state->finish_op = evergreen_finish_op;
- info->accel_state->verts_per_op = 3;
+ info->accel_state->vbo.verts_per_op = 3;
RADEONVlineHelperClear(pScrn);
radeon_vbo_init_lists(pScrn);
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index 2b8d65e..6a2041b 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -264,7 +264,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
dstyoff = 0;
#endif
- radeon_vbo_check(pScrn, 16);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 16);
radeon_cp_start(pScrn);
evergreen_set_default_state(pScrn);
@@ -559,7 +559,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
srch = (pPriv->src_h * dsth) / pPriv->dst_h;
- vb = radeon_vbo_space(pScrn, 16);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
vb[0] = (float)dstX;
vb[1] = (float)dstY;
@@ -576,7 +576,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vb[10] = (float)(srcX + srcw);
vb[11] = (float)(srcY + srch);
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
pBox++;
}
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 7702087..99670b4 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -208,7 +208,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
CLEAR (vs_conf);
CLEAR (ps_conf);
- radeon_vbo_check(pScrn, 16);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 16);
radeon_cp_start(pScrn);
r600_set_default_state(pScrn, accel_state->ib);
@@ -333,7 +333,7 @@ R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
if (accel_state->vsync)
RADEONVlineHelperSet(pScrn, x1, y1, x2, y2);
- vb = radeon_vbo_space(pScrn, 8);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 8);
vb[0] = (float)x1;
vb[1] = (float)y1;
@@ -344,7 +344,7 @@ R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
vb[4] = (float)x2;
vb[5] = (float)y2;
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
}
static void
@@ -380,7 +380,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
CLEAR (vs_conf);
CLEAR (ps_conf);
- radeon_vbo_check(pScrn, 16);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 16);
radeon_cp_start(pScrn);
r600_set_default_state(pScrn, accel_state->ib);
@@ -535,9 +535,11 @@ R600AppendCopyVertex(ScrnInfoPtr pScrn,
int dstX, int dstY,
int w, int h)
{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
float *vb;
- vb = radeon_vbo_space(pScrn, 16);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
vb[0] = (float)dstX;
vb[1] = (float)dstY;
@@ -554,7 +556,7 @@ R600AppendCopyVertex(ScrnInfoPtr pScrn,
vb[10] = (float)(srcX + w);
vb[11] = (float)(srcY + h);
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
}
static Bool
@@ -1318,9 +1320,9 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
CLEAR (ps_conf);
if (pMask)
- radeon_vbo_check(pScrn, 24);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 24);
else
- radeon_vbo_check(pScrn, 16);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 16);
radeon_cp_start(pScrn);
@@ -1332,14 +1334,14 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
if (!R600TextureSetup(pSrcPicture, pSrc, 0)) {
R600IBDiscard(pScrn, accel_state->ib);
- radeon_vb_discard(pScrn);
+ radeon_vb_discard(pScrn, &accel_state->vbo);
return FALSE;
}
if (pMask) {
if (!R600TextureSetup(pMaskPicture, pMask, 1)) {
R600IBDiscard(pScrn, accel_state->ib);
- radeon_vb_discard(pScrn);
+ radeon_vb_discard(pScrn, &accel_state->vbo);
return FALSE;
}
} else
@@ -1484,7 +1486,7 @@ static void R600Composite(PixmapPtr pDst,
if (accel_state->msk_pic) {
- vb = radeon_vbo_space(pScrn, 24);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 24);
vb[0] = (float)dstX;
vb[1] = (float)dstY;
@@ -1507,11 +1509,11 @@ static void R600Composite(PixmapPtr pDst,
vb[16] = (float)(maskX + w);
vb[17] = (float)(maskY + h);
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
} else {
- vb = radeon_vbo_space(pScrn, 16);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
vb[0] = (float)dstX;
vb[1] = (float)dstY;
@@ -1528,7 +1530,7 @@ static void R600Composite(PixmapPtr pDst,
vb[10] = (float)(srcX + w);
vb[11] = (float)(srcY + h);
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
}
@@ -1642,7 +1644,7 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
}
R600IBDiscard(pScrn, scratch);
- radeon_vb_discard(pScrn);
+ radeon_vb_discard(pScrn, &accel_state->vbo);
return TRUE;
}
@@ -1756,7 +1758,7 @@ R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h,
}
R600IBDiscard(pScrn, scratch);
- radeon_vb_discard(pScrn);
+ radeon_vb_discard(pScrn, &accel_state->vbo);
return TRUE;
@@ -2227,9 +2229,9 @@ R600DrawInit(ScreenPtr pScreen)
info->accel_state->src_obj[1].bo = NULL;
info->accel_state->dst_obj.bo = NULL;
info->accel_state->copy_area_bo = NULL;
- info->accel_state->vb_start_op = -1;
+ info->accel_state->vbo.vb_start_op = -1;
info->accel_state->finish_op = r600_finish_op;
- info->accel_state->verts_per_op = 3;
+ info->accel_state->vbo.verts_per_op = 3;
RADEONVlineHelperClear(pScrn);
#ifdef XF86DRM_MODE
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 66164ac..88073ac 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -206,7 +206,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
dstyoff = 0;
#endif
- radeon_vbo_check(pScrn, 16);
+ radeon_vbo_check(pScrn, &accel_state->vbo, 16);
radeon_cp_start(pScrn);
r600_set_default_state(pScrn, accel_state->ib);
@@ -510,7 +510,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
srch = (pPriv->src_h * dsth) / pPriv->dst_h;
- vb = radeon_vbo_space(pScrn, 16);
+ vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
vb[0] = (float)dstX;
vb[1] = (float)dstY;
@@ -527,7 +527,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vb[10] = (float)(srcX + srcw);
vb[11] = (float)(srcY + srch);
- radeon_vbo_commit(pScrn);
+ radeon_vbo_commit(pScrn, &accel_state->vbo);
pBox++;
}
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 2952863..4b5c553 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -525,12 +525,12 @@ r600_set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint
(info->ChipFamily == CHIP_FAMILY_RS880) ||
(info->ChipFamily == CHIP_FAMILY_RV710))
r600_cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
- accel_state->vb_offset, accel_state->vb_mc_addr,
+ accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr,
res->bo,
domain, 0);
else
r600_cp_set_surface_sync(pScrn, ib, VC_ACTION_ENA_bit,
- accel_state->vb_offset, accel_state->vb_mc_addr,
+ accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr,
res->bo,
domain, 0);
@@ -1165,26 +1165,26 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
draw_config_t draw_conf;
vtx_resource_t vtx_res;
- if (accel_state->vb_start_op == -1)
+ if (accel_state->vbo.vb_start_op == -1)
return;
CLEAR (draw_conf);
CLEAR (vtx_res);
- if (accel_state->vb_offset == accel_state->vb_start_op) {
+ if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) {
R600IBDiscard(pScrn, accel_state->ib);
- radeon_vb_discard(pScrn);
+ radeon_vb_discard(pScrn, &accel_state->vbo);
return;
}
/* Vertex buffer setup */
- accel_state->vb_size = accel_state->vb_offset - accel_state->vb_start_op;
+ accel_state->vbo.vb_size = accel_state->vbo.vb_offset - accel_state->vbo.vb_start_op;
vtx_res.id = SQ_VTX_RESOURCE_vs;
vtx_res.vtx_size_dw = vtx_size / 4;
- vtx_res.vtx_num_entries = accel_state->vb_size / 4;
+ vtx_res.vtx_num_entries = accel_state->vbo.vb_size / 4;
vtx_res.mem_req_size = 1;
- vtx_res.vb_addr = accel_state->vb_mc_addr + accel_state->vb_start_op;
- vtx_res.bo = accel_state->vb_bo;
+ vtx_res.vb_addr = accel_state->vbo.vb_mc_addr + accel_state->vbo.vb_start_op;
+ vtx_res.bo = accel_state->vbo.vb_bo;
r600_set_vtx_resource(pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT);
/* Draw */
@@ -1204,7 +1204,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
accel_state->dst_size, accel_state->dst_obj.offset,
accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
- accel_state->vb_start_op = -1;
+ accel_state->vbo.vb_start_op = -1;
accel_state->ib_reset_op = 0;
#if KMS_MULTI_OP
diff --git a/src/radeon.h b/src/radeon.h
index 8428e2d..a6a9dd2 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -676,6 +676,18 @@ struct r600_accel_object {
struct radeon_bo *bo;
};
+struct radeon_vbo_object {
+ int vb_offset;
+ uint64_t vb_mc_addr;
+ int vb_total;
+ void *vb_ptr;
+ uint32_t vb_size;
+ uint32_t vb_op_vert_size;
+ int32_t vb_start_op;
+ struct radeon_bo *vb_bo;
+ unsigned verts_per_op;
+};
+
struct radeon_accel_state {
/* common accel data */
int fifo_slots; /* Free slots in the FIFO (64 max) */
@@ -723,20 +735,14 @@ struct radeon_accel_state {
uint32_t *draw_header;
unsigned vtx_count;
unsigned num_vtx;
- unsigned verts_per_op;
Bool vsync;
drmBufPtr ib;
- int vb_offset;
- uint64_t vb_mc_addr;
- int vb_total;
- void *vb_ptr;
- uint32_t vb_size;
- uint32_t vb_op_vert_size;
- int32_t vb_start_op;
+
+ struct radeon_vbo_object vbo;
+
/* where to discard IB from if we cancel operation */
uint32_t ib_reset_op;
- struct radeon_bo *vb_bo;
#ifdef XF86DRM_MODE
struct radeon_dma_bo bo_free;
struct radeon_dma_bo bo_wait;
diff --git a/src/radeon_exa_shared.c b/src/radeon_exa_shared.c
index d1926f4..9aa4f39 100644
--- a/src/radeon_exa_shared.c
+++ b/src/radeon_exa_shared.c
@@ -131,21 +131,19 @@ static Bool radeon_vb_get(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- accel_state->vb_mc_addr = info->gartLocation + info->dri->bufStart +
+ accel_state->vbo.vb_mc_addr = info->gartLocation + info->dri->bufStart +
(accel_state->ib->idx*accel_state->ib->total)+
(accel_state->ib->total / 2);
- accel_state->vb_total = (accel_state->ib->total / 2);
- accel_state->vb_ptr = (pointer)((char*)accel_state->ib->address +
+ accel_state->vbo.vb_total = (accel_state->ib->total / 2);
+ accel_state->vbo.vb_ptr = (pointer)((char*)accel_state->ib->address +
(accel_state->ib->total / 2));
- accel_state->vb_offset = 0;
+ accel_state->vbo.vb_offset = 0;
return TRUE;
}
-void radeon_vb_discard(ScrnInfoPtr pScrn)
+void radeon_vb_discard(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- info->accel_state->vb_start_op = -1;
+ vbo->vb_start_op = -1;
}
int radeon_cp_start(ScrnInfoPtr pScrn)
@@ -159,7 +157,6 @@ int radeon_cp_start(ScrnInfoPtr pScrn)
radeon_cs_flush_indirect(pScrn);
}
accel_state->ib_reset_op = info->cs->cdw;
- accel_state->vb_start_op = accel_state->vb_offset;
} else
#endif
{
@@ -167,33 +164,35 @@ int radeon_cp_start(ScrnInfoPtr pScrn)
if (!radeon_vb_get(pScrn)) {
return -1;
}
- accel_state->vb_start_op = accel_state->vb_offset;
}
+ accel_state->vbo.vb_start_op = accel_state->vbo.vb_offset;
return 0;
}
-void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
+void radeon_vb_no_space(ScrnInfoPtr pScrn,
+ struct radeon_vbo_object *vbo,
+ int vert_size)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
+ struct radeon_accel_state *accel_state = info->accel_state;
#if defined(XF86DRM_MODE)
if (info->cs) {
- if (accel_state->vb_bo) {
- if (accel_state->vb_start_op != accel_state->vb_offset) {
+ if (vbo->vb_bo) {
+ if (vbo->vb_start_op != vbo->vb_offset) {
accel_state->finish_op(pScrn, vert_size);
accel_state->ib_reset_op = info->cs->cdw;
}
/* release the current VBO */
- radeon_vbo_put(pScrn);
+ radeon_vbo_put(pScrn, vbo);
}
/* get a new one */
- radeon_vbo_get(pScrn);
+ radeon_vbo_get(pScrn, vbo);
return;
}
#endif
- if (accel_state->vb_start_op != -1) {
+ if (vbo->vb_start_op != -1) {
accel_state->finish_op(pScrn, vert_size);
radeon_cp_start(pScrn);
}
@@ -213,8 +212,8 @@ void radeon_ib_discard(ScrnInfoPtr pScrn)
goto out;
}
- info->accel_state->vb_offset = 0;
- info->accel_state->vb_start_op = -1;
+ info->accel_state->vbo.vb_offset = 0;
+ info->accel_state->vbo.vb_start_op = -1;
if (CS_FULL(info->cs)) {
radeon_cs_flush_indirect(pScrn);
@@ -222,7 +221,7 @@ void radeon_ib_discard(ScrnInfoPtr pScrn)
}
radeon_cs_erase(info->cs);
ret = radeon_cs_space_check_with_bo(info->cs,
- info->accel_state->vb_bo,
+ info->accel_state->vbo.vb_bo,
RADEON_GEM_DOMAIN_GTT, 0);
if (ret)
ErrorF("space check failed in flush\n");
diff --git a/src/radeon_exa_shared.h b/src/radeon_exa_shared.h
index 71068b1..489e3b0 100644
--- a/src/radeon_exa_shared.h
+++ b/src/radeon_exa_shared.h
@@ -72,9 +72,9 @@ static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int r
extern void radeon_ib_discard(ScrnInfoPtr pScrn);
#endif /* XF86DRM_MODE */
-extern void radeon_vb_discard(ScrnInfoPtr pScrn);
+extern void radeon_vb_discard(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo);
extern int radeon_cp_start(ScrnInfoPtr pScrn);
-extern void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size);
+extern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size);
extern void radeon_vbo_done_composite(PixmapPtr pDst);
#endif
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index b762648..c372661 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -83,9 +83,9 @@ void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
return;
/* release the current VBO so we don't block on mapping it later */
- if (info->accel_state->vb_offset && info->accel_state->vb_bo) {
- radeon_vbo_put(pScrn);
- info->accel_state->vb_start_op = -1;
+ if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) {
+ radeon_vbo_put(pScrn, &info->accel_state->vbo);
+ info->accel_state->vbo.vb_start_op = -1;
}
radeon_cs_emit(info->cs);
@@ -95,7 +95,7 @@ void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
radeon_vbo_flush_bos(pScrn);
ret = radeon_cs_space_check_with_bo(info->cs,
- accel_state->vb_bo,
+ accel_state->vbo.vb_bo,
RADEON_GEM_DOMAIN_GTT, 0);
if (ret)
ErrorF("space check failed in flush\n");
diff --git a/src/radeon_vbo.c b/src/radeon_vbo.c
index 0735540..c0a668f 100644
--- a/src/radeon_vbo.c
+++ b/src/radeon_vbo.c
@@ -41,31 +41,27 @@
static struct radeon_bo *radeon_vbo_get_bo(ScrnInfoPtr pScrn);
-void radeon_vbo_put(ScrnInfoPtr pScrn)
+void radeon_vbo_put(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- if (accel_state->vb_bo) {
- radeon_bo_unmap(accel_state->vb_bo);
- radeon_bo_unref(accel_state->vb_bo);
- accel_state->vb_bo = NULL;
- accel_state->vb_total = 0;
+
+ if (vbo->vb_bo) {
+ radeon_bo_unmap(vbo->vb_bo);
+ radeon_bo_unref(vbo->vb_bo);
+ vbo->vb_bo = NULL;
+ vbo->vb_total = 0;
}
- accel_state->vb_offset = 0;
+ vbo->vb_offset = 0;
}
-void radeon_vbo_get(ScrnInfoPtr pScrn)
+void radeon_vbo_get(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
- accel_state->vb_bo = radeon_vbo_get_bo(pScrn);
+ vbo->vb_bo = radeon_vbo_get_bo(pScrn);
- accel_state->vb_total = VBO_SIZE;
- accel_state->vb_offset = 0;
- accel_state->vb_start_op = accel_state->vb_offset;
+ vbo->vb_total = VBO_SIZE;
+ vbo->vb_offset = 0;
+ vbo->vb_start_op = vbo->vb_offset;
}
/* these functions could migrate to libdrm and
@@ -80,7 +76,7 @@ static int radeon_bo_is_idle(struct radeon_bo *bo)
void radeon_vbo_init_lists(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
+ struct radeon_accel_state *accel_state = info->accel_state;
accel_state->use_vbos = TRUE;
make_empty_list(&accel_state->bo_free);
@@ -91,7 +87,7 @@ void radeon_vbo_init_lists(ScrnInfoPtr pScrn)
void radeon_vbo_free_lists(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
+ struct radeon_accel_state *accel_state = info->accel_state;
struct radeon_dma_bo *dma_bo, *temp;
foreach_s(dma_bo, temp, &accel_state->bo_free) {
@@ -116,7 +112,7 @@ void radeon_vbo_free_lists(ScrnInfoPtr pScrn)
void radeon_vbo_flush_bos(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
+ struct radeon_accel_state *accel_state = info->accel_state;
struct radeon_dma_bo *dma_bo, *temp;
const int expire_at = ++accel_state->bo_free.expire_counter + DMA_BO_FREE_TIME;
const int time = accel_state->bo_free.expire_counter;
@@ -164,7 +160,7 @@ void radeon_vbo_flush_bos(ScrnInfoPtr pScrn)
static struct radeon_bo *radeon_vbo_get_bo(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
+ struct radeon_accel_state *accel_state = info->accel_state;
struct radeon_dma_bo *dma_bo = NULL;
struct radeon_bo *bo;
diff --git a/src/radeon_vbo.h b/src/radeon_vbo.h
index b505f66..21533c2 100644
--- a/src/radeon_vbo.h
+++ b/src/radeon_vbo.h
@@ -2,39 +2,40 @@
#ifndef RADEON_VBO_H
#define RADEON_VBO_H
-extern void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size);
+extern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size);
extern void radeon_vbo_init_lists(ScrnInfoPtr pScrn);
extern void radeon_vbo_free_lists(ScrnInfoPtr pScrn);
extern void radeon_vbo_flush_bos(ScrnInfoPtr pScrn);
-extern void radeon_vbo_get(ScrnInfoPtr pScrn);
-extern void radeon_vbo_put(ScrnInfoPtr pScrn);
+extern void radeon_vbo_get(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo);
+extern void radeon_vbo_put(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo);
-static inline void radeon_vbo_check(ScrnInfoPtr pScrn, int vert_size)
+static inline void radeon_vbo_check(ScrnInfoPtr pScrn,
+ struct radeon_vbo_object *vbo,
+ int vert_size)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
- if ((accel_state->vb_offset + (accel_state->verts_per_op * vert_size)) > accel_state->vb_total) {
- radeon_vb_no_space(pScrn, vert_size);
+ if ((vbo->vb_offset + (vbo->verts_per_op * vert_size)) > vbo->vb_total) {
+ radeon_vb_no_space(pScrn, vbo, vert_size);
}
}
static inline void *
-radeon_vbo_space(ScrnInfoPtr pScrn, int vert_size)
+radeon_vbo_space(ScrnInfoPtr pScrn,
+ struct radeon_vbo_object *vbo,
+ int vert_size)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
void *vb;
-
+
/* we've ran out of space in the vertex buffer - need to get a
new one */
- radeon_vbo_check(pScrn, vert_size);
+ radeon_vbo_check(pScrn, vbo, vert_size);
- accel_state->vb_op_vert_size = vert_size;
+ vbo->vb_op_vert_size = vert_size;
#if defined(XF86DRM_MODE)
if (info->cs) {
int ret;
- struct radeon_bo *bo = accel_state->vb_bo;
+ struct radeon_bo *bo = vbo->vb_bo;
if (!bo->ptr) {
ret = radeon_bo_map(bo, 1);
@@ -43,19 +44,18 @@ radeon_vbo_space(ScrnInfoPtr pScrn, int vert_size)
return NULL;
}
}
- vb = (pointer)((char *)bo->ptr + accel_state->vb_offset);
+ vb = (pointer)((char *)bo->ptr + vbo->vb_offset);
} else
#endif
- vb = (pointer)((char *)accel_state->vb_ptr + accel_state->vb_offset);
+ vb = (pointer)((char *)vbo->vb_ptr + vbo->vb_offset);
return vb;
}
-static inline void radeon_vbo_commit(ScrnInfoPtr pScrn)
+static inline void radeon_vbo_commit(ScrnInfoPtr pScrn,
+ struct radeon_vbo_object *vbo)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
- accel_state->vb_offset += accel_state->verts_per_op * accel_state->vb_op_vert_size;
+ vbo->vb_offset += vbo->verts_per_op * vbo->vb_op_vert_size;
}
#endif
More information about the xorg-commit
mailing list