xf86-video-ati: Branch 'master' - 2 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Thu Aug 5 14:37:31 PDT 2010
src/drmmode_display.c | 7 ++-
src/r600_exa.c | 3 +
src/r600_state.h | 3 +
src/r6xx_accel.c | 18 ++++++--
src/radeon.h | 6 ++
src/radeon_dri2.c | 32 +++++++++++++--
src/radeon_exa.c | 26 ++++++++++--
src/radeon_kms.c | 103 +++++++++++++++++++++++++++++++++++++++++++-------
8 files changed, 170 insertions(+), 28 deletions(-)
New commits:
commit cc0a167ff2db9b097891883ded147af1d67e4407
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Tue May 25 18:17:15 2010 -0400
r6xx/r7xx: default to micro (1D) tiling for now
SW de-tiling used in the r600c 3D driver has issues with
certain configurations.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 9697bbc..4cafbc6 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -102,7 +102,10 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
case DRI2BufferDepth:
case DRI2BufferDepthStencil:
if (info->ChipFamily >= CHIP_FAMILY_R600)
- flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+ /* macro is the preferred setting, but the 2D detiling for software
+ * fallbacks in mesa still has issues on some configurations
+ */
+ flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
break;
@@ -110,7 +113,13 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
case DRI2BufferBackRight:
case DRI2BufferFakeFrontLeft:
case DRI2BufferFakeFrontRight:
- flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ /* macro is the preferred setting, but the 2D detiling for software
+ * fallbacks in mesa still has issues on some configurations
+ */
+ flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+ else
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
break;
default:
flags = 0;
@@ -186,16 +195,25 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
switch(attachment) {
case DRI2BufferDepth:
case DRI2BufferDepthStencil:
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
- else
- flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ /* macro is the preferred setting, but the 2D detiling for software
+ * fallbacks in mesa still has issues on some configurations
+ */
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+ else
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
break;
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
case DRI2BufferFakeFrontLeft:
case DRI2BufferFakeFrontRight:
- flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ /* macro is the preferred setting, but the 2D detiling for software
+ * fallbacks in mesa still has issues on some configurations
+ */
+ flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+ else
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
break;
default:
flags = 0;
commit b5bfdbd70d9671250957ccd41dfc8818850d257e
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Aug 5 17:26:28 2010 -0400
r6xx/r7xx: add support for tiling with kms (v3)
Requires radeon drm 2.6.0 and updated mesa.
v2: - fix lockup due to not emiting DB_DEPTH_INFO
https://bugs.freedesktop.org/show_bug.cgi?id=28342
- fix drm minor version to deal with evergreen accel
v3: rebase on current ddx git
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index e2d516b..6a4a32d 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1101,8 +1101,11 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
if (!info->front_bo)
goto fail;
- if (info->allowColorTiling)
- tiling_flags |= RADEON_TILING_MACRO;
+ /* no tiled scanout on r6xx+ yet */
+ if (info->allowColorTiling) {
+ if (info->ChipFamily < CHIP_FAMILY_R600)
+ tiling_flags |= RADEON_TILING_MACRO;
+ }
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (cpp) {
case 4:
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 638bd38..911dba0 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -2151,6 +2151,9 @@ R600DrawInit(ScreenPtr pScreen)
info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
info->accel_state->exa->UploadToScreen = R600UploadToScreenCS;
info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreenCS;
+#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 5)
+ info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
+#endif
} else
#endif
#endif
diff --git a/src/r600_state.h b/src/r600_state.h
index 4e65bc1..151f402 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -330,6 +330,9 @@ R600SetAccelState(ScrnInfoPtr pScrn,
extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
+extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
+ int depth, int usage_hint, int bitsPerPixel,
+ int *new_pitch);
extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index b34b6c5..86817bd 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -258,16 +258,21 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_
EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256
RELOC_BATCH(cb_conf->bo, 0, domain);
END_BATCH();
- BEGIN_BATCH(12);
+ BEGIN_BATCH(9);
// pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift) |
(slice << SLICE_TILE_MAX_shift)));
EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0 << SLICE_START_shift) |
(0 << SLICE_MAX_shift)));
- EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) |
(0 << FMASK_TILE_MAX_shift)));
END_BATCH();
+
+ BEGIN_BATCH(3 + 2);
+ EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
+ RELOC_BATCH(cb_conf->bo, 0, domain);
+ END_BATCH();
+
}
static void
@@ -885,7 +890,13 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
sq_setup(pScrn, ib, &sq_conf);
- BEGIN_BATCH(83);
+ /* set fake reloc for unused depth */
+ BEGIN_BATCH(3 + 2);
+ EREG(ib, DB_DEPTH_INFO, 0);
+ RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+ END_BATCH();
+
+ BEGIN_BATCH(80);
if (info->ChipFamily < CHIP_FAMILY_RV770) {
EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) |
- (28 << TD_FIFO_CREDIT_shift)));
@@ -928,7 +939,6 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
E32(ib, 0); // SQ_GS_VERT_ITEMSIZE
// DB
- EREG(ib, DB_DEPTH_INFO, 0);
EREG(ib, DB_DEPTH_CONTROL, 0);
PACK0(ib, DB_RENDER_CONTROL, 2);
E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
diff --git a/src/radeon.h b/src/radeon.h
index 55d673a..d66cdd9 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1035,6 +1035,12 @@ typedef struct {
uint64_t vram_size;
uint64_t gart_size;
drmmode_rec drmmode;
+ /* r6xx+ tile config */
+ uint32_t tile_config;
+ int group_bytes;
+ int num_channels;
+ int num_banks;
+ int r7xx_bank_op;
#else
/* fake bool */
Bool cs;
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index a0ed085..9697bbc 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -101,7 +101,10 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
switch(attachments[i]) {
case DRI2BufferDepth:
case DRI2BufferDepthStencil:
- flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+ else
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
break;
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
@@ -183,7 +186,10 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
switch(attachment) {
case DRI2BufferDepth:
case DRI2BufferDepthStencil:
- flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+ else
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
break;
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 7dd792e..814c864 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -430,11 +430,27 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
tiling &= ~RADEON_TILING_MACRO;
}
- if (tiling) {
- height = RADEON_ALIGN(height, 16);
- pixmap_align = 256;
- } else
- pixmap_align = 64;
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ int bpe = bitsPerPixel / 8;
+
+ if (tiling & RADEON_TILING_MACRO) {
+ height = RADEON_ALIGN(height, info->num_banks * 8);
+ pixmap_align = MAX(info->num_banks,
+ (((info->group_bytes / 8) / bpe) * info->num_banks)) * 8 * bpe;
+ } else if (tiling & RADEON_TILING_MICRO) {
+ height = RADEON_ALIGN(height, 8);
+ pixmap_align = MAX(8, (info->group_bytes / (8 * bpe))) * bpe;
+ } else {
+ height = RADEON_ALIGN(height, 8);
+ pixmap_align = 256; /* 8 * bpe */
+ }
+ } else {
+ if (tiling) {
+ height = RADEON_ALIGN(height, 16);
+ pixmap_align = 256;
+ } else
+ pixmap_align = 64;
+ }
padded_width = ((width * bitsPerPixel + FB_MASK) >> FB_SHIFT) * sizeof(FbBits);
padded_width = RADEON_ALIGN(padded_width, pixmap_align);
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 772be8f..ba13071 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -421,6 +421,74 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
return TRUE;
}
+static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct drm_radeon_info ginfo;
+ int r;
+ uint32_t tmp;
+
+ if (info->ChipFamily < CHIP_FAMILY_R600)
+ return FALSE;
+
+#ifndef RADEON_INFO_TILING_CONFIG
+#define RADEON_INFO_TILING_CONFIG 0x6
+#endif
+
+ memset(&ginfo, 0, sizeof(ginfo));
+ ginfo.request = RADEON_INFO_TILING_CONFIG;
+ ginfo.value = (uintptr_t)&tmp;
+ r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
+ if (r)
+ return FALSE;
+
+ info->tile_config = tmp;
+ info->r7xx_bank_op = 0;
+ if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
+ /* for now */
+ return FALSE;
+ } else {
+ switch((info->tile_config & 0xe) >> 1) {
+ case 0:
+ info->num_channels = 1;
+ break;
+ case 1:
+ info->num_channels = 2;
+ break;
+ case 2:
+ info->num_channels = 4;
+ break;
+ case 3:
+ info->num_channels = 8;
+ break;
+ default:
+ return FALSE;
+ }
+ switch((info->tile_config & 0x30) >> 4) {
+ case 0:
+ info->num_banks = 4;
+ break;
+ case 1:
+ info->num_banks = 8;
+ break;
+ default:
+ return FALSE;
+ }
+ switch((info->tile_config & 0xc0) >> 6) {
+ case 0:
+ info->group_bytes = 256;
+ break;
+ case 1:
+ info->group_bytes = 512;
+ break;
+ default:
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
{
RADEONInfoPtr info;
@@ -484,18 +552,6 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
if (!radeon_alloc_dri(pScrn))
return FALSE;
- colorTilingDefault = info->ChipFamily >= CHIP_FAMILY_R300 &&
- info->ChipFamily <= CHIP_FAMILY_RS740;
-
- info->allowColorTiling = xf86ReturnOptValBool(info->Options,
- OPTION_COLOR_TILING, colorTilingDefault);
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Color tiling is not yet supported on R600/R700\n");
- info->allowColorTiling = FALSE;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
-
if (radeon_open_drm_master(pScrn) == FALSE) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
goto fail;
@@ -509,6 +565,25 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
goto fail;
}
+ colorTilingDefault = info->ChipFamily >= CHIP_FAMILY_R300 &&
+ info->ChipFamily <= CHIP_FAMILY_RS740;
+
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->dri->pKernelDRMVersion->version_minor >= 6) {
+ info->allowColorTiling = xf86ReturnOptValBool(info->Options,
+ OPTION_COLOR_TILING, colorTilingDefault);
+ if (info->allowColorTiling)
+ info->allowColorTiling = r600_get_tile_config(pScrn);
+ } else
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n");
+ } else
+ info->allowColorTiling = xf86ReturnOptValBool(info->Options,
+ OPTION_COLOR_TILING, colorTilingDefault);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
+
if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
goto fail;
@@ -1038,8 +1113,10 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
ErrorF("Failed to map cursor buffer memory\n");
}
}
+ /* no tiled scanout on r6xx+ yet */
if (info->allowColorTiling) {
- tiling_flags |= RADEON_TILING_MACRO;
+ if (info->ChipFamily < CHIP_FAMILY_R600)
+ tiling_flags |= RADEON_TILING_MACRO;
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (cpp) {
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