xf86-video-ati: Branch 'master'
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Aug 2 11:25:39 PDT 2010
src/r600_exa.c | 53 ++++++-----------------------------------
src/r600_state.h | 7 +----
src/r600_textured_videofuncs.c | 38 +++++------------------------
src/r6xx_accel.c | 52 ++++++++++++++++++++++++++--------------
4 files changed, 52 insertions(+), 98 deletions(-)
New commits:
commit a456587b77ae357750179a50f8db2a17c0f2738e
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Aug 2 14:24:41 2010 -0400
r6xx/r7xx: move syrface sync emit to the functions that emit surface info
reduces code duplication.
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 78b0ed2..638bd38 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -195,7 +195,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
dst.height = pPix->drawable.height;
dst.bpp = pPix->drawable.bitsPerPixel;
dst.domain = RADEON_GEM_DOMAIN_VRAM;
-
+
if (!R600SetAccelState(pScrn,
NULL,
NULL,
@@ -218,24 +218,15 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
/* Shader */
-
- /* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->vs_size, accel_state->vs_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
vs_conf.shader_addr = accel_state->vs_mc_addr;
+ vs_conf.shader_size = accel_state->vs_size;
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
- /* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->ps_size, accel_state->ps_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
ps_conf.shader_addr = accel_state->ps_mc_addr;
+ ps_conf.shader_size = accel_state->ps_size;
ps_conf.num_gprs = 1;
ps_conf.stack_size = 0;
ps_conf.uncached_first_inst = 1;
@@ -399,24 +390,15 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
/* Shader */
-
- /* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->vs_size, accel_state->vs_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
vs_conf.shader_addr = accel_state->vs_mc_addr;
+ vs_conf.shader_size = accel_state->vs_size;
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
- /* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->ps_size, accel_state->ps_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
ps_conf.shader_addr = accel_state->ps_mc_addr;
+ ps_conf.shader_size = accel_state->ps_size;
ps_conf.num_gprs = 1;
ps_conf.stack_size = 0;
ps_conf.uncached_first_inst = 1;
@@ -425,11 +407,6 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
ps_conf.bo = accel_state->shaders_bo;
ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
- /* flush texture cache */
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
- accel_state->src_size[0], accel_state->src_obj[0].offset,
- accel_state->src_obj[0].bo, accel_state->src_obj[0].domain, 0);
-
/* Texture */
tex_res.id = 0;
tex_res.w = accel_state->src_obj[0].width;
@@ -439,6 +416,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.dim = SQ_TEX_DIM_2D;
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
if (accel_state->src_obj[0].bpp == 8) {
@@ -950,11 +928,6 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
break;
}
- /* flush texture cache */
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
- accel_state->src_size[unit], accel_state->src_obj[unit].offset,
- accel_state->src_obj[unit].bo, accel_state->src_obj[unit].domain, 0);
-
/* Texture */
tex_res.id = unit;
tex_res.w = w;
@@ -964,6 +937,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.dim = SQ_TEX_DIM_2D;
tex_res.base = accel_state->src_obj[unit].offset;
tex_res.mip_base = accel_state->src_obj[unit].offset;
+ tex_res.size = accel_state->src_size[unit];
tex_res.format = R600TexFormats[i].card_fmt;
tex_res.bo = accel_state->src_obj[unit].bo;
tex_res.mip_bo = accel_state->src_obj[unit].bo;
@@ -1380,24 +1354,15 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
}
/* Shader */
-
- /* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->vs_size, accel_state->vs_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
vs_conf.shader_addr = accel_state->vs_mc_addr;
+ vs_conf.shader_size = accel_state->vs_size;
vs_conf.num_gprs = 3;
vs_conf.stack_size = 1;
vs_conf.bo = accel_state->shaders_bo;
vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
- /* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->ps_size, accel_state->ps_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
ps_conf.shader_addr = accel_state->ps_mc_addr;
+ ps_conf.shader_size = accel_state->ps_size;
ps_conf.num_gprs = 3;
ps_conf.stack_size = 1;
ps_conf.uncached_first_inst = 1;
diff --git a/src/r600_state.h b/src/r600_state.h
index 710ec6d..4e65bc1 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -70,6 +70,7 @@ typedef struct {
/* Shader */
typedef struct {
uint64_t shader_addr;
+ uint32_t shader_size;
int num_gprs;
int stack_size;
int dx10_clamp;
@@ -113,6 +114,7 @@ typedef struct {
int format;
uint64_t base;
uint64_t mip_base;
+ uint32_t size;
int format_comp_x;
int format_comp_y;
int format_comp_z;
@@ -283,9 +285,6 @@ start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
void
set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
void
-cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr,
- struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain);
-void
cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
@@ -298,8 +297,6 @@ set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *co
void
set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
void
-set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain);
-void
set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
void
set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 9f91f6e..e18a9c8 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -229,24 +229,15 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
}
/* Shader */
-
- /* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->vs_size, accel_state->vs_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
vs_conf.shader_addr = accel_state->vs_mc_addr;
+ vs_conf.shader_size = accel_state->vs_size;
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
- /* flush SQ cache */
- cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit,
- accel_state->ps_size, accel_state->ps_mc_addr,
- accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-
ps_conf.shader_addr = accel_state->ps_mc_addr;
+ ps_conf.shader_size = accel_state->ps_size;
ps_conf.num_gprs = 3;
ps_conf.stack_size = 1;
ps_conf.uncached_first_inst = 1;
@@ -265,11 +256,6 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
case FOURCC_I420:
accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
- /* flush texture cache */
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0],
- accel_state->src_obj[0].offset,
- accel_state->src_obj[0].bo, accel_state->src_obj[0].domain, 0);
-
/* Y texture */
tex_res.id = 0;
tex_res.w = accel_state->src_obj[0].width;
@@ -279,6 +265,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.dim = SQ_TEX_DIM_2D;
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
@@ -310,11 +297,6 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
/* U or V texture */
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
- accel_state->src_size[0] / 4,
- accel_state->src_obj[0].offset + pPriv->planev_offset,
- accel_state->src_obj[0].bo, accel_state->src_obj[0].domain, 0);
-
tex_res.id = 1;
tex_res.format = FMT_8;
tex_res.w = accel_state->src_obj[0].width >> 1;
@@ -328,6 +310,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset;
+ tex_res.size = accel_state->src_size[0] / 4;
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* U or V sampler */
@@ -335,11 +318,6 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
/* U or V texture */
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
- accel_state->src_size[0] / 4,
- accel_state->src_obj[0].offset + pPriv->planeu_offset,
- accel_state->src_obj[0].bo, accel_state->src_obj[0].domain, 0);
-
tex_res.id = 2;
tex_res.format = FMT_8;
tex_res.w = accel_state->src_obj[0].width >> 1;
@@ -353,6 +331,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset;
+ tex_res.size = accel_state->src_size[0] / 4;
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
@@ -364,11 +343,6 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
default:
accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
- /* flush texture cache */
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0],
- accel_state->src_obj[0].offset,
- accel_state->src_obj[0].bo, accel_state->src_obj[0].domain, 0);
-
/* Y texture */
tex_res.id = 0;
tex_res.w = accel_state->src_obj[0].width;
@@ -378,6 +352,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.dim = SQ_TEX_DIM_2D;
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
@@ -430,6 +405,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset;
tex_res.mip_base = accel_state->src_obj[0].offset;
+ tex_res.size = accel_state->src_size[0];
set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
/* UV sampler */
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 5b3e32c..b34b6c5 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -270,7 +270,7 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_
END_BATCH();
}
-void
+static void
cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr,
struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain)
{
@@ -413,6 +413,11 @@ vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t dom
if (vs_conf->uncached_first_inst)
sq_pgm_resources |= UNCACHED_FIRST_INST_bit;
+ /* flush SQ cache */
+ cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
+ vs_conf->shader_size, vs_conf->shader_addr,
+ vs_conf->bo, domain, 0);
+
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
RELOC_BATCH(vs_conf->bo, domain, 0);
@@ -442,6 +447,11 @@ ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t dom
if (ps_conf->clamp_consts)
sq_pgm_resources |= CLAMP_CONSTS_bit;
+ /* flush SQ cache */
+ cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
+ ps_conf->shader_size, ps_conf->shader_addr,
+ ps_conf->bo, domain, 0);
+
BEGIN_BATCH(3 + 2);
EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
RELOC_BATCH(ps_conf->bo, domain, 0);
@@ -480,10 +490,11 @@ set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val)
END_BATCH();
}
-void
+static void
set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
uint32_t sq_vtx_constant_word2;
sq_vtx_constant_word2 = ((((res->vb_addr) >> 32) & BASE_ADDRESS_HI_mask) |
@@ -500,6 +511,22 @@ set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t
if (res->srf_mode_all)
sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit;
+ /* flush vertex cache */
+ if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
+ (info->ChipFamily == CHIP_FAMILY_RV620) ||
+ (info->ChipFamily == CHIP_FAMILY_RS780) ||
+ (info->ChipFamily == CHIP_FAMILY_RS880) ||
+ (info->ChipFamily == CHIP_FAMILY_RV710))
+ cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
+ accel_state->vb_offset, accel_state->vb_mc_addr,
+ res->bo,
+ domain, 0);
+ else
+ cp_set_surface_sync(pScrn, ib, VC_ACTION_ENA_bit,
+ accel_state->vb_offset, accel_state->vb_mc_addr,
+ res->bo,
+ domain, 0);
+
BEGIN_BATCH(9 + 2);
PACK0(ib, SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7);
E32(ib, res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS
@@ -566,6 +593,11 @@ set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint3
if (tex_res->interlaced)
sq_tex_resource_word6 |= INTERLACED_bit;
+ /* flush texture cache */
+ cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
+ tex_res->size, tex_res->base,
+ tex_res->bo, domain, 0);
+
BEGIN_BATCH(9 + 4);
PACK0(ib, SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7);
E32(ib, sq_tex_resource_word0);
@@ -1133,22 +1165,6 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
return;
}
- /* flush vertex cache */
- if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
- (info->ChipFamily == CHIP_FAMILY_RV620) ||
- (info->ChipFamily == CHIP_FAMILY_RS780) ||
- (info->ChipFamily == CHIP_FAMILY_RS880) ||
- (info->ChipFamily == CHIP_FAMILY_RV710))
- cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
- accel_state->vb_offset, accel_state->vb_mc_addr,
- accel_state->vb_bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- else
- cp_set_surface_sync(pScrn, accel_state->ib, VC_ACTION_ENA_bit,
- accel_state->vb_offset, accel_state->vb_mc_addr,
- accel_state->vb_bo,
- RADEON_GEM_DOMAIN_GTT, 0);
-
/* Vertex buffer setup */
accel_state->vb_size = accel_state->vb_offset - accel_state->vb_start_op;
vtx_res.id = SQ_VTX_RESOURCE_vs;
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