xf86-video-ati: Branch 'master'
Alex Deucher
agd5f at kemper.freedesktop.org
Fri Sep 25 13:45:26 PDT 2009
src/r600_state.h | 2
src/r600_textured_videofuncs.c | 7 --
src/r6xx_accel.c | 64 ++++++++++----------
src/radeon.h | 4 -
src/radeon_commonfuncs.c | 122 ++++++++++++++++-----------------------
src/radeon_exa.c | 9 +-
src/radeon_textured_videofuncs.c | 28 ++------
7 files changed, 104 insertions(+), 132 deletions(-)
New commits:
commit 3efecebb10de7f7bacf9f8c57ae20fd508097294
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Sep 25 14:44:41 2009 -0400
radeon: fix vline handling for kms
drm crtc ids do not correspond to actual hw crtcs,
as such the vline stuff was never enabled for Xv.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/r600_state.h b/src/r600_state.h
index cb039d4..46c18f9 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -286,7 +286,7 @@ void
cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr,
struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain);
void
-cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, int crtc, int start, int stop);
+cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
void
fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf);
void
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index e30cfcb..5e6c561 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -579,14 +579,11 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pPriv->drw_x + pPriv->dst_w,
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
- if (crtc) {
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
+ if (crtc)
cp_wait_vline_sync(pScrn, accel_state->ib, pPixmap,
- radeon_crtc->crtc_id,
+ crtc,
pPriv->drw_y - crtc->y,
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
- }
}
while (nBox--) {
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 0e2f8a9..f5e6bce 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -313,12 +313,10 @@ cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_
/* inserts a wait for vline in the command stream */
void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
- int crtc, int start, int stop)
+ xf86CrtcPtr crtc, int start, int stop)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
uint32_t offset;
- RADEONCrtcPrivatePtr radeon_crtc;
//XXX FIXME
#if defined(XF86DRM_MODE)
@@ -326,49 +324,53 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
return;
#endif
- if ((crtc < 0) || (crtc > 1))
+ if (!crtc)
return;
if (stop < start)
return;
- if (!xf86_config->crtc[crtc]->enabled)
+ if (!crtc->enabled)
return;
+ {
#ifdef USE_EXA
- if (info->useEXA)
- offset = exaGetPixmapOffset(pPix);
- else
+ if (info->useEXA)
+ offset = exaGetPixmapOffset(pPix);
+ else
#endif
- offset = pPix->devPrivate.ptr - info->FB;
+ offset = pPix->devPrivate.ptr - info->FB;
- /* if drawing to front buffer */
- if (offset != 0)
- return;
+ /* if drawing to front buffer */
+ if (offset != 0)
+ return;
+ }
start = max(start, 0);
- stop = min(stop, xf86_config->crtc[crtc]->mode.VDisplay);
+ stop = min(stop, crtc->mode.VDisplay);
- if (start > xf86_config->crtc[crtc]->mode.VDisplay)
+ if (start > crtc->mode.VDisplay)
return;
- radeon_crtc = xf86_config->crtc[crtc]->driver_private;
-
- BEGIN_BATCH(10);
- /* set the VLINE range */
- EREG(ib, AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
- (start << AVIVO_D1MODE_VLINE_START_SHIFT) |
- (stop << AVIVO_D1MODE_VLINE_END_SHIFT));
-
- /* tell the CP to poll the VLINE state register */
- PACK3(ib, IT_WAIT_REG_MEM, 6);
- E32(ib, IT_WAIT_REG | IT_WAIT_EQ);
- E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS + radeon_crtc->crtc_offset));
- E32(ib, 0);
- E32(ib, 0); // Ref value
- E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask
- E32(ib, 10); // Wait interval
- END_BATCH();
+ {
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+ BEGIN_BATCH(10);
+ /* set the VLINE range */
+ EREG(ib, AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
+ (start << AVIVO_D1MODE_VLINE_START_SHIFT) |
+ (stop << AVIVO_D1MODE_VLINE_END_SHIFT));
+
+ /* tell the CP to poll the VLINE state register */
+ PACK3(ib, IT_WAIT_REG_MEM, 6);
+ E32(ib, IT_WAIT_REG | IT_WAIT_EQ);
+ E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS + radeon_crtc->crtc_offset));
+ E32(ib, 0);
+ E32(ib, 0); // Ref value
+ E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask
+ E32(ib, 10); // Wait interval
+ END_BATCH();
+ }
}
void
diff --git a/src/radeon.h b/src/radeon.h
index fc21955..e4f5334 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1111,11 +1111,11 @@ extern Bool radeon_card_posted(ScrnInfoPtr pScrn);
#ifdef XF86DRI
extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix,
- int crtc, int start, int stop);
+ xf86CrtcPtr crtc, int start, int stop);
#endif
extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix,
- int crtc, int start, int stop);
+ xf86CrtcPtr crtc, int start, int stop);
/* radeon_crtc.c */
extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode);
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 6387e4f..c0625c4 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -825,55 +825,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
}
-#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
-void drmmode_wait_for_vline(ScrnInfoPtr pScrn, PixmapPtr pPix,
- int crtc, int start, int stop)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[crtc]->driver_private;
- ACCEL_PREAMBLE();
-
- BEGIN_ACCEL(3);
-
- if (IS_AVIVO_VARIANT) {
- uint32_t reg = AVIVO_D1MODE_VLINE_START_END; /* this is just a marker */
- OUT_ACCEL_REG(reg,
- ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
- (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
- AVIVO_D1MODE_VLINE_INV));
- } else {
- OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */
- ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
- (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
- RADEON_CRTC_GUI_TRIG_VLINE_INV |
- RADEON_CRTC_GUI_TRIG_VLINE_STALL));
- }
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
- RADEON_ENG_DISPLAY_SELECT_CRTC0));
-
- OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0));
- OUT_RING(drmmode_crtc->mode_crtc->crtc_id);
- FINISH_ACCEL();
-}
-#endif
-
/* inserts a wait for vline in the command stream */
void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
- int crtc, int start, int stop)
+ xf86CrtcPtr crtc, int start, int stop)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
uint32_t offset;
ACCEL_PREAMBLE();
- if ((crtc < 0) || (crtc > 1))
+ if (!crtc)
return;
if (stop < start)
return;
- if (!xf86_config->crtc[crtc]->enabled)
+ if (!crtc->enabled)
return;
if (info->cs) {
@@ -893,50 +859,68 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
}
start = max(start, 0);
- stop = min(stop, xf86_config->crtc[crtc]->mode.VDisplay);
+ stop = min(stop, crtc->mode.VDisplay);
- if (start > xf86_config->crtc[crtc]->mode.VDisplay)
+ if (start > crtc->mode.VDisplay)
return;
#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
- if (info->kms_enabled) {
- drmmode_wait_for_vline(pScrn, pPix, crtc, start, stop);
- return;
- }
-#endif
-
- BEGIN_ACCEL(2);
-
- if (IS_AVIVO_VARIANT) {
- RADEONCrtcPrivatePtr radeon_crtc = xf86_config->crtc[crtc]->driver_private;
+ if (info->cs) {
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
- OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
- ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
- (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
- AVIVO_D1MODE_VLINE_INV));
- } else {
- if (crtc == 0)
- OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE,
- ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
- (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
- RADEON_CRTC_GUI_TRIG_VLINE_INV |
- RADEON_CRTC_GUI_TRIG_VLINE_STALL));
- else
- OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE,
+ BEGIN_ACCEL(3);
+ if (IS_AVIVO_VARIANT) {
+ OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
+ ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
+ (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
+ AVIVO_D1MODE_VLINE_INV));
+ } else {
+ OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */
((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
(stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
RADEON_CRTC_GUI_TRIG_VLINE_INV |
RADEON_CRTC_GUI_TRIG_VLINE_STALL));
- }
-
- if (crtc == 0)
+ }
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
RADEON_ENG_DISPLAY_SELECT_CRTC0));
- else
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
- RADEON_ENG_DISPLAY_SELECT_CRTC1));
- FINISH_ACCEL();
+ OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0));
+ OUT_RING(drmmode_crtc->mode_crtc->crtc_id);
+ FINISH_ACCEL();
+ } else
+#endif
+ {
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+ BEGIN_ACCEL(2);
+ if (IS_AVIVO_VARIANT) {
+ OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
+ ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
+ (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
+ AVIVO_D1MODE_VLINE_INV));
+ } else {
+ if (radeon_crtc->crtc_id == 0)
+ OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE,
+ ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
+ (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
+ RADEON_CRTC_GUI_TRIG_VLINE_INV |
+ RADEON_CRTC_GUI_TRIG_VLINE_STALL));
+ else
+ OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE,
+ ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
+ (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
+ RADEON_CRTC_GUI_TRIG_VLINE_INV |
+ RADEON_CRTC_GUI_TRIG_VLINE_STALL));
+ }
+
+ if (radeon_crtc->crtc_id == 0)
+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
+ RADEON_ENG_DISPLAY_SELECT_CRTC0));
+ else
+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
+ RADEON_ENG_DISPLAY_SELECT_CRTC1));
+ FINISH_ACCEL();
+ }
}
/* MMIO:
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 7b9164e..6cf9598 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -211,11 +211,12 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset)
* syncing per-blit is unrealistic so,
* we sync to whichever crtc has a larger area.
*/
-int RADEONBiggerCrtcArea(PixmapPtr pPix)
+xf86CrtcPtr RADEONBiggerCrtcArea(PixmapPtr pPix)
{
ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int c, crtc_num = -1, area = 0;
+ int c, area = 0;
+ xf86CrtcPtr ret_crtc = NULL;
for (c = 0; c < xf86_config->num_crtc; c++) {
xf86CrtcPtr crtc = xf86_config->crtc[c];
@@ -225,11 +226,11 @@ int RADEONBiggerCrtcArea(PixmapPtr pPix)
if ((crtc->mode.HDisplay * crtc->mode.VDisplay) > area) {
area = crtc->mode.HDisplay * crtc->mode.VDisplay;
- crtc_num = c;
+ ret_crtc = crtc;
}
}
- return crtc_num;
+ return ret_crtc;
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index f069d8f..d26e7c0 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -355,14 +355,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
pPriv->drw_x + pPriv->dst_w,
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
- if (crtc) {
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
+ if (crtc)
FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
- radeon_crtc->crtc_id,
+ crtc,
pPriv->drw_y - crtc->y,
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
- }
}
/*
* Rendering of the actual polygon is done in two different
@@ -916,14 +913,11 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pPriv->drw_x + pPriv->dst_w,
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
- if (crtc) {
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
+ if (crtc)
FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
- radeon_crtc->crtc_id,
+ crtc,
pPriv->drw_y - crtc->y,
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
- }
}
/*
* Rendering of the actual polygon is done in two different
@@ -2290,14 +2284,11 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pPriv->drw_x + pPriv->dst_w,
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
- if (crtc) {
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
+ if (crtc)
FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
- radeon_crtc->crtc_id,
+ crtc,
pPriv->drw_y - crtc->y,
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
- }
}
/*
* Rendering of the actual polygon is done in two different
@@ -3867,14 +3858,11 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
pPriv->drw_x + pPriv->dst_w,
pPriv->drw_y,
pPriv->drw_y + pPriv->dst_h);
- if (crtc) {
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
+ if (crtc)
FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap,
- radeon_crtc->crtc_id,
+ crtc,
pPriv->drw_y - crtc->y,
(pPriv->drw_y - crtc->y) + pPriv->dst_h);
- }
}
/*
* Rendering of the actual polygon is done in two different
More information about the xorg-commit
mailing list