xf86-video-ati: Branch 'master'

[Alex Deucher]

 src/legacy_output.c |   19 +++++++++++++++----
 src/radeon_reg.h    |    2 +-
 2 files changed, 16 insertions(+), 5 deletions(-)

New commits:
commit c4ab50c5eafca3d04129a72453496eb8afb26b34
Author: Alex Deucher <alexdeucher at gmail.com>
Date:   Tue Sep 1 13:43:00 2009 -0400

    radeon: add some notes about DVO setup

diff --git a/src/legacy_output.c b/src/legacy_output.c
index 7134ee1..73c86b9 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -1216,14 +1216,25 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
 	if ((info->Chipset == PCI_CHIP_RV350_NP) &&
 	    (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1028) &&
 	    (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x2001))
-	    save->fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */
+	    save->fp2_gen_cntl |= R200_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */
 	else
-	    save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
+	    save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R200_FP2_DVO_CLOCK_MODE_SINGLE;
+    }
+
 #if 0
-	if (mode->Clock > 165000)
+    /* DVO configurations:
+     * SDR single channel (data rate 165 Mhz, port width 12 bits)
+     * DDR single channel (data rate 330 Mhz, port width 12 bits)
+     * SDR dual   channel (data rate 330 Mhz, port width 24 bits)
+     * - dual channel is only available on r3xx+
+     */
+    if (info->ChipFamily >= CHIP_FAMILY_R200) {
+	if (sdr)
+	    save->fp2_gen_cntl |= R200_FP2_DVO_RATE_SEL_SDR;
+	if (IS_R300_VARIANT && dual channel)
 	    save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;
-#endif
     }
+#endif
 
     if (IsPrimary) {
 	if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 3a4eda1..5467286 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -882,7 +882,7 @@
 #       define RADEON_FP2_DVO_EN               (1 << 25)
 #       define RADEON_FP2_DVO_RATE_SEL_SDR     (1 << 26)
 #       define R200_FP2_DVO_RATE_SEL_SDR       (1 << 27)
-#       define R300_FP2_DVO_CLOCK_MODE_SINGLE  (1 << 28)
+#       define R200_FP2_DVO_CLOCK_MODE_SINGLE  (1 << 28)
 #       define R300_FP2_DVO_DUAL_CHANNEL_EN    (1 << 29)
 #define RADEON_FP_H_SYNC_STRT_WID           0x02c4
 #define RADEON_FP_H2_SYNC_STRT_WID          0x03c4