xf86-video-ati: Branch 'master' - 2 commits

[Alex Deucher]

 src/atombios_crtc.c   |   10 ++++++++++
 src/radeon_atombios.c |    9 +++++++++
 src/radeon_output.c   |    7 ++++++-
 3 files changed, 25 insertions(+), 1 deletion(-)

New commits:
commit 5a0019126a57138ee506d9a66738c9e8b75cbb96
Author: Alex Deucher <alexdeucher at gmail.com>
Date:   Tue Oct 27 11:39:06 2009 -0400

    radeon: fix DVO on AVIVO chips
    
    DVO generally requires 2x ppll on AVIVO cards due to the
    way the tmds chip is wired up.  Because of this, disable
    cloning of DVO outputs.
    
    fixes fdo bug 21857.
    
    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>

diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index d513c13..fb7728f 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -324,6 +324,16 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
 	else
 	    pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 
+	for (i = 0; i < xf86_config->num_output; i++) {
+	    xf86OutputPtr output = xf86_config->output[i];
+	    if (output->crtc == crtc) {
+		radeon_encoder = radeon_get_encoder(output);
+		/* DVO seems to want 2x pixel clock */
+		if (radeon_encoder && (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
+		    sclock *= 2;
+	    }
+	}
+
 	/* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
 	if (radeon_crtc->crtc_id == 0) {
 	    temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
diff --git a/src/radeon_output.c b/src/radeon_output.c
index a252363..6e00ab8 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2634,16 +2634,21 @@ radeon_output_clones (ScrnInfoPtr pScrn, xf86OutputPtr output)
     int			index_mask = 0;
 
     /* DIG routing gets problematic */
-    if (IS_DCE32_VARIANT)
+    if (info->ChipFamily >= CHIP_FAMILY_R600)
 	return index_mask;
 
     /* LVDS is too wacky */
     if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT))
 	return index_mask;
 
+    /* TV requires very specific timing */
     if (radeon_output->devices & (ATOM_DEVICE_TV_SUPPORT))
 	return index_mask;
 
+    /* DVO requires 2x ppll clocks depending on the tmds chip */
+    if (radeon_output->devices & (ATOM_DEVICE_DFP2_SUPPORT))
+	return index_mask;
+
     for (o = 0; o < config->num_output; o++) {
 	xf86OutputPtr clone = config->output[o];
 	RADEONOutputPrivatePtr radeon_clone = clone->driver_private;
commit 2a6eeec72d6bb04a32225883f431c1d2e8cff123
Author: Alex Deucher <alexdeucher at gmail.com>
Date:   Tue Oct 27 11:18:44 2009 -0400

    atom: loosen pll min output limits
    
    Limiting the pll output range is a good thing generally as
    it limits the number of possible pll combinations for a given
    frequency presumably to the ones that work best on each card.
    That's why the limits are in the bios tables. However, certain
    duallink DVI monitors seem to like pll combinations that would
    be limited by this at least on pre-DCE 3.0 r6xx hardware.  This
    might need to be adjusted per family or per clock range in the
    future.
    
    Fixes fdo bug 24727.
    
    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>

diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index a8eded6..1f4b9dc 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -2171,6 +2171,15 @@ RADEONGetATOMClockInfo(ScrnInfoPtr pScrn)
     if (pll->pll_out_min == 0)
 	pll->pll_out_min = 64800;
 
+    /* limiting the range is a good thing in most cases
+     * as it limits the number of matching pll combinations,
+     * however, some duallink DVI monitors seem to prefer combinations that
+     * would be limited by this.  This may need to be revisited
+     * per chip family.
+     */
+    if (pll->pll_out_min > 64800)
+	pll->pll_out_min = 64800;
+
     return TRUE;
 }