xf86-video-ati: Branch 'master' - 2 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Nov 16 16:19:30 PST 2009
src/r600_exa.c | 57 +++++++++++++++++-------------------------------------
src/r600_shader.c | 52 ++++++++++++++++++++++++-------------------------
2 files changed, 44 insertions(+), 65 deletions(-)
New commits:
commit 7587ce16ab0380337fe801f457c1d1d9b4141cc5
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Nov 16 19:16:03 2009 -0500
r600: remove un-needed format conversions
we do the normalization and xforms in the vertex
shader.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 7d8cf46..ca1a1fa 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -1901,23 +1901,11 @@ static void R600Composite(PixmapPtr pDst,
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
float *vb;
- xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
/* ErrorF("R600Composite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
- srcTopLeft.x = IntToxFixed(srcX);
- srcTopLeft.y = IntToxFixed(srcY);
- srcTopRight.x = IntToxFixed(srcX + w);
- srcTopRight.y = IntToxFixed(srcY);
- srcBottomLeft.x = IntToxFixed(srcX);
- srcBottomLeft.y = IntToxFixed(srcY + h);
- srcBottomRight.x = IntToxFixed(srcX + w);
- srcBottomRight.y = IntToxFixed(srcY + h);
-
if (accel_state->msk_pic) {
- xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
-
if (((accel_state->vb_index + 3) * 24) > accel_state->vb_total) {
R600DoneComposite(pDst);
r600_cp_start(pScrn);
@@ -1925,35 +1913,26 @@ static void R600Composite(PixmapPtr pDst,
vb = (pointer)((char*)accel_state->vb_ptr+accel_state->vb_index*24);
- maskTopLeft.x = IntToxFixed(maskX);
- maskTopLeft.y = IntToxFixed(maskY);
- maskTopRight.x = IntToxFixed(maskX + w);
- maskTopRight.y = IntToxFixed(maskY);
- maskBottomLeft.x = IntToxFixed(maskX);
- maskBottomLeft.y = IntToxFixed(maskY + h);
- maskBottomRight.x = IntToxFixed(maskX + w);
- maskBottomRight.y = IntToxFixed(maskY + h);
-
vb[0] = (float)dstX;
vb[1] = (float)dstY;
- vb[2] = xFixedToFloat(srcTopLeft.x);
- vb[3] = xFixedToFloat(srcTopLeft.y);
- vb[4] = xFixedToFloat(maskTopLeft.x);
- vb[5] = xFixedToFloat(maskTopLeft.y);
+ vb[2] = (float)srcX;
+ vb[3] = (float)srcY;
+ vb[4] = (float)maskX;
+ vb[5] = (float)maskY;
vb[6] = (float)dstX;
vb[7] = (float)(dstY + h);
- vb[8] = xFixedToFloat(srcBottomLeft.x);
- vb[9] = xFixedToFloat(srcBottomLeft.y);
- vb[10] = xFixedToFloat(maskBottomLeft.x);
- vb[11] = xFixedToFloat(maskBottomLeft.y);
+ vb[8] = (float)srcX;
+ vb[9] = (float)(srcY + h);
+ vb[10] = (float)maskX;
+ vb[11] = (float)(maskY + h);
vb[12] = (float)(dstX + w);
vb[13] = (float)(dstY + h);
- vb[14] = xFixedToFloat(srcBottomRight.x);
- vb[15] = xFixedToFloat(srcBottomRight.y);
- vb[16] = xFixedToFloat(maskBottomRight.x);
- vb[17] = xFixedToFloat(maskBottomRight.y);
+ vb[14] = (float)(srcX + w);
+ vb[15] = (float)(srcY + h);
+ vb[16] = (float)(maskX + w);
+ vb[17] = (float)(maskY + h);
} else {
if (((accel_state->vb_index + 3) * 16) > accel_state->vb_total) {
@@ -1965,18 +1944,18 @@ static void R600Composite(PixmapPtr pDst,
vb[0] = (float)dstX;
vb[1] = (float)dstY;
- vb[2] = xFixedToFloat(srcTopLeft.x);
- vb[3] = xFixedToFloat(srcTopLeft.y);
+ vb[2] = (float)srcX;
+ vb[3] = (float)srcY;
vb[4] = (float)dstX;
vb[5] = (float)(dstY + h);
- vb[6] = xFixedToFloat(srcBottomLeft.x);
- vb[7] = xFixedToFloat(srcBottomLeft.y);
+ vb[6] = (float)srcX;
+ vb[7] = (float)(srcY + h);
vb[8] = (float)(dstX + w);
vb[9] = (float)(dstY + h);
- vb[10] = xFixedToFloat(srcBottomRight.x);
- vb[11] = xFixedToFloat(srcBottomRight.y);
+ vb[10] = (float)(srcX + w);
+ vb[11] = (float)(srcY + h);
}
accel_state->vb_index += 3;
commit ba605b5c9ff48765f2b66960aa4cc81b6235d012
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Nov 16 19:00:52 2009 -0500
r600: fix num format in vtx fetch
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/r600_shader.c b/src/r600_shader.c
index 584deb4..e78aa32 100644
--- a/src/r600_shader.c
+++ b/src/r600_shader.c
@@ -106,9 +106,9 @@ int R600_solid_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_Z(SQ_SEL_0),
DST_SEL_W(SQ_SEL_1),
USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
ENDIAN_SWAP(ENDIAN_NONE),
@@ -336,9 +336,9 @@ int R600_copy_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_Z(SQ_SEL_0),
DST_SEL_W(SQ_SEL_1),
USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
ENDIAN_SWAP(ENDIAN_NONE),
@@ -361,9 +361,9 @@ int R600_copy_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_Z(SQ_SEL_0),
DST_SEL_W(SQ_SEL_1),
USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(8),
ENDIAN_SWAP(ENDIAN_NONE),
@@ -592,7 +592,7 @@ int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_W(SQ_SEL_1),
USE_CONST_FIELDS(0),
DATA_FORMAT(FMT_32_32_FLOAT),
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
@@ -617,7 +617,7 @@ int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_W(SQ_SEL_1),
USE_CONST_FIELDS(0),
DATA_FORMAT(FMT_32_32_FLOAT),
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(8),
@@ -1817,9 +1817,9 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_Z(SQ_SEL_0),
DST_SEL_W(SQ_SEL_1),
USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
ENDIAN_SWAP(ENDIAN_NONE),
@@ -1842,9 +1842,9 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_Z(SQ_SEL_1),
DST_SEL_W(SQ_SEL_0),
USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(8),
ENDIAN_SWAP(ENDIAN_NONE),
@@ -1867,9 +1867,9 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_Z(SQ_SEL_1),
DST_SEL_W(SQ_SEL_0),
USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(16),
ENDIAN_SWAP(ENDIAN_NONE),
@@ -2117,9 +2117,9 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_Z(SQ_SEL_0),
DST_SEL_W(SQ_SEL_1),
USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
ENDIAN_SWAP(ENDIAN_NONE),
@@ -2142,9 +2142,9 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_SEL_Z(SQ_SEL_1),
DST_SEL_W(SQ_SEL_0),
USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(8),
ENDIAN_SWAP(ENDIAN_NONE),
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