xf86-video-intel: 5 commits - src/i830_3d.c src/i830_batchbuffer.c src/i830_batchbuffer.h src/i830_driver.c src/i830.h src/i830_render.c src/i915_3d.c src/i915_3d.h src/i915_render.c src/i915_video.c src/i965_render.c src/i965_video.c uxa/uxa-render.c
Chris Wilson
ickle at kemper.freedesktop.org
Tue Nov 10 07:35:07 PST 2009
src/i830.h | 5
src/i830_3d.c | 2
src/i830_batchbuffer.c | 2
src/i830_batchbuffer.h | 13 +
src/i830_driver.c | 6
src/i830_render.c | 6
src/i915_3d.c | 2
src/i915_3d.h | 13 -
src/i915_render.c | 409 ++++++++++++++++++++++++++++---------------------
src/i915_video.c | 10 -
src/i965_render.c | 14 -
src/i965_video.c | 10 -
uxa/uxa-render.c | 2
13 files changed, 294 insertions(+), 200 deletions(-)
New commits:
commit 14109abf285866ad4cd99d0cd16b0954a0a73a62
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Nov 10 11:17:23 2009 +0000
i915: Fix texture sampling coordinates.
RENDER specifies that texels should sampled from the pixel centre. This
corrects a number of failures in the cairo test suite and a few
off-by-one bug reports.
Grey border around images
https://bugs.freedesktop.org/show_bug.cgi?id=21523
Note that the earlier attempt to fix this was subverted by the buggy use
of 1x1R textures for solid sources -- which caused the majority of text
to disappear.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i915_render.c b/src/i915_render.c
index db0daf0..f64e031 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -135,6 +135,9 @@ static uint32_t i915_get_blend_cntl(int op, PicturePtr mask,
(dblend << S6_CBUF_DST_BLEND_FACT_SHIFT);
}
+#define DSTORG_HORT_BIAS(x) ((x)<<20)
+#define DSTORG_VERT_BIAS(x) ((x)<<16)
+
static Bool i915_get_dest_format(PicturePtr dest_picture, uint32_t * dst_format)
{
ScrnInfoPtr scrn;
@@ -165,6 +168,7 @@ static Bool i915_get_dest_format(PicturePtr dest_picture, uint32_t * dst_format)
(int)dest_picture->format);
return FALSE;
}
+ *dst_format |= DSTORG_HORT_BIAS(0x8) | DSTORG_VERT_BIAS(0x8);
return TRUE;
}
@@ -416,7 +420,7 @@ i915_prepare_composite(int op, PicturePtr source_picture,
}
if (source_picture->filter == PictFilterNearest)
- intel->dst_coord_adjust = -0.125;
+ intel->src_coord_adjust = 0.375;
}
if (mask != NULL) {
@@ -428,7 +432,7 @@ i915_prepare_composite(int op, PicturePtr source_picture,
}
if (mask_picture->filter == PictFilterNearest)
- intel->dst_coord_adjust = -0.125;
+ intel->mask_coord_adjust = 0.375;
}
}
commit e581ceb7381e29ecc1a172597d258824f6a1d2d3
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Nov 10 11:14:23 2009 +0000
i915: Use the color channels to pass along solid sources and masks.
Instead of allocating and utilising the texture samplers for 1x1R
solid sources and masks we can simply use the default diffuse and
specular colour channels and adjust the fragment shader appropriately.
The big advantage is the reduction in size of batches which should give
a good boost to glyph performance, irrespective of the additional boost
from using simpler shaders.
However, the motivating factor behind the switch is that our use of 1x1
textures turns out to be buggy...
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i830.h b/src/i830.h
index 7d6a9ff..bd62743 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -259,6 +259,10 @@ typedef struct intel_screen_private {
PixmapPtr render_source, render_mask, render_dest;
PicturePtr render_source_picture, render_mask_picture, render_dest_picture;
+ uint32_t render_source_solid;
+ uint32_t render_mask_solid;
+ Bool render_source_is_solid;
+ Bool render_mask_is_solid;
Bool needs_render_state_emit;
/* i830 render accel state */
@@ -266,6 +270,7 @@ typedef struct intel_screen_private {
uint32_t cblend, ablend, s8_blendctl;
/* i915 render accel state */
+ PixmapPtr texture[2];
uint32_t mapstate[6];
uint32_t samplerstate[6];
diff --git a/src/i915_render.c b/src/i915_render.c
index 65fea78..db0daf0 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -320,6 +320,7 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
}
/* offset filled in at emit time */
+ intel->texture[unit] = pixmap;
intel->mapstate[unit * 3 + 0] = 0;
intel->mapstate[unit * 3 + 1] = format |
MS3_USE_FENCE_REGS |
@@ -356,6 +357,7 @@ i915_prepare_composite(int op, PicturePtr source_picture,
mask ? i830_get_pixmap_bo(mask) : NULL,
i830_get_pixmap_bo(dest),
};
+ int tex_unit = 0;
intel->render_source_picture = source_picture;
intel->render_source = source;
@@ -364,12 +366,29 @@ i915_prepare_composite(int op, PicturePtr source_picture,
intel->render_dest_picture = dest_picture;
intel->render_dest = dest;
- if (!intel_check_pitch_3d(source))
+ intel->render_source_is_solid =
+ source_picture->pDrawable &&
+ source_picture->pDrawable->width == 1 &&
+ source_picture->pDrawable->height == 1 &&
+ source_picture->repeat;
+ if (intel->render_source_is_solid)
+ intel->render_source_solid = uxa_get_pixmap_first_pixel(source);
+ else if (!intel_check_pitch_3d(source))
return FALSE;
+
+ intel->render_mask_is_solid = TRUE; /* mask == NULL => opaque */
if (mask) {
- if (!intel_check_pitch_3d(mask))
- return FALSE;
+ intel->render_mask_is_solid =
+ mask_picture->pDrawable &&
+ mask_picture->pDrawable->width == 1 &&
+ mask_picture->pDrawable->height == 1 &&
+ mask_picture->repeat;
+ if (intel->render_mask_is_solid)
+ intel->render_mask_solid = uxa_get_pixmap_first_pixel(mask);
+ else if (!intel_check_pitch_3d(mask))
+ return FALSE;
}
+
if (!intel_check_pitch_3d(dest))
return FALSE;
@@ -379,30 +398,38 @@ i915_prepare_composite(int op, PicturePtr source_picture,
if (!i830_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table)))
return FALSE;
-
- if (!i915_texture_setup(source_picture, source, 0)) {
- intel_debug_fallback(scrn, "fail to setup src texture\n");
- return FALSE;
- }
-
intel->dst_coord_adjust = 0;
intel->src_coord_adjust = 0;
intel->mask_coord_adjust = 0;
- if (source_picture->filter == PictFilterNearest)
- intel->dst_coord_adjust = -0.125;
- if (mask != NULL) {
- if (!i915_texture_setup(mask_picture, mask, 1)) {
- intel_debug_fallback(scrn,
- "fail to setup mask texture\n");
+
+ intel->transform[0] = NULL;
+ intel->scale_units[0][0] = -1;
+ intel->scale_units[0][1] = -1;
+ intel->transform[1] = NULL;
+ intel->scale_units[1][0] = -1;
+ intel->scale_units[1][1] = -1;
+
+ if (! intel->render_source_is_solid) {
+ if (!i915_texture_setup(source_picture, source, tex_unit++)) {
+ intel_debug_fallback(scrn, "fail to setup src texture\n");
return FALSE;
}
- if (mask_picture->filter == PictFilterNearest)
+ if (source_picture->filter == PictFilterNearest)
intel->dst_coord_adjust = -0.125;
- } else {
- intel->transform[1] = NULL;
- intel->scale_units[1][0] = -1;
- intel->scale_units[1][1] = -1;
+ }
+
+ if (mask != NULL) {
+ if (! intel->render_mask_is_solid) {
+ if (!i915_texture_setup(mask_picture, mask, tex_unit++)) {
+ intel_debug_fallback(scrn,
+ "fail to setup mask texture\n");
+ return FALSE;
+ }
+
+ if (mask_picture->filter == PictFilterNearest)
+ intel->dst_coord_adjust = -0.125;
+ }
}
intel->i915_render_state.op = op;
@@ -418,14 +445,13 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
PicturePtr source_picture = intel->render_source_picture;
PicturePtr mask_picture = intel->render_mask_picture;
PicturePtr dest_picture = intel->render_dest_picture;
- PixmapPtr source = intel->render_source;
PixmapPtr mask = intel->render_mask;
PixmapPtr dest = intel->render_dest;
uint32_t dst_format = intel->i915_render_state.dst_format, dst_pitch;
uint32_t blendctl;
- int out_reg = FS_OC;
- FS_LOCALS(20);
Bool is_affine_src, is_affine_mask;
+ Bool is_solid_src, is_solid_mask;
+ int tex_count, t;
intel->needs_render_state_emit = FALSE;
@@ -437,71 +463,79 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
is_affine_src = i830_transform_is_affine(intel->transform[0]);
is_affine_mask = i830_transform_is_affine(intel->transform[1]);
- if (mask == NULL) {
- ATOMIC_BATCH(10);
- OUT_BATCH(_3DSTATE_MAP_STATE | 3);
- OUT_BATCH(0x00000001); /* map 0 */
- OUT_RELOC_PIXMAP(source, I915_GEM_DOMAIN_SAMPLER, 0, 0);
- OUT_BATCH(intel->mapstate[1]);
- OUT_BATCH(intel->mapstate[2]);
-
- OUT_BATCH(_3DSTATE_SAMPLER_STATE | 3);
- OUT_BATCH(0x00000001); /* sampler 0 */
- OUT_BATCH(intel->samplerstate[0]);
- OUT_BATCH(intel->samplerstate[1]);
- OUT_BATCH(intel->samplerstate[2]);
- ADVANCE_BATCH();
- } else {
- ATOMIC_BATCH(16);
- OUT_BATCH(_3DSTATE_MAP_STATE | 6);
- OUT_BATCH(0x00000003); /* map 0,1 */
- OUT_RELOC_PIXMAP(source, I915_GEM_DOMAIN_SAMPLER, 0, 0);
- OUT_BATCH(intel->mapstate[1]);
- OUT_BATCH(intel->mapstate[2]);
- OUT_RELOC_PIXMAP(mask, I915_GEM_DOMAIN_SAMPLER, 0, 0);
- OUT_BATCH(intel->mapstate[4]);
- OUT_BATCH(intel->mapstate[5]);
-
- OUT_BATCH(_3DSTATE_SAMPLER_STATE | 6);
- OUT_BATCH(0x00000003); /* sampler 0,1 */
- OUT_BATCH(intel->samplerstate[0]);
- OUT_BATCH(intel->samplerstate[1]);
- OUT_BATCH(intel->samplerstate[2]);
- OUT_BATCH(intel->samplerstate[3]);
- OUT_BATCH(intel->samplerstate[4]);
- OUT_BATCH(intel->samplerstate[5]);
- ADVANCE_BATCH();
+ is_solid_src = intel->render_source_is_solid;
+ is_solid_mask = intel->render_mask_is_solid;
+
+ tex_count = 0;
+ tex_count += ! is_solid_src;
+ tex_count += mask && ! is_solid_mask;
+
+ t = 16;
+ if (tex_count)
+ t += 6 * tex_count + 4;
+ if (is_solid_src)
+ t += 2;
+ if (mask && is_solid_mask)
+ t += 2;
+ ATOMIC_BATCH (t);
+
+ if (tex_count != 0) {
+ OUT_BATCH(_3DSTATE_MAP_STATE | (3 * tex_count));
+ OUT_BATCH((1 << tex_count) - 1);
+ for (t = 0; t < tex_count; t++) {
+ OUT_RELOC_PIXMAP(intel->texture[t], I915_GEM_DOMAIN_SAMPLER, 0, 0);
+ OUT_BATCH(intel->mapstate[3*t + 1]);
+ OUT_BATCH(intel->mapstate[3*t + 2]);
+ }
+
+ OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * tex_count));
+ OUT_BATCH((1 << tex_count) - 1);
+ for (t = 0; t < tex_count; t++) {
+ OUT_BATCH(intel->samplerstate[3*t + 0]);
+ OUT_BATCH(intel->samplerstate[3*t + 1]);
+ OUT_BATCH(intel->samplerstate[3*t + 2]);
+ }
}
- {
- uint32_t ss2;
- ATOMIC_BATCH(16);
- OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
- OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
- BUF_3D_PITCH(dst_pitch));
- OUT_RELOC_PIXMAP(dest, I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER, 0);
+ if (is_solid_src) {
+ OUT_BATCH (_3DSTATE_DFLT_DIFFUSE_CMD);
+ OUT_BATCH (intel->render_source_solid);
+ }
+ if (mask && is_solid_mask) {
+ OUT_BATCH (_3DSTATE_DFLT_SPEC_CMD);
+ OUT_BATCH (intel->render_mask_solid);
+ }
+
+ OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
+ OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
+ BUF_3D_PITCH(dst_pitch));
+ OUT_RELOC_PIXMAP(dest, I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER, 0);
+
+ OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
+ OUT_BATCH(dst_format);
- OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
- OUT_BATCH(dst_format);
+ {
+ uint32_t ss2;
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | 3);
- ss2 = S2_TEXCOORD_FMT(0,
- is_affine_src ? TEXCOORDFMT_2D :
- TEXCOORDFMT_4D);
- if (mask)
- ss2 |= S2_TEXCOORD_FMT(1,
- is_affine_mask ? TEXCOORDFMT_2D :
- TEXCOORDFMT_4D);
- else
- ss2 |= S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT);
- ss2 |= S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT);
- ss2 |= S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT);
- ss2 |= S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT);
- ss2 |= S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT);
- ss2 |= S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT);
- ss2 |= S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT);
+ ss2 = ~0;
+ t = 0;
+ if (! is_solid_src) {
+ ss2 &= ~S2_TEXCOORD_FMT(t, TEXCOORDFMT_NOT_PRESENT);
+ ss2 |= S2_TEXCOORD_FMT(t,
+ is_affine_src ? TEXCOORDFMT_2D :
+ TEXCOORDFMT_4D);
+ t++;
+ }
+ if (mask && ! is_solid_mask) {
+ ss2 &= ~S2_TEXCOORD_FMT(t, TEXCOORDFMT_NOT_PRESENT);
+ ss2 |= S2_TEXCOORD_FMT(t,
+ is_affine_mask ? TEXCOORDFMT_2D :
+ TEXCOORDFMT_4D);
+ t++;
+ }
OUT_BATCH(ss2);
OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) | S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE | S4_VFMT_XY);
@@ -520,51 +554,74 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
DRAW_XMAX(dest->drawable.width - 1));
/* yorig, xorig (relate to color buffer?) */
OUT_BATCH(0x00000000);
- OUT_BATCH(MI_NOOP);
- ADVANCE_BATCH();
}
- if (dst_format == COLR_BUF_8BIT)
- out_reg = FS_U0;
+ OUT_BATCH(MI_NOOP);
+ ADVANCE_BATCH();
- FS_BEGIN();
+ {
+ FS_LOCALS(20);
+ int src_reg, mask_reg, out_reg = FS_OC;
- /* Declare the registers necessary for our program. I don't think the
- * S then T ordering is necessary.
- */
- i915_fs_dcl(FS_S0);
- if (mask)
- i915_fs_dcl(FS_S1);
- i915_fs_dcl(FS_T0);
- if (mask)
- i915_fs_dcl(FS_T1);
+ FS_BEGIN();
- /* Load the source_picture texel */
- if (is_affine_src) {
- i915_fs_texld(FS_R0, FS_S0, FS_T0);
- } else {
- i915_fs_texldp(FS_R0, FS_S0, FS_T0);
- }
+ if (dst_format == COLR_BUF_8BIT)
+ out_reg = FS_U0;
- /* If the texture lacks an alpha channel, force the alpha to 1. */
- if (PICT_FORMAT_A(source_picture->format) == 0)
- i915_fs_mov_masked(FS_R0, MASK_W, i915_fs_operand_one());
+ /* Declare the registers necessary for our program. */
+ t = 0;
+ if (is_solid_src) {
+ i915_fs_dcl(FS_T8);
+ src_reg = FS_T8;
+ } else {
+ i915_fs_dcl(FS_T0);
+ i915_fs_dcl(FS_S0);
+ t++;
+ }
+ if (mask) {
+ if (is_solid_mask) {
+ i915_fs_dcl(FS_T9);
+ mask_reg = FS_T9;
+ } else {
+ i915_fs_dcl(FS_T0 + t);
+ i915_fs_dcl(FS_S0 + t);
+ }
+ }
- if (!mask) {
- /* No mask, so move to output color */
- i915_fs_mov(out_reg, i915_fs_operand_reg(FS_R0));
- } else {
- /* Load the mask_picture texel */
- if (is_affine_mask) {
- i915_fs_texld(FS_R1, FS_S1, FS_T1);
+ /* Load the source_picture texel */
+ if (! is_solid_src) {
+ if (is_affine_src) {
+ i915_fs_texld(FS_R0, FS_S0, FS_T0);
} else {
- i915_fs_texldp(FS_R1, FS_S1, FS_T1);
+ i915_fs_texldp(FS_R0, FS_S0, FS_T0);
}
- /* If the texture lacks an alpha channel, force the alpha to 1.
- */
- if (PICT_FORMAT_A(mask_picture->format) == 0)
+
+ /* If the texture lacks an alpha channel, force the alpha to 1. */
+ if (PICT_FORMAT_A(source_picture->format) == 0)
+ i915_fs_mov_masked(FS_R0, MASK_W, i915_fs_operand_one());
+
+ src_reg = FS_R0;
+ }
+
+ if (!mask) {
+ /* No mask, so move to output color */
+ i915_fs_mov(out_reg, i915_fs_operand_reg(src_reg));
+ } else {
+ if (! is_solid_mask) {
+ /* Load the mask_picture texel */
+ if (is_affine_mask) {
+ i915_fs_texld(FS_R1, FS_S0, FS_T0 + t);
+ } else {
+ i915_fs_texldp(FS_R1, FS_S0, FS_T0 + t);
+ }
+ /* If the texture lacks an alpha channel, force the alpha to 1.
+ */
+ if (PICT_FORMAT_A(mask_picture->format) == 0)
i915_fs_mov_masked(FS_R1, MASK_W,
- i915_fs_operand_one());
+ i915_fs_operand_one());
+
+ mask_reg = FS_R1;
+ }
/* If component alpha is active in the mask and the blend
* operation uses the source alpha, then we know we don't
@@ -577,24 +634,25 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
* source value (src.X * mask.A).
*/
if (mask_picture->componentAlpha &&
- PICT_FORMAT_RGB(mask_picture->format)) {
- if (i915_blend_op[op].src_alpha) {
- i915_fs_mul(out_reg,
- i915_fs_operand(FS_R0, W, W, W, W),
- i915_fs_operand_reg(FS_R1));
- } else {
- i915_fs_mul(out_reg, i915_fs_operand_reg(FS_R0),
- i915_fs_operand_reg(FS_R1));
- }
+ PICT_FORMAT_RGB(mask_picture->format)) {
+ if (i915_blend_op[op].src_alpha) {
+ i915_fs_mul(out_reg,
+ i915_fs_operand(src_reg, W, W, W, W),
+ i915_fs_operand_reg(mask_reg));
+ } else {
+ i915_fs_mul(out_reg, i915_fs_operand_reg(src_reg),
+ i915_fs_operand_reg(mask_reg));
+ }
} else {
- i915_fs_mul(out_reg, i915_fs_operand_reg(FS_R0),
- i915_fs_operand(FS_R1, W, W, W, W));
+ i915_fs_mul(out_reg, i915_fs_operand_reg(src_reg),
+ i915_fs_operand(mask_reg, W, W, W, W));
}
- }
- if (dst_format == COLR_BUF_8BIT)
+ }
+ if (dst_format == COLR_BUF_8BIT)
i915_fs_mov(FS_OC, i915_fs_operand(out_reg, W, W, W, W));
- FS_END();
+ FS_END();
+ }
}
/* Emit the vertices for a single composite rectangle.
@@ -611,33 +669,37 @@ i915_emit_composite_primitive(PixmapPtr dest,
intel_screen_private *intel = intel_get_screen_private(scrn);
Bool is_affine_src, is_affine_mask = TRUE;
int per_vertex, num_floats;
+ int tex_unit = 0;
+ int src_unit = -1, mask_unit = -1;
float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
per_vertex = 2; /* dest x/y */
- {
+ if (! intel->render_source_is_solid) {
float x = srcX + intel->src_coord_adjust;
float y = srcY + intel->src_coord_adjust;
- is_affine_src = i830_transform_is_affine(intel->transform[0]);
+ src_unit = tex_unit++;
+
+ is_affine_src = i830_transform_is_affine(intel->transform[src_unit]);
if (is_affine_src) {
if (!i830_get_transformed_coordinates(x, y,
intel->
- transform[0],
+ transform[src_unit],
&src_x[0],
&src_y[0]))
return;
if (!i830_get_transformed_coordinates(x, y + h,
intel->
- transform[0],
+ transform[src_unit],
&src_x[1],
&src_y[1]))
return;
if (!i830_get_transformed_coordinates(x + w, y + h,
intel->
- transform[0],
+ transform[src_unit],
&src_x[2],
&src_y[2]))
return;
@@ -646,7 +708,7 @@ i915_emit_composite_primitive(PixmapPtr dest,
} else {
if (!i830_get_transformed_coordinates_3d(x, y,
intel->
- transform[0],
+ transform[src_unit],
&src_x[0],
&src_y[0],
&src_w[0]))
@@ -654,7 +716,7 @@ i915_emit_composite_primitive(PixmapPtr dest,
if (!i830_get_transformed_coordinates_3d(x, y + h,
intel->
- transform[0],
+ transform[src_unit],
&src_x[1],
&src_y[1],
&src_w[1]))
@@ -662,7 +724,7 @@ i915_emit_composite_primitive(PixmapPtr dest,
if (!i830_get_transformed_coordinates_3d(x + w, y + h,
intel->
- transform[0],
+ transform[src_unit],
&src_x[2],
&src_y[2],
&src_w[2]))
@@ -672,29 +734,31 @@ i915_emit_composite_primitive(PixmapPtr dest,
}
}
- if (intel->render_mask) {
+ if (intel->render_mask && ! intel->render_mask_is_solid) {
float x = maskX + intel->mask_coord_adjust;
float y = maskY + intel->mask_coord_adjust;
- is_affine_mask = i830_transform_is_affine(intel->transform[1]);
+ mask_unit = tex_unit++;
+
+ is_affine_mask = i830_transform_is_affine(intel->transform[mask_unit]);
if (is_affine_mask) {
if (!i830_get_transformed_coordinates(x, y,
intel->
- transform[1],
+ transform[mask_unit],
&mask_x[0],
&mask_y[0]))
return;
if (!i830_get_transformed_coordinates(x, y + h,
intel->
- transform[1],
+ transform[mask_unit],
&mask_x[1],
&mask_y[1]))
return;
if (!i830_get_transformed_coordinates(x + w, y + h,
intel->
- transform[1],
+ transform[mask_unit],
&mask_x[2],
&mask_y[2]))
return;
@@ -703,7 +767,7 @@ i915_emit_composite_primitive(PixmapPtr dest,
} else {
if (!i830_get_transformed_coordinates_3d(x, y,
intel->
- transform[1],
+ transform[mask_unit],
&mask_x[0],
&mask_y[0],
&mask_w[0]))
@@ -711,7 +775,7 @@ i915_emit_composite_primitive(PixmapPtr dest,
if (!i830_get_transformed_coordinates_3d(x, y + h,
intel->
- transform[1],
+ transform[mask_unit],
&mask_x[1],
&mask_y[1],
&mask_w[1]))
@@ -719,7 +783,7 @@ i915_emit_composite_primitive(PixmapPtr dest,
if (!i830_get_transformed_coordinates_3d(x + w, y + h,
intel->
- transform[1],
+ transform[mask_unit],
&mask_x[2],
&mask_y[2],
&mask_w[2]))
@@ -736,15 +800,17 @@ i915_emit_composite_primitive(PixmapPtr dest,
OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (num_floats - 1));
OUT_BATCH_F(intel->dst_coord_adjust + dstX + w);
OUT_BATCH_F(intel->dst_coord_adjust + dstY + h);
- OUT_BATCH_F(src_x[2] / intel->scale_units[0][0]);
- OUT_BATCH_F(src_y[2] / intel->scale_units[0][1]);
- if (!is_affine_src) {
+ if (! intel->render_source_is_solid) {
+ OUT_BATCH_F(src_x[2] / intel->scale_units[src_unit][0]);
+ OUT_BATCH_F(src_y[2] / intel->scale_units[src_unit][1]);
+ if (!is_affine_src) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(src_w[2]);
+ }
}
- if (intel->render_mask) {
- OUT_BATCH_F(mask_x[2] / intel->scale_units[1][0]);
- OUT_BATCH_F(mask_y[2] / intel->scale_units[1][1]);
+ if (intel->render_mask && ! intel->render_mask_is_solid) {
+ OUT_BATCH_F(mask_x[2] / intel->scale_units[mask_unit][0]);
+ OUT_BATCH_F(mask_y[2] / intel->scale_units[mask_unit][1]);
if (!is_affine_mask) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(mask_w[2]);
@@ -753,15 +819,17 @@ i915_emit_composite_primitive(PixmapPtr dest,
OUT_BATCH_F(intel->dst_coord_adjust + dstX);
OUT_BATCH_F(intel->dst_coord_adjust + dstY + h);
- OUT_BATCH_F(src_x[1] / intel->scale_units[0][0]);
- OUT_BATCH_F(src_y[1] / intel->scale_units[0][1]);
- if (!is_affine_src) {
+ if (! intel->render_source_is_solid) {
+ OUT_BATCH_F(src_x[1] / intel->scale_units[src_unit][0]);
+ OUT_BATCH_F(src_y[1] / intel->scale_units[src_unit][1]);
+ if (!is_affine_src) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(src_w[1]);
+ }
}
- if (intel->render_mask) {
- OUT_BATCH_F(mask_x[1] / intel->scale_units[1][0]);
- OUT_BATCH_F(mask_y[1] / intel->scale_units[1][1]);
+ if (intel->render_mask && ! intel->render_mask_is_solid) {
+ OUT_BATCH_F(mask_x[1] / intel->scale_units[mask_unit][0]);
+ OUT_BATCH_F(mask_y[1] / intel->scale_units[mask_unit][1]);
if (!is_affine_mask) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(mask_w[1]);
@@ -770,15 +838,17 @@ i915_emit_composite_primitive(PixmapPtr dest,
OUT_BATCH_F(intel->dst_coord_adjust + dstX);
OUT_BATCH_F(intel->dst_coord_adjust + dstY);
- OUT_BATCH_F(src_x[0] / intel->scale_units[0][0]);
- OUT_BATCH_F(src_y[0] / intel->scale_units[0][1]);
- if (!is_affine_src) {
+ if (! intel->render_source_is_solid) {
+ OUT_BATCH_F(src_x[0] / intel->scale_units[src_unit][0]);
+ OUT_BATCH_F(src_y[0] / intel->scale_units[src_unit][1]);
+ if (!is_affine_src) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(src_w[0]);
+ }
}
- if (intel->render_mask) {
- OUT_BATCH_F(mask_x[0] / intel->scale_units[1][0]);
- OUT_BATCH_F(mask_y[0] / intel->scale_units[1][1]);
+ if (intel->render_mask && ! intel->render_mask_is_solid) {
+ OUT_BATCH_F(mask_x[0] / intel->scale_units[mask_unit][0]);
+ OUT_BATCH_F(mask_y[0] / intel->scale_units[mask_unit][1]);
if (!is_affine_mask) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(mask_w[0]);
@@ -795,6 +865,7 @@ i915_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum];
intel_screen_private *intel = intel_get_screen_private(scrn);
+ /* 28 + 16 + 10 + 20 + 32 + 16 */
intel_batch_start_atomic(scrn, 150);
if (intel->needs_render_state_emit)
commit 33cabbfca6acb5149e26f87a538a7cb79f00cad2
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Nov 10 11:09:52 2009 +0000
i915: Check for overflow before overflowing.
As the immediate victim of the overflow would be to overwrite the maximum
permissible value, the test was optimistic.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i915_3d.h b/src/i915_3d.h
index 500817f..f85780a 100644
--- a/src/i915_3d.h
+++ b/src/i915_3d.h
@@ -420,8 +420,8 @@ do { \
*/
#define FS_LOCALS(x) \
uint32_t _shader_buf[(x) * 3]; \
- int _max_shader_commands = x; \
- int _cur_shader_commands
+ unsigned int _max_shader_commands = x; \
+ unsigned int _cur_shader_commands
#define FS_BEGIN() \
do { \
@@ -430,12 +430,13 @@ do { \
#define FS_OUT(_shaderop) \
do { \
+ if (_cur_shader_commands >= _max_shader_commands) \
+ FatalError("fragment shader command buffer exceeded (%d)\n", \
+ _cur_shader_commands); \
_shader_buf[_cur_shader_commands * 3 + 0] = _shaderop.ui[0]; \
_shader_buf[_cur_shader_commands * 3 + 1] = _shaderop.ui[1]; \
_shader_buf[_cur_shader_commands * 3 + 2] = _shaderop.ui[2]; \
- if (++_cur_shader_commands > _max_shader_commands) \
- FatalError("fragment shader command buffer exceeded (%d)\n", \
- _cur_shader_commands); \
+ ++_cur_shader_commands; \
} while (0)
#define FS_END() \
commit 67af5a99253b1295f8dc09b28863eb7dc8b59e1d
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Nov 10 11:05:20 2009 +0000
Check that batch buffers are atomic.
Since batch buffers are rarely emitted by themselves but as part of a
sequence of state and vertices, the whole sequence is emitted atomically.
Here we just enforce that batches are marked as being part of an atomic
sequence as appropriate.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i830_3d.c b/src/i830_3d.c
index c95a0b1..e83cb3f 100644
--- a/src/i830_3d.c
+++ b/src/i830_3d.c
@@ -38,7 +38,7 @@ void I830EmitInvarientState(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
- BEGIN_BATCH(58);
+ ATOMIC_BATCH(58);
OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
diff --git a/src/i830_batchbuffer.c b/src/i830_batchbuffer.c
index 62466b7..e5ddb47 100644
--- a/src/i830_batchbuffer.c
+++ b/src/i830_batchbuffer.c
@@ -95,6 +95,8 @@ void intel_batch_flush(ScrnInfoPtr scrn, Bool flushed)
intel_screen_private *intel = intel_get_screen_private(scrn);
int ret;
+ assert (!intel->in_batch_atomic);
+
if (intel->batch_used == 0)
return;
diff --git a/src/i830_batchbuffer.h b/src/i830_batchbuffer.h
index 274e82f..a7dd289 100644
--- a/src/i830_batchbuffer.h
+++ b/src/i830_batchbuffer.h
@@ -127,11 +127,24 @@ do { \
if (intel->batch_emitting != 0) \
FatalError("%s: BEGIN_BATCH called without closing " \
"ADVANCE_BATCH\n", __FUNCTION__); \
+ assert(!intel->in_batch_atomic); \
intel_batch_require_space(scrn, intel, (n) * 4); \
intel->batch_emitting = (n) * 4; \
intel->batch_emit_start = intel->batch_used; \
} while (0)
+/* special-case variant for when we have preallocated space */
+#define ATOMIC_BATCH(n) \
+do { \
+ if (intel->batch_emitting != 0) \
+ FatalError("%s: ATOMIC_BATCH called without closing " \
+ "ADVANCE_BATCH\n", __FUNCTION__); \
+ assert(intel->in_batch_atomic); \
+ assert(intel->batch_used + (n) * 4 <= intel->batch_atomic_limit); \
+ intel->batch_emitting = (n) * 4; \
+ intel->batch_emit_start = intel->batch_used; \
+} while (0)
+
#define ADVANCE_BATCH() do { \
if (intel->batch_emitting == 0) \
FatalError("%s: ADVANCE_BATCH called with no matching " \
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 867047c..445ab37 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1399,9 +1399,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv)
if (intel->XvEnabled)
I830InitVideo(screen);
- /* Setup 3D engine, needed for rotation too */
- IntelEmitInvarientState(scrn);
-
#if defined(DRI2)
switch (intel->directRenderingType) {
case DRI_DRI2:
@@ -1513,9 +1510,8 @@ static Bool I830EnterVT(int scrnIndex, int flags)
if (!xf86SetDesiredModes(scrn))
return FALSE;
- /* Mark 3D state as being clobbered and setup the basics */
+ /* Mark all state as being clobbered. */
intel->last_3d = LAST_3D_OTHER;
- IntelEmitInvarientState(scrn);
return TRUE;
}
diff --git a/src/i830_render.c b/src/i830_render.c
index 24d644b..ee89950 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -339,7 +339,7 @@ static void i830_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
else
format |= MAPSURF_32BIT;
- BEGIN_BATCH(10);
+ ATOMIC_BATCH(10);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
LOAD_TEXTURE_MAP(unit) | 4);
OUT_RELOC_PIXMAP(pixmap, I915_GEM_DOMAIN_SAMPLER, 0,
@@ -569,7 +569,7 @@ static void i830_emit_composite_state(ScrnInfoPtr scrn)
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_RENDER;
- BEGIN_BATCH(21);
+ ATOMIC_BATCH(21);
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
@@ -770,7 +770,7 @@ i830_emit_composite_primitive(PixmapPtr dest,
num_floats = 3 * per_vertex;
- BEGIN_BATCH(1 + num_floats);
+ ATOMIC_BATCH(1 + num_floats);
OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (num_floats - 1));
OUT_BATCH_F(intel->dst_coord_adjust + dstX + w);
diff --git a/src/i915_3d.c b/src/i915_3d.c
index e3b5674..517c685 100644
--- a/src/i915_3d.c
+++ b/src/i915_3d.c
@@ -38,7 +38,7 @@ void I915EmitInvarientState(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
- BEGIN_BATCH(24);
+ ATOMIC_BATCH(24);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
diff --git a/src/i915_3d.h b/src/i915_3d.h
index 117712e..500817f 100644
--- a/src/i915_3d.h
+++ b/src/i915_3d.h
@@ -441,7 +441,7 @@ do { \
#define FS_END() \
do { \
int _i, _pad = (_cur_shader_commands & 0x1) ? 0 : 1; \
- BEGIN_BATCH(_cur_shader_commands * 3 + 1 + _pad); \
+ ATOMIC_BATCH(_cur_shader_commands * 3 + 1 + _pad); \
OUT_BATCH(_3DSTATE_PIXEL_SHADER_PROGRAM | \
(_cur_shader_commands * 3 - 1)); \
for (_i = 0; _i < _cur_shader_commands * 3; _i++) \
diff --git a/src/i915_render.c b/src/i915_render.c
index 6a936be..65fea78 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -438,7 +438,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
is_affine_mask = i830_transform_is_affine(intel->transform[1]);
if (mask == NULL) {
- BEGIN_BATCH(10);
+ ATOMIC_BATCH(10);
OUT_BATCH(_3DSTATE_MAP_STATE | 3);
OUT_BATCH(0x00000001); /* map 0 */
OUT_RELOC_PIXMAP(source, I915_GEM_DOMAIN_SAMPLER, 0, 0);
@@ -452,7 +452,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
OUT_BATCH(intel->samplerstate[2]);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(16);
+ ATOMIC_BATCH(16);
OUT_BATCH(_3DSTATE_MAP_STATE | 6);
OUT_BATCH(0x00000003); /* map 0,1 */
OUT_RELOC_PIXMAP(source, I915_GEM_DOMAIN_SAMPLER, 0, 0);
@@ -475,7 +475,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
{
uint32_t ss2;
- BEGIN_BATCH(16);
+ ATOMIC_BATCH(16);
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
BUF_3D_PITCH(dst_pitch));
@@ -731,7 +731,7 @@ i915_emit_composite_primitive(PixmapPtr dest,
num_floats = 3 * per_vertex;
- BEGIN_BATCH(1 + num_floats);
+ ATOMIC_BATCH(1 + num_floats);
OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (num_floats - 1));
OUT_BATCH_F(intel->dst_coord_adjust + dstX + w);
diff --git a/src/i915_video.c b/src/i915_video.c
index e54bd9b..4e4ec03 100644
--- a/src/i915_video.c
+++ b/src/i915_video.c
@@ -75,7 +75,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_VIDEO;
- BEGIN_BATCH(20);
+ ATOMIC_BATCH(20);
/* flush map & render cache */
OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE |
@@ -139,7 +139,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
if (!is_planar_fourcc(id)) {
FS_LOCALS(10);
- BEGIN_BATCH(16);
+ ATOMIC_BATCH(16);
OUT_BATCH(_3DSTATE_PIXEL_SHADER_CONSTANTS | 4);
OUT_BATCH(0x0000001); /* constant 0 */
/* constant 0: brightness/contrast */
@@ -200,7 +200,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
} else {
FS_LOCALS(16);
- BEGIN_BATCH(22 + 11 + 11);
+ ATOMIC_BATCH(22 + 11 + 11);
/* For the planar formats, we set up three samplers --
* one for each plane, in a Y8 format. Because I
* couldn't get the special PLANAR_TO_PACKED
@@ -390,7 +390,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
}
{
- BEGIN_BATCH(2);
+ ATOMIC_BATCH(2);
OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE |
MI_INVALIDATE_MAP_CACHE);
OUT_BATCH(0x00000000);
@@ -423,7 +423,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
src_scale_x = ((float)src_w / width) / drw_w;
src_scale_y = ((float)src_h / height) / drw_h;
- BEGIN_BATCH(8 + 12);
+ ATOMIC_BATCH(8 + 12);
OUT_BATCH(MI_NOOP);
OUT_BATCH(MI_NOOP);
OUT_BATCH(MI_NOOP);
diff --git a/src/i965_render.c b/src/i965_render.c
index 09a71bf..236ce49 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1158,7 +1158,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
* rendering pipe
*/
{
- BEGIN_BATCH(2);
+ ATOMIC_BATCH(2);
OUT_BATCH(MI_FLUSH |
MI_STATE_INSTRUCTION_CACHE_FLUSH |
BRW_MI_GLOBAL_SNAPSHOT_RESET);
@@ -1167,9 +1167,9 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
}
{
if (IS_IGDNG(intel))
- BEGIN_BATCH(14);
+ ATOMIC_BATCH(14);
else
- BEGIN_BATCH(12);
+ ATOMIC_BATCH(12);
/* Match Mesa driver setup */
if (IS_G4X(intel) || IS_IGDNG(intel))
@@ -1215,7 +1215,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
}
{
int pipe_ctrl;
- BEGIN_BATCH(26);
+ ATOMIC_BATCH(26);
/* Pipe control */
if (IS_IGDNG(intel))
@@ -1328,7 +1328,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
}
if (IS_IGDNG(intel)) {
- BEGIN_BATCH(mask ? 9 : 7);
+ ATOMIC_BATCH(mask ? 9 : 7);
/*
* The reason to add this extra vertex element in the header is that
* IGDNG has different vertex header definition and origin method to
@@ -1358,7 +1358,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
(BRW_VFCOMPONENT_STORE_0 <<
VE1_VFCOMPONENT_3_SHIFT));
} else {
- BEGIN_BATCH(mask ? 7 : 5);
+ ATOMIC_BATCH(mask ? 7 : 5);
/* Set up our vertex elements, sourced from the single vertex buffer.
* that will be set up later.
*/
@@ -1804,7 +1804,7 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
if (intel->needs_render_state_emit)
i965_emit_composite_state(scrn);
- BEGIN_BATCH(12);
+ ATOMIC_BATCH(12);
OUT_BATCH(MI_FLUSH);
/* Set up the pointer to our (single) vertex buffer */
OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3);
diff --git a/src/i965_video.c b/src/i965_video.c
index 89d5eef..6225aa4 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -779,7 +779,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
urb_cs_start = urb_sf_start + urb_sf_size;
urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
- BEGIN_BATCH(2);
+ ATOMIC_BATCH(2);
OUT_BATCH(MI_FLUSH |
MI_STATE_INSTRUCTION_CACHE_FLUSH |
BRW_MI_GLOBAL_SNAPSHOT_RESET);
@@ -788,9 +788,9 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
/* brw_debug (scrn, "before base address modify"); */
if (IS_IGDNG(intel))
- BEGIN_BATCH(14);
+ ATOMIC_BATCH(14);
else
- BEGIN_BATCH(12);
+ ATOMIC_BATCH(12);
/* Match Mesa driver setup */
if (IS_G4X(intel) || IS_IGDNG(intel))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
@@ -844,7 +844,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
else
pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
- BEGIN_BATCH(38);
+ ATOMIC_BATCH(38);
OUT_BATCH(MI_NOOP);
@@ -1220,7 +1220,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
i965_emit_video_setup(scrn, bind_bo, n_src_surf);
- BEGIN_BATCH(12);
+ ATOMIC_BATCH(12);
/* Set up the pointer to our vertex buffer */
OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3);
/* four 32-bit floats per vertex */
commit 998d6b3d8c549086fbc8a9f0e309694b23398d8d
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Nov 10 11:00:43 2009 +0000
uxa: Force alpha bits to fill remaining bits
In the case of x8r8g8b8 and similar where the alpha channel is ignored,
but should be interpreted as being 1, then it is convenient if those bits
are set appropriately in the colour. In order to do so for these formats,
where PIXMAN_FORMAT_A() returns 0 we need to compute the alpha channel
width as the remaining bits instead.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/uxa/uxa-render.c b/uxa/uxa-render.c
index 7c0dbe5..ee1e4e1 100644
--- a/uxa/uxa-render.c
+++ b/uxa/uxa-render.c
@@ -147,6 +147,8 @@ uxa_get_pixel_from_rgba(CARD32 * pixel,
gbits = PICT_FORMAT_G(format);
bbits = PICT_FORMAT_B(format);
abits = PICT_FORMAT_A(format);
+ if (abits == 0)
+ abits = PICT_FORMAT_BPP(format) - (rbits+gbits+bbits);
if (PICT_FORMAT_TYPE(format) == PICT_TYPE_ARGB) {
bshift = 0;
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