xf86-video-intel: 2 commits - src/i810_reg.h src/i830_debug.c src/i830_driver.c

[Eric Anholt]

 src/i810_reg.h    |   42 ++++++++++++++++++++++++++++++++++++++++++
 src/i830_debug.c  |    8 ++++++++
 src/i830_driver.c |    8 ++++++++
 3 files changed, 58 insertions(+)

New commits:
commit 52367847087206b92f18c40d356d36ab9ee89d39
Author: Keith Packard <keithp at keithp.com>
Date:   Thu May 7 14:58:02 2009 -0700

    Load i915 and fbcon when checking for KMS
    
    Signed-off-by: Keith Packard <keithp at keithp.com>
    Signed-off-by: Eric Anholt <eric at anholt.net>

diff --git a/src/i830_driver.c b/src/i830_driver.c
index 0f66d63..aaf5a20 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1009,6 +1009,14 @@ static Bool i830_kernel_mode_enabled(ScrnInfoPtr pScrn)
     busIdString = DRICreatePCIBusID(PciInfo);
 
     ret = drmCheckModesettingSupported(busIdString);
+    if (ret)
+	if (xf86LoadKernelModule("i915")) {
+	    ret = drmCheckModesettingSupported(busIdString);
+
+	    /* Be nice to the user and load fbcon too */
+	    if (!ret)
+		(void) xf86LoadKernelModule("fbcon");
+	}
     xfree(busIdString);
     if (ret)
 	return FALSE;
commit ff7494b4c4b1bd8bb6f169402a9edbe9780787bb
Author: Keith Packard <keithp at keithp.com>
Date:   Thu May 7 14:58:01 2009 -0700

    Add DP link and GMCH M and N registers
    
    Signed-off-by: Eric Anholt <eric at anholt.net>

diff --git a/src/i810_reg.h b/src/i810_reg.h
index 8d4e641..cb33784 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -2214,6 +2214,43 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define PIPE_PIXEL_MASK		0x00ffffff
 #define PIPE_PIXEL_SHIFT	0
 
+/*
+ * Computing GMCH M and N values.
+ *
+ * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
+ *
+ * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
+ *
+ * The GMCH value is used internally
+ */
+#define PIPEA_GMCH_DATA_M	0x70050
+
+/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
+#define PIPE_GMCH_DATA_M_TU_SIZE_MASK	(0x3f << 25)
+#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT	25
+
+#define PIPE_GMCH_DATA_M_MASK		(0xffffff)
+
+#define PIPEA_GMCH_DATA_N	0x70054
+#define PIPE_GMCH_DATA_N_MASK		(0xffffff)
+
+/*
+ * Computing Link M and N values.
+ *
+ * Link M / N = pixel_clock / ls_clk
+ *
+ * (the DP spec calls pixel_clock the 'strm_clk')
+ *
+ * The Link value is transmitted in the Main Stream
+ * Attributes and VB-ID.
+ */
+
+#define PIPEA_DP_LINK_M		0x70060
+#define PIPEA_DP_LINK_M_MASK	(0xffffff)
+
+#define PIPEA_DP_LINK_N		0x70064
+#define PIPEA_DP_LINK_N_MASK	(0xffffff)
+
 #define PIPEB_DSL		0x71000
 
 #define PIPEBCONF 0x71008
@@ -2231,6 +2268,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define PIPEBFRAMEHIGH		0x71040
 #define PIPEBFRAMEPIXEL		0x71044
 
+#define PIPEB_GMCH_DATA_M	0x71050
+#define PIPEB_GMCH_DATA_N	0x71054
+#define PIPEB_DP_LINK_M		0x71060
+#define PIPEB_DP_LINK_N		0x71064
+
 #define DSPACNTR		0x70180
 #define DSPBCNTR		0x71180
 #define DISPLAY_PLANE_ENABLE 			(1<<31)
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 86f5f21..5a8c3eb 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -652,6 +652,10 @@ static struct i830SnapshotRec {
     DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
     DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
     DEFINEREG2(PIPEASTAT, i830_debug_pipestat),
+    DEFINEREG(PIPEA_GMCH_DATA_M),
+    DEFINEREG(PIPEA_GMCH_DATA_N),
+    DEFINEREG(PIPEA_DP_LINK_M),
+    DEFINEREG(PIPEA_DP_LINK_N),
 
     DEFINEREG2(FPA0, i830_debug_fp),
     DEFINEREG2(FPA1, i830_debug_fp),
@@ -676,6 +680,10 @@ static struct i830SnapshotRec {
     DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
     DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
     DEFINEREG2(PIPEBSTAT, i830_debug_pipestat),
+    DEFINEREG(PIPEB_GMCH_DATA_M),
+    DEFINEREG(PIPEB_GMCH_DATA_N),
+    DEFINEREG(PIPEB_DP_LINK_M),
+    DEFINEREG(PIPEB_DP_LINK_N),
 
     DEFINEREG2(FPB0, i830_debug_fp),
     DEFINEREG2(FPB1, i830_debug_fp),