xf86-video-intel: Branch '2.7' - 5 commits - man/intel.man src/drmmode_display.c src/i830_bios.c src/i830_display.c src/i830_display.h src/i830_driver.c src/i830_memory.c uxa/uxa-glyphs.c
Carl Worth
cworth at kemper.freedesktop.org
Thu Mar 19 10:43:53 PDT 2009
man/intel.man | 9 -
src/drmmode_display.c | 13 ++
src/i830_bios.c | 2
src/i830_display.c | 226 ++++++++++++++++++++++++++++----------------------
src/i830_display.h | 2
src/i830_driver.c | 31 ++++--
src/i830_memory.c | 5 -
uxa/uxa-glyphs.c | 36 ++-----
8 files changed, 176 insertions(+), 148 deletions(-)
New commits:
commit 1883d912c75238e73b3662580e08d3455d2efb33
Author: Kristian Høgsberg <krh at redhat.com>
Date: Wed Mar 11 11:10:57 2009 -0400
Drop Legacy3D option, only use fixed texture space with non-gem.
With this change, we always expect the 3D driver to use GEM textures
when the 2D driver uses GEM. When GEM is not available or disabled,
we fall back to legacy fixed textures.
(cherry picked from commit 73db44e7ac524e84e5f0fda2d60069a9e954ad1b)
diff --git a/man/intel.man b/man/intel.man
index e6cb03e..ffe69a1 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -146,15 +146,6 @@ have options for selecting adaptors.
.IP
Default: Textured video adaptor is preferred.
.TP
-.BI "Option \*qLegacy3D\*q \*q" boolean \*q
-Enable support for the non-GEM mode of the 3D driver on i830 and newer.
-This will allocate a large static area for older Mesa to use for its texture
-pool. On systems with a working GEM environment, this can be disabled to
-increase the memory pool available to other graphics tasks.
-.IP
-Default for i830 and newer: Enabled.
-.IP
-Default for i810: this option is not used.
.BI "Option \*qAccelMethod\*q \*q" string \*q
Choose acceleration architecture, either "XAA", "EXA", or "UXA". XAA is the old
XFree86 based acceleration architecture. EXA is a simpler
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 3977b28..7502d30 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -311,7 +311,6 @@ typedef enum {
OPTION_LVDS24BITMODE,
OPTION_FBC,
OPTION_TILING,
- OPTION_LEGACY3D,
OPTION_LVDSFIXEDMODE,
OPTION_FORCEENABLEPIPEA,
#ifdef INTEL_XVMC
@@ -332,9 +331,6 @@ static OptionInfoRec I830Options[] = {
{OPTION_LVDS24BITMODE, "LVDS24Bit", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_FBC, "FramebufferCompression", OPTV_BOOLEAN, {0}, TRUE},
{OPTION_TILING, "Tiling", OPTV_BOOLEAN, {0}, TRUE},
-#ifdef XF86DRI
- {OPTION_LEGACY3D, "Legacy3D", OPTV_BOOLEAN, {0}, FALSE},
-#endif
{OPTION_LVDSFIXEDMODE, "LVDSFixedMode", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_FORCEENABLEPIPEA, "ForceEnablePipeA", OPTV_BOOLEAN, {0}, FALSE},
#ifdef INTEL_XVMC
@@ -3015,11 +3011,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
*/
if (!pI830->can_resize && pI830->directRenderingType == DRI_NONE && I830DRIScreenInit(pScreen))
pI830->directRenderingType = DRI_XF86DRI;
-
- if (pI830->directRenderingType == DRI_XF86DRI) {
- pI830->allocate_classic_textures =
- xf86ReturnOptValBool(pI830->Options, OPTION_LEGACY3D, TRUE);
- }
#endif
/* Enable tiling by default */
diff --git a/src/i830_memory.c b/src/i830_memory.c
index e98c914..96e1763 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -504,9 +504,6 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
mmsize -= ROUND_TO_PAGE(3 * pScrn->displayWidth * pI830->cpp *
pScrn->virtualY);
}
- /* Classic textures are fixed. */
- if (pI830->allocate_classic_textures)
- mmsize -= MB(32);
/* Overlay and cursors, if physical, need to be allocated outside
* of the kernel memory manager.
*/
@@ -566,6 +563,8 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
i830_free_memory(pScrn, pI830->memory_manager);
pI830->memory_manager = NULL;
}
+ } else {
+ pI830->allocate_classic_textures = TRUE;
}
#endif /* XF86DRI */
commit db3675ceaf96342b339026022b1f2c13b5086ad4
Author: Ma Ling <ling.ma at intel.com>
Date: Thu Mar 19 09:10:19 2009 -0700
Set SSC frequency for 8xx chips correctly
All 8xx class chips have the 66/48 split, not just 855.
Fixes #18358.
(cherry picked from commit 85e6b528582c2397ee9eb2132cd0d05ce12eb43d)
diff --git a/src/i830_bios.c b/src/i830_bios.c
index 7f20553..9b13bf4 100644
--- a/src/i830_bios.c
+++ b/src/i830_bios.c
@@ -161,7 +161,7 @@ parse_general_features(I830Ptr pI830, struct bdb_header *bdb)
pI830->tv_present = general->int_tv_support;
pI830->lvds_use_ssc = general->enable_ssc;
if (pI830->lvds_use_ssc) {
- if (IS_I855(pI830))
+ if (IS_I85X(pI830))
pI830->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
else
pI830->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
commit e03403e55ffb11302ffd354e7a5fb1704eb9edbd
Author: Jesse Barnes <jbarnes at nietzche.localdomain>
Date: Wed Mar 18 20:19:44 2009 -0700
Re-enable disabled outputs after rotation
The server may have made a DPMS call before doing rotation, so after we
do the mode set with the rotated framebuffer, we need to re-enable the
corresponding output(s).
Fixes bug #20573.
(cherry picked from commit bedc894a565ce3c7a50990e3f78953fc2432ad40)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 141c027..e485256 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -60,6 +60,9 @@ typedef struct {
} drmmode_output_private_rec, *drmmode_output_private_ptr;
static void
+drmmode_output_dpms(xf86OutputPtr output, int mode);
+
+static void
drmmode_ConvertFromKMode(ScrnInfoPtr scrn,
drmModeModeInfoPtr kmode,
DisplayModePtr mode)
@@ -210,6 +213,16 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
else
ret = TRUE;
+ /* Turn on any outputs on this crtc that may have been disabled */
+ for (i = 0; i < xf86_config->num_output; i++) {
+ xf86OutputPtr output = xf86_config->output[i];
+
+ if (output->crtc != crtc)
+ continue;
+
+ drmmode_output_dpms(output, DPMSModeOn);
+ }
+
done:
if (!ret) {
crtc->x = saved_x;
commit f76a16d5b1d47430d60d1aa6c5f034c46a8be228
Author: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Wed Mar 18 09:36:58 2009 -0700
Create known output configuration at EnterVT time
Since we added the pipe A force quirk (leaving pipe A on all the time),
DPMS calls to disable it have silently returned, leaving the pipe on.
If another driver (like vesafb) has enabled it, we may end up with a bad
configuration, leading to hangs or blank screens at VT switch time.
Fixes bug #19603.
(cherry picked from commit 6deb26ae7bd796e88a5dd90df5f6c35fbc44e798)
diff --git a/src/i830_display.c b/src/i830_display.c
index ca55906..21883c4 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -873,14 +873,8 @@ i830_disable_vga_plane (xf86CrtcPtr crtc)
}
-/**
- * Sets the power management mode of the pipe and plane.
- *
- * This code should probably grow support for turning the cursor off and back
- * on appropriately at the same time as we're turning the pipe off/on.
- */
-static void
-i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
+void
+i830_crtc_enable(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
@@ -893,112 +887,148 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
int dspbase_reg = (plane == 0) ? DSPABASE : DSPBBASE;
uint32_t temp;
- /* XXX: When our outputs are all unaware of DPMS modes other than off and
- * on, we should map those modes to DPMSModeOff in the CRTC.
- */
- switch (mode) {
- case DPMSModeOn:
- case DPMSModeStandby:
- case DPMSModeSuspend:
- /* Enable the DPLL */
- temp = INREG(dpll_reg);
- if ((temp & DPLL_VCO_ENABLE) == 0)
- {
- OUTREG(dpll_reg, temp);
- POSTING_READ(dpll_reg);
- /* Wait for the clocks to stabilize. */
- usleep(150);
- OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
- POSTING_READ(dpll_reg);
- /* Wait for the clocks to stabilize. */
- usleep(150);
- OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
- POSTING_READ(dpll_reg);
- /* Wait for the clocks to stabilize. */
- usleep(150);
- }
+ /* Enable the DPLL */
+ temp = INREG(dpll_reg);
+ if ((temp & DPLL_VCO_ENABLE) == 0)
+ {
+ OUTREG(dpll_reg, temp);
+ POSTING_READ(dpll_reg);
+ /* Wait for the clocks to stabilize. */
+ usleep(150);
+ OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
+ POSTING_READ(dpll_reg);
+ /* Wait for the clocks to stabilize. */
+ usleep(150);
+ OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
+ POSTING_READ(dpll_reg);
+ /* Wait for the clocks to stabilize. */
+ usleep(150);
+ }
- /* Enable the pipe */
- temp = INREG(pipeconf_reg);
- if ((temp & PIPEACONF_ENABLE) == 0)
- OUTREG(pipeconf_reg, temp | PIPEACONF_ENABLE);
+ /* Enable the pipe */
+ temp = INREG(pipeconf_reg);
+ if ((temp & PIPEACONF_ENABLE) == 0)
+ OUTREG(pipeconf_reg, temp | PIPEACONF_ENABLE);
- /* Enable the plane */
- temp = INREG(dspcntr_reg);
- if ((temp & DISPLAY_PLANE_ENABLE) == 0)
- {
- OUTREG(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
- /* Flush the plane changes */
- OUTREG(dspbase_reg, INREG(dspbase_reg));
- }
+ /* Enable the plane */
+ temp = INREG(dspcntr_reg);
+ if ((temp & DISPLAY_PLANE_ENABLE) == 0)
+ {
+ OUTREG(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
+ /* Flush the plane changes */
+ OUTREG(dspbase_reg, INREG(dspbase_reg));
+ }
- i830_crtc_load_lut(crtc);
+ i830_crtc_load_lut(crtc);
- /* Give the overlay scaler a chance to enable if it's on this pipe */
- i830_crtc_dpms_video(crtc, TRUE);
+ /* Give the overlay scaler a chance to enable if it's on this pipe */
+ i830_crtc_dpms_video(crtc, TRUE);
- /* Reenable compression if needed */
- if (i830_use_fb_compression(crtc))
- i830_enable_fb_compression(crtc);
- i830_modeset_ctl(crtc, 0);
- break;
- case DPMSModeOff:
- i830_modeset_ctl(crtc, 1);
- /* Shut off compression if in use */
- if (i830_use_fb_compression(crtc))
- i830_disable_fb_compression(crtc);
+ /* Reenable compression if needed */
+ if (i830_use_fb_compression(crtc))
+ i830_enable_fb_compression(crtc);
+ i830_modeset_ctl(crtc, 0);
+}
- /* Give the overlay scaler a chance to disable if it's on this pipe */
- i830_crtc_dpms_video(crtc, FALSE);
+void
+i830_crtc_disable(xf86CrtcPtr crtc, Bool disable_pipe)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
+ I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+ int pipe = intel_crtc->pipe;
+ int plane = intel_crtc->plane;
+ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
+ int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
+ int dspbase_reg = (plane == 0) ? DSPABASE : DSPBBASE;
+ uint32_t temp;
- /*
- * The documentation says :
- * - Disable planes (VGA or hires)
- * - Disable pipe
- * - Disable VGA display
- */
+ i830_modeset_ctl(crtc, 1);
+ /* Shut off compression if in use */
+ if (i830_use_fb_compression(crtc))
+ i830_disable_fb_compression(crtc);
- /* Disable display plane */
- temp = INREG(dspcntr_reg);
- if ((temp & DISPLAY_PLANE_ENABLE) != 0)
- {
- OUTREG(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
- /* Flush the plane changes */
- OUTREG(dspbase_reg, INREG(dspbase_reg));
- POSTING_READ(dspbase_reg);
- }
+ /* Give the overlay scaler a chance to disable if it's on this pipe */
+ i830_crtc_dpms_video(crtc, FALSE);
- if (!IS_I9XX(pI830)) {
- /* Wait for vblank for the disable to take effect */
- i830WaitForVblank(pScrn);
- }
+ /*
+ * The documentation says :
+ * - Disable planes (VGA or hires)
+ * - Disable pipe
+ * - Disable VGA display
+ */
- /* May need to leave pipe A on */
- if ((pipe != 0) || !(pI830->quirk_flag & QUIRK_PIPEA_FORCE))
- {
- /* Next, disable display pipes */
- temp = INREG(pipeconf_reg);
- if ((temp & PIPEACONF_ENABLE) != 0) {
- OUTREG(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
- POSTING_READ(pipeconf_reg);
- }
+ /* Disable display plane */
+ temp = INREG(dspcntr_reg);
+ if ((temp & DISPLAY_PLANE_ENABLE) != 0)
+ {
+ OUTREG(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
+ /* Flush the plane changes */
+ OUTREG(dspbase_reg, INREG(dspbase_reg));
+ POSTING_READ(dspbase_reg);
+ }
- /* Wait for vblank for the disable to take effect. */
- i830WaitForVblank(pScrn);
+ if (!IS_I9XX(pI830)) {
+ /* Wait for vblank for the disable to take effect */
+ i830WaitForVblank(pScrn);
+ }
- temp = INREG(dpll_reg);
- if ((temp & DPLL_VCO_ENABLE) != 0) {
- OUTREG(dpll_reg, temp & ~DPLL_VCO_ENABLE);
- POSTING_READ(dpll_reg);
- }
+ /* May need to leave pipe A on */
+ if (disable_pipe)
+ {
+ /* Next, disable display pipes */
+ temp = INREG(pipeconf_reg);
+ if ((temp & PIPEACONF_ENABLE) != 0) {
+ OUTREG(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
+ POSTING_READ(pipeconf_reg);
+ }
- /* Wait for the clocks to turn off. */
- usleep(150);
+ /* Wait for vblank for the disable to take effect. */
+ i830WaitForVblank(pScrn);
+
+ temp = INREG(dpll_reg);
+ if ((temp & DPLL_VCO_ENABLE) != 0) {
+ OUTREG(dpll_reg, temp & ~DPLL_VCO_ENABLE);
+ POSTING_READ(dpll_reg);
}
- /* Disable the VGA plane that we never use. */
- i830_disable_vga_plane (crtc);
+ /* Wait for the clocks to turn off. */
+ usleep(150);
+ }
+ /* Disable the VGA plane that we never use. */
+ i830_disable_vga_plane (crtc);
+}
+
+/**
+ * Sets the power management mode of the pipe and plane.
+ *
+ * This code should probably grow support for turning the cursor off and back
+ * on appropriately at the same time as we're turning the pipe off/on.
+ */
+static void
+i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
+ I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+ int pipe = intel_crtc->pipe;
+ Bool disable_pipe = TRUE;
+
+ /* XXX: When our outputs are all unaware of DPMS modes other than off and
+ * on, we should map those modes to DPMSModeOff in the CRTC.
+ */
+ switch (mode) {
+ case DPMSModeOn:
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ i830_crtc_enable(crtc);
+ break;
+ case DPMSModeOff:
+ if ((pipe == 0) && (pI830->quirk_flag & QUIRK_PIPEA_FORCE))
+ disable_pipe = FALSE;
+ i830_crtc_disable(crtc, disable_pipe);
break;
}
diff --git a/src/i830_display.h b/src/i830_display.h
index 8d767b1..0ba196d 100644
--- a/src/i830_display.h
+++ b/src/i830_display.h
@@ -32,6 +32,8 @@ void i830PipeSetBase(xf86CrtcPtr crtc, int x, int y);
void i830WaitForVblank(ScrnInfoPtr pScrn);
void i830DescribeOutputConfiguration(ScrnInfoPtr pScrn);
void i830_set_new_crtc_bo(ScrnInfoPtr pScrn);
+void i830_crtc_disable(xf86CrtcPtr crtc, Bool disable_pipe);
+void i830_crtc_enable(xf86CrtcPtr crtc);
xf86CrtcPtr i830GetLoadDetectPipe(xf86OutputPtr output, DisplayModePtr mode, int *dpms_mode);
void i830ReleaseLoadDetectPipe(xf86OutputPtr output, int dpms_mode);
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 3ba5762..3977b28 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2279,7 +2279,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
/* Disable pipes */
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
- crtc->funcs->dpms(crtc, DPMSModeOff);
+ i830_crtc_disable(crtc, TRUE);
}
i830WaitForVblank(pScrn);
@@ -3469,8 +3469,9 @@ static Bool
I830EnterVT(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
- int ret;
+ int i, ret;
DPRINTF(PFX, "Enter VT\n");
@@ -3491,6 +3492,23 @@ I830EnterVT(int scrnIndex, int flags)
SaveHWState(pScrn);
}
+ /* Get the hardware into a known state if needed */
+ if (!pI830->use_drm_mode) {
+ /* Disable outputs */
+ for (i = 0; i < xf86_config->num_output; i++) {
+ xf86OutputPtr output = xf86_config->output[i];
+ output->funcs->dpms(output, DPMSModeOff);
+ }
+ i830WaitForVblank(pScrn);
+
+ /* Disable pipes */
+ for (i = 0; i < xf86_config->num_crtc; i++) {
+ xf86CrtcPtr crtc = xf86_config->crtc[i];
+ i830_crtc_disable(crtc, TRUE);
+ }
+ i830WaitForVblank(pScrn);
+ }
+
pI830->leaving = FALSE;
if (!pI830->use_drm_mode)
commit b6b56f6d3710dc31bace15c0a1db1b21e0f2f20c
Author: Keith Packard <keithp at keithp.com>
Date: Mon Mar 2 07:39:41 2009 -0800
Use CopyArea to load glyphs from per-glyph pixmap to cache pixmap
With glyphs sitting in per-glyph pixmaps, there's no reason to use the CPU
to move them to the cache pixmap, and lots of reasons to use the accelerator.
Signed-off-by: Keith Packard <keithp at keithp.com>
(cherry picked from commit fe08b81d0f5d6f96e0124e6286bd24aba6e140ad)
(also includes revert from fe08b81d0f5d6f96e0124e6286bd24aba6e140ad)
(and revert from from 78a60e1b66fe2e8449702dd43d9b062d279af8f1)
The reverts simply eliminate some unrelated changes accidentally included
with the first commit.
diff --git a/uxa/uxa-glyphs.c b/uxa/uxa-glyphs.c
index 5abd001..3cb03f5 100644
--- a/uxa/uxa-glyphs.c
+++ b/uxa/uxa-glyphs.c
@@ -353,9 +353,7 @@ uxa_glyph_cache_hash_remove(uxa_glyph_cache_t *cache,
#define CACHE_Y(pos) (cache->yOffset + ((pos) / cache->columns) * cache->glyphHeight)
/* The most efficient thing to way to upload the glyph to the screen
- * is to use the UploadToScreen() driver hook; this allows us to
- * pipeline glyph uploads and to avoid creating offscreen pixmaps for
- * glyphs that we'll never use again.
+ * is to use CopyArea; uxa pixmaps are always offscreen.
*/
static Bool
uxa_glyph_cache_upload_glyph(ScreenPtr pScreen,
@@ -363,37 +361,23 @@ uxa_glyph_cache_upload_glyph(ScreenPtr pScreen,
int pos,
GlyphPtr pGlyph)
{
- uxa_screen_t *uxa_screen = uxa_get_screen(pScreen);
PicturePtr pGlyphPicture = GlyphPicture(pGlyph)[pScreen->myNum];
PixmapPtr pGlyphPixmap = (PixmapPtr)pGlyphPicture->pDrawable;
PixmapPtr pCachePixmap = (PixmapPtr)cache->picture->pDrawable;
- int cacheXoff, cacheYoff;
-
- if (!uxa_screen->info->put_image || uxa_screen->swappedOut)
- return FALSE;
-
- /* If the glyph pixmap is already uploaded, no point in doing
- * things this way */
- if (uxa_pixmap_is_offscreen(pGlyphPixmap))
- return FALSE;
+ GCPtr pGC;
/* UploadToScreen only works if bpp match */
if (pGlyphPixmap->drawable.bitsPerPixel != pCachePixmap->drawable.bitsPerPixel)
return FALSE;
- pCachePixmap = uxa_get_offscreen_pixmap ((DrawablePtr)pCachePixmap, &cacheXoff, &cacheYoff);
- if (!pCachePixmap)
- return FALSE;
-
- if (!uxa_screen->info->put_image(pCachePixmap,
- CACHE_X(pos) + cacheXoff,
- CACHE_Y(pos) + cacheYoff,
- pGlyph->info.width,
- pGlyph->info.height,
- (char *)pGlyphPixmap->devPrivate.ptr,
- pGlyphPixmap->devKind))
- return FALSE;
-
+ pGC = GetScratchGC(pCachePixmap->drawable.depth, pScreen);
+ ValidateGC(&pCachePixmap->drawable, pGC);
+ (void) uxa_copy_area (&pGlyphPixmap->drawable,
+ &pCachePixmap->drawable,
+ pGC,
+ 0, 0, pGlyph->info.width, pGlyph->info.height,
+ CACHE_X(pos), CACHE_Y(pos));
+ FreeScratchGC (pGC);
return TRUE;
}
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