xf86-video-ati: Branch 'master' - 5 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Fri Mar 13 15:02:27 PDT 2009
src/r600_exa.c | 7 ++-----
src/r600_state.h | 2 +-
src/r600_textured_videofuncs.c | 20 ++++++++++----------
src/r6xx_accel.c | 5 +----
src/radeon_commonfuncs.c | 3 +++
src/radeon_crtc.c | 12 ++++++------
src/radeon_driver.c | 36 +++++++++++++++++++-----------------
src/radeon_macros.h | 13 ++++---------
src/radeon_probe.h | 2 +-
9 files changed, 47 insertions(+), 53 deletions(-)
New commits:
commit 1db81afe4f8db55e02a65cd22ad84c6bbb27e8ef
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Mar 13 17:51:56 2009 -0400
radeon: add support for 30 bit LUTs
All radeons have them. Thanks to Yang Zhao for figuring
this out.
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index e360d4e..cd0d55e 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -339,20 +339,20 @@ radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green,
for (i = 0; i < 64; i++) {
if (i <= 31) {
for (j = 0; j < 8; j++) {
- radeon_crtc->lut_r[i * 8 + j] = red[i] >> 8;
- radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 8;
+ radeon_crtc->lut_r[i * 8 + j] = red[i] >> 6;
+ radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 6;
}
}
for (j = 0; j < 4; j++) {
- radeon_crtc->lut_g[i * 4 + j] = green[i] >> 8;
+ radeon_crtc->lut_g[i * 4 + j] = green[i] >> 6;
}
}
} else {
for (i = 0; i < 256; i++) {
- radeon_crtc->lut_r[i] = red[i] >> 8;
- radeon_crtc->lut_g[i] = green[i] >> 8;
- radeon_crtc->lut_b[i] = blue[i] >> 8;
+ radeon_crtc->lut_r[i] = red[i] >> 6;
+ radeon_crtc->lut_g[i] = green[i] >> 6;
+ radeon_crtc->lut_b[i] = blue[i] >> 6;
}
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 2e4967f..d1b2f54 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -3122,9 +3122,9 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
for (i = 0 ; i < 256; i++) {
- lut_r[i] = radeon_crtc->lut_r[i] << 8;
- lut_g[i] = radeon_crtc->lut_g[i] << 8;
- lut_b[i] = radeon_crtc->lut_b[i] << 8;
+ lut_r[i] = radeon_crtc->lut_r[i] << 6;
+ lut_g[i] = radeon_crtc->lut_g[i] << 6;
+ lut_b[i] = radeon_crtc->lut_b[i] << 6;
}
switch (info->CurrentLayout.depth) {
@@ -3132,9 +3132,9 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
for (i = 0; i < numColors; i++) {
index = indices[i];
for (j = 0; j < 8; j++) {
- lut_r[index * 8 + j] = colors[index].red << 8;
- lut_g[index * 8 + j] = colors[index].green << 8;
- lut_b[index * 8 + j] = colors[index].blue << 8;
+ lut_r[index * 8 + j] = colors[index].red << 6;
+ lut_g[index * 8 + j] = colors[index].green << 6;
+ lut_b[index * 8 + j] = colors[index].blue << 6;
}
}
case 16:
@@ -3143,21 +3143,21 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
if (i <= 31) {
for (j = 0; j < 8; j++) {
- lut_r[index * 8 + j] = colors[index].red << 8;
- lut_b[index * 8 + j] = colors[index].blue << 8;
+ lut_r[index * 8 + j] = colors[index].red << 6;
+ lut_b[index * 8 + j] = colors[index].blue << 6;
}
}
-
+
for (j = 0; j < 4; j++) {
- lut_g[index * 4 + j] = colors[index].green << 8;
+ lut_g[index * 4 + j] = colors[index].green << 6;
}
}
default:
for (i = 0; i < numColors; i++) {
index = indices[i];
- lut_r[index] = colors[index].red << 8;
- lut_g[index] = colors[index].green << 8;
- lut_b[index] = colors[index].blue << 8;
+ lut_r[index] = colors[index].red << 6;
+ lut_g[index] = colors[index].green << 6;
+ lut_b[index] = colors[index].blue << 6;
}
break;
}
@@ -3749,7 +3749,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Initializing color map\n");
if (!miCreateDefColormap(pScreen)) return FALSE;
- if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8,
+ /* all radeons support 10 bit CLUTs */
+ if (!xf86HandleColormaps(pScreen, 256, 10,
RADEONLoadPalette, NULL,
CMAP_PALETTED_TRUECOLOR
#if 0 /* This option messes up text mode! (eich at suse.de) */
diff --git a/src/radeon_macros.h b/src/radeon_macros.h
index f19bc3e..387e5f5 100644
--- a/src/radeon_macros.h
+++ b/src/radeon_macros.h
@@ -102,17 +102,12 @@ do { \
#define OUTPAL_NEXT(r, g, b) \
do { \
if (IS_AVIVO_VARIANT) { \
- OUTREG(AVIVO_DC_LUT_30_COLOR, ((r) << 22) | ((g) << 12) | ((b) << 2)); \
- } else { \
- OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
+ OUTREG(AVIVO_DC_LUT_30_COLOR, ((r) << 20) | ((g) << 10) | (b)); \
+ } else { \
+ OUTREG(RADEON_PALETTE_30_DATA, ((r) << 20) | ((g) << 10) | (b)); \
} \
} while (0)
-#define OUTPAL_NEXT_uint32_t(v) \
-do { \
- OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \
-} while (0)
-
#define OUTPAL(idx, r, g, b) \
do { \
OUTPAL_START((idx)); \
@@ -133,7 +128,7 @@ do { \
if (IS_AVIVO_VARIANT) { \
INREG(AVIVO_DC_LUT_30_COLOR); \
} else { \
- INREG(RADEON_PALETTE_DATA); \
+ INREG(RADEON_PALETTE_30_DATA); \
} \
} while (0)
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index afc8e21..a0c6b2c 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -153,7 +153,7 @@ typedef struct _RADEONCrtcPrivateRec {
int binding;
uint32_t cursor_offset;
/* Lookup table values to be set when the CRTC is enabled */
- uint8_t lut_r[256], lut_g[256], lut_b[256];
+ uint16_t lut_r[256], lut_g[256], lut_b[256];
uint32_t crtc_offset;
int can_tile;
commit 5bb326c64ad3bf5c93943280dcbcb25c8910d1aa
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Mar 13 14:10:58 2009 -0400
R6xx/R7xx: EXA VSync Option not supported yet
diff --git a/src/r600_exa.c b/src/r600_exa.c
index f16e040..22e554d 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -2109,11 +2109,8 @@ R600DrawInit(ScreenPtr pScreen)
#endif
info->accel_state->exa->maxY = 8192;
- if (xf86ReturnOptValBool(info->Options, OPTION_EXA_VSYNC, FALSE)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA VSync enabled\n");
- info->accel_state->vsync = TRUE;
- } else
- info->accel_state->vsync = FALSE;
+ /* not supported yet */
+ info->accel_state->vsync = FALSE;
if (!exaDriverInit(pScreen, info->accel_state->exa)) {
xfree(info->accel_state->exa);
commit 8c2d40894448329e721360811c124998a17ba2ba
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Mar 13 14:03:43 2009 -0400
R6xx/R7xx: fix up vline stuff along the lines of previous chips
Avoids an additional function call.
diff --git a/src/r600_state.h b/src/r600_state.h
index 6621420..c903ded 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -245,7 +245,7 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf);
void
cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr);
void
-cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, int crtc, int start, int stop, Bool enable);
+cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, int crtc, int start, int stop);
void
fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf);
void
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 56adc6d..735231b 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -446,16 +446,16 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
EREG(accel_state->ib, SPI_INTERP_CONTROL_0, 0);
- cp_wait_vline_sync(pScrn, accel_state->ib, pPixmap,
- radeon_covering_crtc_num(pScrn,
- pPriv->drw_x,
- pPriv->drw_x + pPriv->dst_w,
- pPriv->drw_y,
- pPriv->drw_y + pPriv->dst_h,
- pPriv->desired_crtc),
- pPriv->drw_y,
- pPriv->drw_y + pPriv->dst_h,
- pPriv->vsync);
+ if (pPriv->vsync)
+ cp_wait_vline_sync(pScrn, accel_state->ib, pPixmap,
+ radeon_covering_crtc_num(pScrn,
+ pPriv->drw_x,
+ pPriv->drw_x + pPriv->dst_w,
+ pPriv->drw_y,
+ pPriv->drw_y + pPriv->dst_h,
+ pPriv->desired_crtc),
+ pPriv->drw_y,
+ pPriv->drw_y + pPriv->dst_h);
accel_state->vb_index = 0;
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 114ccf5..f93ca01 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -309,16 +309,13 @@ cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_
/* inserts a wait for vline in the command stream */
void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
- int crtc, int start, int stop, Bool enable)
+ int crtc, int start, int stop)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
uint32_t offset;
RADEONCrtcPrivatePtr radeon_crtc;
- if (!enable)
- return;
-
if ((crtc < 0) || (crtc > 1))
return;
commit 176c1b43fc3ee48e87c134446754360b3683c24b
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Mar 13 13:28:42 2009 -0400
R6xx/R7xx: return in RADEONWaitForIdleMMIO() if accel is off
Don't wait for engine idle if we haven't initialized the engine.
Behavior should be consistent with versions of the driver prior
to accel support being added.
Should fix bug 20645
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index eabd87d..a9bc7d2 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -744,6 +744,9 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
#endif
if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (!info->accelOn)
+ return;
+
/* Wait for the engine to go idle */
if (info->ChipFamily >= CHIP_FAMILY_RV770)
R600WaitForFifoFunction(pScrn, 8);
commit d538a4508248adf2debaf0cc870a2d1c48abd986
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Mar 13 13:22:03 2009 -0400
R6xx/r7xx: clarify accel messages
We only support EXA and and only with DRI.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 47a40ab..2e4967f 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2057,9 +2057,10 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
info->useEXA = TRUE;
#endif /* !USE_XAA */
#endif /* USE_EXA */
- xf86DrvMsg(pScrn->scrnIndex, from,
- "Using %s acceleration architecture\n",
- info->useEXA ? "EXA" : "XAA");
+ if (info->ChipFamily < CHIP_FAMILY_R600)
+ xf86DrvMsg(pScrn->scrnIndex, from,
+ "Using %s acceleration architecture\n",
+ info->useEXA ? "EXA" : "XAA");
#ifdef USE_EXA
if (info->useEXA) {
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