xf86-video-intel: 6 commits - configure.ac src/brw_structs.h src/exa_sf.g4a src/exa_sf.g4b src/exa_sf_mask.g4a src/exa_sf_mask.g4b src/exa_wm_affine.g4i src/exa_wm_ca.g4a src/exa_wm_ca.g4b src/exa_wm_ca_srcalpha.g4a src/exa_wm_ca_srcalpha.g4b src/exa_wm.g4i src/exa_wm_mask_affine.g4a src/exa_wm_mask_affine.g4b src/exa_wm_mask_projective.g4a src/exa_wm_mask_projective.g4b src/exa_wm_mask_sample_a.g4a src/exa_wm_mask_sample_a.g4b src/exa_wm_mask_sample_argb.g4a src/exa_wm_mask_sample_argb.g4b src/exa_wm_noca.g4a src/exa_wm_noca.g4b src/exa_wm_nomask.g4a src/exa_wm_projective.g4i src/exa_wm_src_affine.g4a src/exa_wm_src_affine.g4b src/exa_wm_src_projective.g4a src/exa_wm_src_projective.g4b src/exa_wm_src_sample_a.g4a src/exa_wm_src_sample_a.g4b src/exa_wm_src_sample_argb.g4a src/exa_wm_src_sample_argb.g4b src/exa_wm_src_sample_planar.g4a src/exa_wm_src_sample_planar.g4b src/exa_wm_write.g4a src/exa_wm_write.g4b src/exa_wm_xy.g4a src/exa_wm_xy.g4b src/exa_wm_yuv_rgb.g4a src/exa_wm_yuv_rgb.g4b src/i830_uxa.c src/i965_render.c src/i965_video.c src/Makefile.am src/packed_yuv_sf.g4a src/packed_yuv_sf.g4b src/packed_yuv_wm.g4a src/packed_yuv_wm.g4b src/render_program/exa_sf.g4a src/render_program/exa_sf.g4b src/render_program/exa_sf.g4b.gen5 src/render_program/exa_sf_mask.g4a src/render_program/exa_sf_mask.g4b src/render_program/exa_sf_mask.g4b.gen5 src/render_program/exa_wm_affine.g4i src/render_program/exa_wm_ca.g4a src/render_program/exa_wm_ca.g4b src/render_program/exa_wm_ca.g4b.gen5 src/render_program/exa_wm_ca_srcalpha.g4a src/render_program/exa_wm_ca_srcalpha.g4b src/render_program/exa_wm_ca_srcalpha.g4b.gen5 src/render_program/exa_wm.g4i src/render_program/exa_wm_mask_affine.g4a src/render_program/exa_wm_mask_affine.g4b src/render_program/exa_wm_mask_affine.g4b.gen5 src/render_program/exa_wm_mask_projective.g4a src/render_program/exa_wm_mask_projective.g4b src/render_program/exa_wm_mask_projective.g4b.gen5 src/render_program/exa_wm_mask_sample_a.g4a src/render_program/exa_wm_mask_sample_a.g4b src/render_program/exa_wm_mask_sample_a.g4b.gen5 src/render_program/exa_wm_mask_sample_argb.g4a src/render_program/exa_wm_mask_sample_argb.g4b src/render_program/exa_wm_mask_sample_argb.g4b.gen5 src/render_program/exa_wm_noca.g4a src/render_program/exa_wm_noca.g4b src/render_program/exa_wm_noca.g4b.gen5 src/render_program/exa_wm_nomask.g4a src/render_program/exa_wm_projective.g4i src/render_program/exa_wm_src_affine.g4a src/render_program/exa_wm_src_affine.g4b src/render_program/exa_wm_src_affine.g4b.gen5 src/render_program/exa_wm_src_projective.g4a src/render_program/exa_wm_src_projective.g4b src/render_program/exa_wm_src_projective.g4b.gen5 src/render_program/exa_wm_src_sample_a.g4a src/render_program/exa_wm_src_sample_a.g4b src/render_program/exa_wm_src_sample_a.g4b.gen5 src/render_program/exa_wm_src_sample_argb.g4a src/render_program/exa_wm_src_sample_argb.g4b src/render_program/exa_wm_src_sample_argb.g4b.gen5 src/render_program/exa_wm_src_sample_planar.g4a src/render_program/exa_wm_src_sample_planar.g4b src/render_program/exa_wm_src_sample_planar.g4b.gen5 src/render_program/exa_wm_write.g4a src/render_program/exa_wm_write.g4b src/render_program/exa_wm_write.g4b.gen5 src/render_program/exa_wm_xy.g4a src/render_program/exa_wm_xy.g4b src/render_program/exa_wm_xy.g4b.gen5 src/render_program/exa_wm_yuv_rgb.g4a src/render_program/exa_wm_yuv_rgb.g4b src/render_program/exa_wm_yuv_rgb.g4b.gen5 src/render_program/Makefile.am
Zhenyu Wang
zhen at kemper.freedesktop.org
Mon Jun 29 22:31:41 PDT 2009
configure.ac | 10
src/Makefile.am | 68 ---
src/brw_structs.h | 21 +
src/exa_sf.g4a | 107 ------
src/exa_sf.g4b | 15
src/exa_sf_mask.g4a | 107 ------
src/exa_sf_mask.g4b | 15
src/exa_wm.g4i | 156 --------
src/exa_wm_affine.g4i | 44 --
src/exa_wm_ca.g4a | 38 --
src/exa_wm_ca.g4b | 4
src/exa_wm_ca_srcalpha.g4a | 37 --
src/exa_wm_ca_srcalpha.g4b | 4
src/exa_wm_mask_affine.g4a | 41 --
src/exa_wm_mask_affine.g4b | 8
src/exa_wm_mask_projective.g4a | 53 --
src/exa_wm_mask_projective.g4b | 16
src/exa_wm_mask_sample_a.g4a | 48 --
src/exa_wm_mask_sample_a.g4b | 2
src/exa_wm_mask_sample_argb.g4a | 48 --
src/exa_wm_mask_sample_argb.g4b | 2
src/exa_wm_noca.g4a | 38 --
src/exa_wm_noca.g4b | 4
src/exa_wm_nomask.g4a | 143 --------
src/exa_wm_projective.g4i | 51 --
src/exa_wm_src_affine.g4a | 45 --
src/exa_wm_src_affine.g4b | 8
src/exa_wm_src_projective.g4a | 49 --
src/exa_wm_src_projective.g4b | 16
src/exa_wm_src_sample_a.g4a | 47 --
src/exa_wm_src_sample_a.g4b | 2
src/exa_wm_src_sample_argb.g4a | 47 --
src/exa_wm_src_sample_argb.g4b | 2
src/exa_wm_src_sample_planar.g4a | 65 ---
src/exa_wm_src_sample_planar.g4b | 4
src/exa_wm_write.g4a | 74 ----
src/exa_wm_write.g4b | 18 -
src/exa_wm_xy.g4a | 52 --
src/exa_wm_xy.g4b | 4
src/exa_wm_yuv_rgb.g4a | 98 -----
src/exa_wm_yuv_rgb.g4b | 12
src/i830_uxa.c | 8
src/i965_render.c | 338 +++++++++++++++----
src/i965_video.c | 190 ++++++++--
src/packed_yuv_sf.g4a | 45 --
src/packed_yuv_sf.g4b | 17
src/packed_yuv_wm.g4a | 221 ------------
src/packed_yuv_wm.g4b | 79 ----
src/render_program/Makefile.am | 82 ++++
src/render_program/exa_sf.g4a | 107 ++++++
src/render_program/exa_sf.g4b | 15
src/render_program/exa_sf.g4b.gen5 | 15
src/render_program/exa_sf_mask.g4a | 107 ++++++
src/render_program/exa_sf_mask.g4b | 15
src/render_program/exa_sf_mask.g4b.gen5 | 15
src/render_program/exa_wm.g4i | 156 ++++++++
src/render_program/exa_wm_affine.g4i | 44 ++
src/render_program/exa_wm_ca.g4a | 38 ++
src/render_program/exa_wm_ca.g4b | 4
src/render_program/exa_wm_ca.g4b.gen5 | 4
src/render_program/exa_wm_ca_srcalpha.g4a | 37 ++
src/render_program/exa_wm_ca_srcalpha.g4b | 4
src/render_program/exa_wm_ca_srcalpha.g4b.gen5 | 4
src/render_program/exa_wm_mask_affine.g4a | 41 ++
src/render_program/exa_wm_mask_affine.g4b | 8
src/render_program/exa_wm_mask_affine.g4b.gen5 | 8
src/render_program/exa_wm_mask_projective.g4a | 53 ++
src/render_program/exa_wm_mask_projective.g4b | 16
src/render_program/exa_wm_mask_projective.g4b.gen5 | 16
src/render_program/exa_wm_mask_sample_a.g4a | 48 ++
src/render_program/exa_wm_mask_sample_a.g4b | 2
src/render_program/exa_wm_mask_sample_a.g4b.gen5 | 2
src/render_program/exa_wm_mask_sample_argb.g4a | 48 ++
src/render_program/exa_wm_mask_sample_argb.g4b | 2
src/render_program/exa_wm_mask_sample_argb.g4b.gen5 | 2
src/render_program/exa_wm_noca.g4a | 38 ++
src/render_program/exa_wm_noca.g4b | 4
src/render_program/exa_wm_noca.g4b.gen5 | 4
src/render_program/exa_wm_nomask.g4a | 143 ++++++++
src/render_program/exa_wm_projective.g4i | 51 ++
src/render_program/exa_wm_src_affine.g4a | 45 ++
src/render_program/exa_wm_src_affine.g4b | 8
src/render_program/exa_wm_src_affine.g4b.gen5 | 8
src/render_program/exa_wm_src_projective.g4a | 49 ++
src/render_program/exa_wm_src_projective.g4b | 16
src/render_program/exa_wm_src_projective.g4b.gen5 | 16
src/render_program/exa_wm_src_sample_a.g4a | 47 ++
src/render_program/exa_wm_src_sample_a.g4b | 2
src/render_program/exa_wm_src_sample_a.g4b.gen5 | 2
src/render_program/exa_wm_src_sample_argb.g4a | 47 ++
src/render_program/exa_wm_src_sample_argb.g4b | 2
src/render_program/exa_wm_src_sample_argb.g4b.gen5 | 2
src/render_program/exa_wm_src_sample_planar.g4a | 65 +++
src/render_program/exa_wm_src_sample_planar.g4b | 4
src/render_program/exa_wm_src_sample_planar.g4b.gen5 | 4
src/render_program/exa_wm_write.g4a | 74 ++++
src/render_program/exa_wm_write.g4b | 18 +
src/render_program/exa_wm_write.g4b.gen5 | 18 +
src/render_program/exa_wm_xy.g4a | 52 ++
src/render_program/exa_wm_xy.g4b | 4
src/render_program/exa_wm_xy.g4b.gen5 | 4
src/render_program/exa_wm_yuv_rgb.g4a | 98 +++++
src/render_program/exa_wm_yuv_rgb.g4b | 12
src/render_program/exa_wm_yuv_rgb.g4b.gen5 | 12
104 files changed, 2195 insertions(+), 2068 deletions(-)
New commits:
commit afac333bef4a0ac934f0e4d933dc5053d81ca88c
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Tue Jun 30 11:10:52 2009 +0800
Remove unused packed yuv sampler shader programs
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am
index 72923d6..c9a0bfc 100644
--- a/src/render_program/Makefile.am
+++ b/src/render_program/Makefile.am
@@ -1,6 +1,4 @@
INTEL_G4A = \
- packed_yuv_sf.g4a \
- packed_yuv_wm.g4a \
exa_sf.g4a \
exa_sf_mask.g4a \
exa_wm_src_affine.g4a \
@@ -25,8 +23,6 @@ INTEL_G4I = \
exa_wm_projective.g4i
INTEL_G4B = \
- packed_yuv_sf.g4b \
- packed_yuv_wm.g4b \
exa_sf.g4b \
exa_sf_mask.g4b \
exa_wm_src_affine.g4b \
@@ -47,8 +43,6 @@ INTEL_G4B = \
INTEL_G4B_GEN5 = \
- packed_yuv_sf.g4b.gen5 \
- packed_yuv_wm.g4b.gen5 \
exa_sf.g4b.gen5 \
exa_sf_mask.g4b.gen5 \
exa_wm_src_affine.g4b.gen5 \
diff --git a/src/render_program/packed_yuv_sf.g4a b/src/render_program/packed_yuv_sf.g4a
deleted file mode 100644
index 5a02399..0000000
--- a/src/render_program/packed_yuv_sf.g4a
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Keith Packard <keithp at keithp.com>
- * Eric Anholt <eric at anholt.net>
- *
- */
-
-send (1) 0 g6<1>F g1.12<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
-send (1) 0 g6.4<1>F g1.20<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
-add (8) g7<1>F g4<8,8,1>F -g3<8,8,1>F { align1 };
-mul (1) g7<1>F g7<0,1,0>F g6<0,1,0>F { align1 };
-mul (1) g7.4<1>F g7.4<0,1,0>F g6.4<0,1,0>F { align1 };
-mov (8) m1<1>F g7<0,1,0>F { align1 };
-mov (8) m2<1>F g7.4<0,1,0>F { align1 };
-mov (8) m3<1>F g3<8,8,1>F { align1 };
-send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
diff --git a/src/render_program/packed_yuv_sf.g4b b/src/render_program/packed_yuv_sf.g4b
deleted file mode 100644
index 830d176..0000000
--- a/src/render_program/packed_yuv_sf.g4b
+++ /dev/null
@@ -1,17 +0,0 @@
- { 0x00000031, 0x20c01fbd, 0x0000002c, 0x01110081 },
- { 0x00000031, 0x20c41fbd, 0x00000034, 0x01110081 },
- { 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
- { 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
- { 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
- { 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
- { 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
- { 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
- { 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/packed_yuv_sf.g4b.gen5 b/src/render_program/packed_yuv_sf.g4b.gen5
deleted file mode 100644
index d4d235a..0000000
--- a/src/render_program/packed_yuv_sf.g4b.gen5
+++ /dev/null
@@ -1,17 +0,0 @@
- { 0x00000031, 0x20c01fbd, 0x1000002c, 0x02100081 },
- { 0x00000031, 0x20c41fbd, 0x10000034, 0x02100081 },
- { 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
- { 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
- { 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
- { 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
- { 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
- { 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
- { 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/packed_yuv_wm.g4a b/src/render_program/packed_yuv_wm.g4a
deleted file mode 100644
index 2be52b5..0000000
--- a/src/render_program/packed_yuv_wm.g4a
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Keith Packard <keithp at keithp.com>
- * Eric Anholt <eric at anholt.net>
- *
- */
-
-include(`exa_wm.g4i')
-
-define(`YCbCr_base', `g12')
-define(`Cr', `g12')
-define(`Cr_01', `g12')
-define(`Cr_23', `g13')
-define(`Y', `g14')
-define(`Y_01', `g14')
-define(`Y_23', `g15')
-define(`Cb', `g16')
-define(`Cb_01', `g16')
-define(`Cb_23', `g17')
-
-/* The initial payload of the thread is always g0.
- * WM_URB (incoming URB entries) is g3
- * X0_R is g4
- * X1_R is g5
- * Y0_R is g6
- * Y1_R is g7
- */
-
- /* Set up the X/Y screen coordinates of the pixels in our 4 subspans. Each
- * subspan is a 2x2 rectangle, and the screen x/y of the upper left of each
- * subspan are given in GRF register 1.2 through 1.5 (which, with the word
- * addressing below, are 1.4 through 1.11).
- *
- * The result is WM_X*_R and WM_Y*R being:
- *
- * X0: {ss0.x, ss0.x+1, ss0.x, ss0.x+1, ss1.x, ss1.x+1, ss1.x, ss1.x+y}
- * Y0: {ss0.y, ss0.y, ss0.y+1, ss0.y+1, ss1.y, ss1.y, ss1.y+1, ss1.y+1}
- * X1: {ss2.x, ss2.x+1, ss2.x, ss2.x+1, ss3.x, ss3.x+1, ss3.x, ss3.x+y}
- * Y1: {ss2.y, ss2.y, ss2.y+1, ss2.y+1, ss3.y, ss3.y, ss3.y+1, ss3.y+1}
- */
-
- /* Set up ss0.x coordinates*/
-mov (1) g4<1>F g1.8<0,1,0>UW { align1 };
-add (1) g4.4<1>F g1.8<0,1,0>UW 1UD { align1 };
-mov (1) g4.8<1>F g1.8<0,1,0>UW { align1 };
-add (1) g4.12<1>F g1.8<0,1,0>UW 1UD { align1 };
- /* Set up ss0.y coordinates */
-mov (1) g6<1>F g1.10<0,1,0>UW { align1 };
-mov (1) g6.4<1>F g1.10<0,1,0>UW { align1 };
-add (1) g6.8<1>F g1.10<0,1,0>UW 1UD { align1 };
-add (1) g6.12<1>F g1.10<0,1,0>UW 1UD { align1 };
- /* set up ss1.x coordinates */
-mov (1) g4.16<1>F g1.12<0,1,0>UW { align1 };
-add (1) g4.20<1>F g1.12<0,1,0>UW 1UD { align1 };
-mov (1) g4.24<1>F g1.12<0,1,0>UW { align1 };
-add (1) g4.28<1>F g1.12<0,1,0>UW 1UD { align1 };
- /* set up ss1.y coordinates */
-mov (1) g6.16<1>F g1.14<0,1,0>UW { align1 };
-mov (1) g6.20<1>F g1.14<0,1,0>UW { align1 };
-add (1) g6.24<1>F g1.14<0,1,0>UW 1UD { align1 };
-add (1) g6.28<1>F g1.14<0,1,0>UW 1UD { align1 };
- /* Set up ss2.x coordinates */
-mov (1) g5<1>F g1.16<0,1,0>UW { align1 };
-add (1) g5.4<1>F g1.16<0,1,0>UW 1UD { align1 };
-mov (1) g5.8<1>F g1.16<0,1,0>UW { align1 };
-add (1) g5.12<1>F g1.16<0,1,0>UW 1UD { align1 };
- /* Set up ss2.y coordinates */
-mov (1) g7<1>F g1.18<0,1,0>UW { align1 };
-mov (1) g7.4<1>F g1.18<0,1,0>UW { align1 };
-add (1) g7.8<1>F g1.18<0,1,0>UW 1UD { align1 };
-add (1) g7.12<1>F g1.18<0,1,0>UW 1UD { align1 };
- /* Set up ss3.x coordinates */
-mov (1) g5.16<1>F g1.20<0,1,0>UW { align1 };
-add (1) g5.20<1>F g1.20<0,1,0>UW 1UD { align1 };
-mov (1) g5.24<1>F g1.20<0,1,0>UW { align1 };
-add (1) g5.28<1>F g1.20<0,1,0>UW 1UD { align1 };
- /* Set up ss3.y coordinates */
-mov (1) g7.16<1>F g1.22<0,1,0>UW { align1 };
-mov (1) g7.20<1>F g1.22<0,1,0>UW { align1 };
-add (1) g7.24<1>F g1.22<0,1,0>UW 1UD { align1 };
-add (1) g7.28<1>F g1.22<0,1,0>UW 1UD { align1 };
-
- /* Now, map these screen space coordinates into texture coordinates. */
- /* subtract screen-space X origin of vertex 0. */
-add (8) g4<1>F g4<8,8,1>F -g1<0,1,0>F { align1 };
-add (8) g5<1>F g5<8,8,1>F -g1<0,1,0>F { align1 };
- /* scale by texture X increment */
-mul (8) g4<1>F g4<8,8,1>F g3<0,1,0>F { align1 };
-mul (8) g5<1>F g5<8,8,1>F g3<0,1,0>F { align1 };
- /* add in texture X offset */
-add (8) g4<1>F g4<8,8,1>F g3.12<0,1,0>F { align1 };
-add (8) g5<1>F g5<8,8,1>F g3.12<0,1,0>F { align1 };
- /* subtract screen-space Y origin of vertex 0. */
-add (8) g6<1>F g6<8,8,1>F -g1.4<0,1,0>F { align1 };
-add (8) g7<1>F g7<8,8,1>F -g1.4<0,1,0>F { align1 };
- /* scale by texture Y increment */
-mul (8) g6<1>F g6<8,8,1>F g3.20<0,1,0>F { align1 };
-mul (8) g7<1>F g7<8,8,1>F g3.20<0,1,0>F { align1 };
- /* add in texture Y offset */
-add (8) g6<1>F g6<8,8,1>F g3.28<0,1,0>F { align1 };
-add (8) g7<1>F g7<8,8,1>F g3.28<0,1,0>F { align1 };
- /* sampler */
-mov (8) m1<1>F g4<8,8,1>F { align1 };
-mov (8) m2<1>F g5<8,8,1>F { align1 };
-mov (8) m3<1>F g6<8,8,1>F { align1 };
-mov (8) m4<1>F g7<8,8,1>F { align1 };
-
- /*
- * g0 holds the PS thread payload, which (oddly) contains
- * precisely what the sampler wants to see in m0
- */
-send (16)
- 0 /* load g0 to m0 */
- YCbCr_base<1>UW
- g0<8,8,1>UW
- sampler (1,0,F)
- mlen 5 rlen 8 { align1 };
-
- /* color space conversion function:
- * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1)
- * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1)
- * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1)
- *
- * Y is g14, g15.
- * Cr is g12, g13.
- * Cb is g16, g17.
- *
- * R is g2, g6.
- * G is g3, g7.
- * B is g4, g8.
- */
-
- /* Normalize Y, Cb and Cr:
- *
- * Y = (Y - 16/255) * 1.164
- * Cr = Cr - 128 / 255
- * Cb = Cb - 128 / 255
- */
-add (16) Y<1>F Y<8,8,1>F -0.0627451F { compr align1 };
-mul (16) Y<1>F Y<8,8,1>F 1.164F { compr align1 };
-
-add (16) Cr<1>F Cr<8,8,1>F -0.501961F { compr align1 };
-
-add (16) Cb<1>F Cb<8,8,1>F -0.501961F { compr align1 };
-
- /*
- * R = Y + Cr * 1.596
- */
-mul (8) null Cr_01<8,8,1>F 1.596F { align1 };
-mac.sat (8) data_port_r_01<1>F Y_01<8,8,1>F 1F { align1 };
-mul (8) null Cr_23<8,8,1>F 1.596F { align1 };
-mac.sat (8) data_port_r_23<1>F Y_23<8,8,1>F 1F { align1 };
-
- /*
- * G = Cr * -0.813 + Cb * -0.392 + Y
- */
-mul (8) null Cr_01<8,8,1>F -0.813F { align1 };
-mac (8) null Cb_01<8,8,1>F -0.392F { align1 };
-mac.sat (8) data_port_g_01<1>F Y_01<8,8,1>F 1F { align1 };
-mul (8) null Cr_23<8,8,1>F -0.813F { align1 };
-mac (8) null Cb_23<8,8,1>F -0.392F { align1 };
-mac.sat (8) data_port_g_23<1>F Y_23<8,8,1>F 1F { align1 };
-
- /*
- * B = Cb * 2.017 + Y
- */
-mul (8) null Cb_01<8,8,1>F 2.017F { align1 };
-mac.sat (8) data_port_b_01<1>F Y_01<8,8,1>F 1F { align1 };
-mul (8) null Cb_23<8,8,1>F 2.017F { align1 };
-mac.sat (8) data_port_b_23<1>F Y_23<8,8,1>F 1F { align1 };
-
- /*
- * A = 1.0
- */
-mov (8) data_port_a_01<1>F 1.0F { align1 };
-mov (8) data_port_a_23<1>F 1.0F { align1 };
-
- /*
- * Pass through control information:
- */
-mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
-
- /*
- * Send framebuffer write message: XXX: acc0?
- */
-send (16) 0 acc0<1>UW g0<8,8,1>UW write (
- 0, /* binding table index 0 */
- 8, /* pixel scoreboard clear */
- 4, /* render target write */
- 0 /* no write commit message */
- ) mlen 10 rlen 0 { align1 EOT };
- /* padding */
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
diff --git a/src/render_program/packed_yuv_wm.g4b b/src/render_program/packed_yuv_wm.g4b
deleted file mode 100644
index f2e650a..0000000
--- a/src/render_program/packed_yuv_wm.g4b
+++ /dev/null
@@ -1,79 +0,0 @@
- { 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
- { 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
- { 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
- { 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
- { 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
- { 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
- { 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
- { 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
- { 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
- { 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
- { 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
- { 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
- { 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
- { 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
- { 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
- { 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
- { 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
- { 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
- { 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
- { 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
- { 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
- { 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
- { 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
- { 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
- { 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
- { 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
- { 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
- { 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
- { 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
- { 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
- { 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
- { 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
- { 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
- { 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
- { 0x00600041, 0x208077bd, 0x008d0080, 0x00000060 },
- { 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000060 },
- { 0x00600040, 0x208077bd, 0x008d0080, 0x0000006c },
- { 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000006c },
- { 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
- { 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
- { 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000074 },
- { 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000074 },
- { 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000007c },
- { 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000007c },
- { 0x00600001, 0x202003be, 0x008d0080, 0x00000000 },
- { 0x00600001, 0x204003be, 0x008d00a0, 0x00000000 },
- { 0x00600001, 0x206003be, 0x008d00c0, 0x00000000 },
- { 0x00600001, 0x208003be, 0x008d00e0, 0x00000000 },
- { 0x00800031, 0x21801d29, 0x008d0000, 0x02580001 },
- { 0x00802040, 0x21c07fbd, 0x008d01c0, 0xbd808081 },
- { 0x00802041, 0x21c07fbd, 0x008d01c0, 0x3f94fdf4 },
- { 0x00802040, 0x21807fbd, 0x008d0180, 0xbf008084 },
- { 0x00802040, 0x22007fbd, 0x008d0200, 0xbf008084 },
- { 0x00600041, 0x20007fbc, 0x008d0180, 0x3fcc49ba },
- { 0x80600048, 0x20407fbe, 0x008d01c0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d01a0, 0x3fcc49ba },
- { 0x80600048, 0x20c07fbe, 0x008d01e0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d0180, 0xbf5020c5 },
- { 0x00600048, 0x20007fbc, 0x008d0200, 0xbec8b439 },
- { 0x80600048, 0x20607fbe, 0x008d01c0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d01a0, 0xbf5020c5 },
- { 0x00600048, 0x20007fbc, 0x008d0220, 0xbec8b439 },
- { 0x80600048, 0x20e07fbe, 0x008d01e0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d0200, 0x40011687 },
- { 0x80600048, 0x20807fbe, 0x008d01c0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d0220, 0x40011687 },
- { 0x80600048, 0x21007fbe, 0x008d01e0, 0x3f800000 },
- { 0x00600001, 0x20a003fe, 0x00000000, 0x3f800000 },
- { 0x00600001, 0x212003fe, 0x00000000, 0x3f800000 },
- { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
- { 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/packed_yuv_wm.g4b.gen5 b/src/render_program/packed_yuv_wm.g4b.gen5
deleted file mode 100644
index 43fefa6..0000000
--- a/src/render_program/packed_yuv_wm.g4b.gen5
+++ /dev/null
@@ -1,79 +0,0 @@
- { 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
- { 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
- { 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
- { 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
- { 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
- { 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
- { 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
- { 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
- { 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
- { 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
- { 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
- { 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
- { 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
- { 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
- { 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
- { 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
- { 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
- { 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
- { 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
- { 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
- { 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
- { 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
- { 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
- { 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
- { 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
- { 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
- { 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
- { 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
- { 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
- { 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
- { 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
- { 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
- { 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
- { 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
- { 0x00600041, 0x208077bd, 0x008d0080, 0x00000060 },
- { 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000060 },
- { 0x00600040, 0x208077bd, 0x008d0080, 0x0000006c },
- { 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000006c },
- { 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
- { 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
- { 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000074 },
- { 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000074 },
- { 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000007c },
- { 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000007c },
- { 0x00600001, 0x202003be, 0x008d0080, 0x00000000 },
- { 0x00600001, 0x204003be, 0x008d00a0, 0x00000000 },
- { 0x00600001, 0x206003be, 0x008d00c0, 0x00000000 },
- { 0x00600001, 0x208003be, 0x008d00e0, 0x00000000 },
- { 0x00800031, 0x21801d29, 0x208d0000, 0x0a8a0001 },
- { 0x00802040, 0x21c07fbd, 0x008d01c0, 0xbd808081 },
- { 0x00802041, 0x21c07fbd, 0x008d01c0, 0x3f94fdf4 },
- { 0x00802040, 0x21807fbd, 0x008d0180, 0xbf008084 },
- { 0x00802040, 0x22007fbd, 0x008d0200, 0xbf008084 },
- { 0x00600041, 0x20007fbc, 0x008d0180, 0x3fcc49ba },
- { 0x80600048, 0x20407fbe, 0x008d01c0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d01a0, 0x3fcc49ba },
- { 0x80600048, 0x20c07fbe, 0x008d01e0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d0180, 0xbf5020c5 },
- { 0x00600048, 0x20007fbc, 0x008d0200, 0xbec8b439 },
- { 0x80600048, 0x20607fbe, 0x008d01c0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d01a0, 0xbf5020c5 },
- { 0x00600048, 0x20007fbc, 0x008d0220, 0xbec8b439 },
- { 0x80600048, 0x20e07fbe, 0x008d01e0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d0200, 0x40011687 },
- { 0x80600048, 0x20807fbe, 0x008d01c0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d0220, 0x40011687 },
- { 0x80600048, 0x21007fbe, 0x008d01e0, 0x3f800000 },
- { 0x00600001, 0x20a003fe, 0x00000000, 0x3f800000 },
- { 0x00600001, 0x212003fe, 0x00000000, 0x3f800000 },
- { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
- { 0x00800031, 0x24001d28, 0x548d0000, 0x94084800 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
commit 150c9adebc0b502f19c970783f411928e5a5c3b1
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Tue Jun 30 10:42:41 2009 +0800
Xv: fix domain usage for binding table on i965+ chips
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/i965_video.c b/src/i965_video.c
index 012799b..805b33f 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -857,7 +857,7 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
/* Only the PS uses the binding table */
- OUT_RELOC(bind_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
/* Blend constant color (magenta is fun) */
OUT_BATCH(BRW_3DSTATE_CONSTANT_COLOR | 3);
commit 7770958e42d60966d95702e75c704e20ae2d90dd
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Tue Jun 30 10:41:26 2009 +0800
Add XV support on IGDNG
This brings necessary change for IGDNG for texture video support
from 2D render code.
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/i965_video.c b/src/i965_video.c
index d459027..012799b 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -110,6 +110,27 @@ static const uint32_t ps_kernel_planar_static[][4] = {
#include "exa_wm_write.g4b"
};
+/* new program for IGDNG */
+static const uint32_t sf_kernel_static_gen5[][4] = {
+#include "exa_sf.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_packed_static_gen5[][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_affine.g4b.gen5"
+#include "exa_wm_src_sample_argb.g4b.gen5"
+#include "exa_wm_yuv_rgb.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_planar_static_gen5[][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_affine.g4b.gen5"
+#include "exa_wm_src_sample_planar.g4b.gen5"
+#include "exa_wm_yuv_rgb.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1))
#define MIN(a,b) ((a) < (b) ? (a) : (b))
@@ -498,7 +519,10 @@ i965_create_vs_state(ScrnInfoPtr scrn)
return NULL;
/* Set up the vertex shader to be disabled (passthrough) */
- vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
+ if (IS_IGDNG(pI830))
+ vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
+ else
+ vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
vs_state->vs6.vs_enable = 0;
vs_state->vs6.vert_cache_disable = 1;
@@ -531,8 +555,12 @@ i965_create_sf_state(ScrnInfoPtr scrn)
drm_intel_bo *sf_bo, *kernel_bo;
struct brw_sf_unit_state *sf_state;
- kernel_bo = i965_create_program(scrn, &sf_kernel_static[0][0],
- sizeof(sf_kernel_static));
+ if (IS_IGDNG(pI830))
+ kernel_bo = i965_create_program(scrn, &sf_kernel_static_gen5[0][0],
+ sizeof(sf_kernel_static_gen5));
+ else
+ kernel_bo = i965_create_program(scrn, &sf_kernel_static[0][0],
+ sizeof(sf_kernel_static));
if (!kernel_bo)
return NULL;
@@ -591,11 +619,19 @@ i965_create_wm_state(ScrnInfoPtr scrn, drm_intel_bo *sampler_bo, Bool is_packed)
struct brw_wm_unit_state *wm_state;
if (is_packed) {
- kernel_bo = i965_create_program(scrn, &ps_kernel_packed_static[0][0],
- sizeof(ps_kernel_packed_static));
+ if (IS_IGDNG(pI830))
+ kernel_bo = i965_create_program(scrn, &ps_kernel_packed_static_gen5[0][0],
+ sizeof(ps_kernel_packed_static_gen5));
+ else
+ kernel_bo = i965_create_program(scrn, &ps_kernel_packed_static[0][0],
+ sizeof(ps_kernel_packed_static));
} else {
- kernel_bo = i965_create_program(scrn, &ps_kernel_planar_static[0][0],
- sizeof(ps_kernel_planar_static));
+ if (IS_IGDNG(pI830))
+ kernel_bo = i965_create_program(scrn, &ps_kernel_planar_static_gen5[0][0],
+ sizeof(ps_kernel_planar_static_gen5));
+ else
+ kernel_bo = i965_create_program(scrn, &ps_kernel_planar_static[0][0],
+ sizeof(ps_kernel_planar_static));
}
if (!kernel_bo)
return NULL;
@@ -616,6 +652,13 @@ i965_create_wm_state(ScrnInfoPtr scrn, drm_intel_bo *sampler_bo, Bool is_packed)
wm_state->thread1.binding_table_entry_count = 2;
else
wm_state->thread1.binding_table_entry_count = 7;
+
+ /* binding table entry count is only used for prefetching, and it has to
+ * be set 0 for IGDNG
+ */
+ if (IS_IGDNG(pI830))
+ wm_state->thread1.binding_table_entry_count = 0;
+
/* Though we never use the scratch space in our WM kernel, it has to be
* set, and the minimum allocation is 1024 bytes.
*/
@@ -631,7 +674,10 @@ i965_create_wm_state(ScrnInfoPtr scrn, drm_intel_bo *sampler_bo, Bool is_packed)
intel_emit_reloc(wm_bo, offsetof(struct brw_wm_unit_state, wm4),
sampler_bo, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
- wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
+ if (IS_IGDNG(pI830))
+ wm_state->wm4.sampler_count = 0;
+ else
+ wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
wm_state->wm5.thread_dispatch_enable = 1;
wm_state->wm5.enable_16_pix = 1;
@@ -713,6 +759,7 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
int urb_clip_start, urb_clip_size;
int urb_sf_start, urb_sf_size;
int urb_cs_start, urb_cs_size;
+ int pipe_ctl;
IntelEmitInvarientState(pScrn);
pI830->last_3d = LAST_3D_VIDEO;
@@ -736,9 +783,12 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
ADVANCE_BATCH();
/* brw_debug (pScrn, "before base address modify"); */
- BEGIN_BATCH(12);
+ if (IS_IGDNG(pI830))
+ BEGIN_BATCH(14);
+ else
+ BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_G4X(pI830))
+ if (IS_G4X(pI830) || IS_IGDNG(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
@@ -751,14 +801,28 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
/* Zero out the two base address registers so all offsets are
* absolute
*/
- OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
- /* general state max addr, disabled */
- OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
- /* media object state max addr, disabled */
- OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ if (IS_IGDNG(pI830)) {
+ OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6);
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction base address */
+ /* general state max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ /* media object state max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ /* Instruction max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ } else {
+ OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
+ /* general state max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ /* media object state max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ }
/* Set system instruction pointer */
OUT_BATCH(BRW_STATE_SIP | 0);
@@ -771,14 +835,17 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
/* brw_debug (pScrn, "after base address modify"); */
+ if (IS_IGDNG(pI830))
+ pipe_ctl = BRW_PIPE_CONTROL_NOWRITE;
+ else
+ pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
+
BEGIN_BATCH(38);
+
OUT_BATCH(MI_NOOP);
/* Pipe control */
- OUT_BATCH(BRW_PIPE_CONTROL |
- BRW_PIPE_CONTROL_NOWRITE |
- BRW_PIPE_CONTROL_IS_FLUSH |
- 2);
+ OUT_BATCH(BRW_PIPE_CONTROL | pipe_ctl | 2);
OUT_BATCH(0); /* Destination address */
OUT_BATCH(0); /* Immediate data low DW */
OUT_BATCH(0); /* Immediate data high DW */
@@ -849,27 +916,50 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
(URB_CS_ENTRIES << 0));
/* Set up our vertex elements, sourced from the single vertex buffer. */
- OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
- /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
- OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
- VE0_VALID |
- (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
- (0 << VE0_OFFSET_SHIFT));
- OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
- (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
- (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
- /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
- OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
- VE0_VALID |
- (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
- (8 << VE0_OFFSET_SHIFT));
- OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
- (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
- (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+
+ if (IS_IGDNG(pI830)) {
+ OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
+ /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
+ OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ VE0_VALID |
+ (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+ (0 << VE0_OFFSET_SHIFT));
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
+ /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
+ OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ VE0_VALID |
+ (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+ (8 << VE0_OFFSET_SHIFT));
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
+ } else {
+ OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
+ /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
+ OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ VE0_VALID |
+ (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+ (0 << VE0_OFFSET_SHIFT));
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+ (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+ /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
+ OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ VE0_VALID |
+ (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+ (8 << VE0_OFFSET_SHIFT));
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+ (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+ }
OUT_BATCH(MI_NOOP); /* pad to quadword */
ADVANCE_BATCH();
@@ -1112,7 +1202,8 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
drm_intel_bo_unmap(vb_bo);
- i965_pre_draw_debug(pScrn);
+ if (!IS_IGDNG(pI830))
+ i965_pre_draw_debug(pScrn);
/* If this command won't fit in the current batch, flush.
* Assume that it does after being flushed.
@@ -1134,7 +1225,10 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
VB0_VERTEXDATA |
((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
- OUT_BATCH(3); /* four corners to our rectangle */
+ if (IS_IGDNG(pI830))
+ OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, (vb_bo->offset + i) * 4);
+ else
+ OUT_BATCH(3); /* four corners to our rectangle */
OUT_BATCH(0); /* reserved */
OUT_BATCH(BRW_3DPRIMITIVE |
@@ -1154,7 +1248,9 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
drm_intel_bo_unreference(vb_bo);
- i965_post_draw_debug(pScrn);
+ if (!IS_IGDNG(pI830))
+ i965_post_draw_debug(pScrn);
+
}
/* release reference once we're finished */
commit f806fe7d675b966680a63406167ce37e4f8a1ae8
Author: Xiang Haihao <haihao.xiang at intel.com>
Date: Thu Jun 25 15:39:32 2009 +0800
Enable 2D composite on IGDNG
This patch enables 2D composite on IGDNG. IGDNG requires
new compiled shader programs for Gen5 and some command changes.
The most notable is the layout of vertex element has changed,
but we tried to keep it as origin to not change shader programs.
Also vertex buffer state requires end address of vertex buffer
instead of origin max index.
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/brw_structs.h b/src/brw_structs.h
index 022915d..1cee5bd 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
@@ -838,6 +838,27 @@ struct brw_wm_unit_state
float global_depth_offset_constant;
float global_depth_offset_scale;
+
+ struct {
+ unsigned int pad0:1;
+ unsigned int grf_reg_count_1:3;
+ unsigned int pad1:2;
+ unsigned int kernel_start_pointer_1:26;
+ } wm8;
+
+ struct {
+ unsigned int pad0:1;
+ unsigned int grf_reg_count_2:3;
+ unsigned int pad1:2;
+ unsigned int kernel_start_pointer_2:26;
+ } wm9;
+
+ struct {
+ unsigned int pad0:1;
+ unsigned int grf_reg_count_3:3;
+ unsigned int pad1:2;
+ unsigned int kernel_start_pointer_3:26;
+ } wm10;
};
/* The hardware supports two different modes for border color. The
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index faf4d5d..eb35014 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -722,14 +722,6 @@ i830_uxa_init (ScreenPtr pScreen)
i830->uxa_driver->done_composite = i830_done_composite;
}
- /* FIXME */
- if (IS_IGDNG(i830)) {
- i830->uxa_driver->check_composite = NULL;
- i830->uxa_driver->prepare_composite = NULL;
- i830->uxa_driver->composite = NULL;
- i830->uxa_driver->done_composite = NULL;
- }
-
i830->uxa_driver->prepare_access = i830_uxa_prepare_access;
i830->uxa_driver->finish_access = i830_uxa_finish_access;
i830->uxa_driver->pixmap_is_offscreen = i830_uxa_pixmap_is_offscreen;
diff --git a/src/i965_render.c b/src/i965_render.c
index e527f11..8ab984d 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -390,6 +390,89 @@ static const uint32_t ps_kernel_masknoca_projective_static [][4] = {
#include "exa_wm_write.g4b"
};
+/* new programs for IGDNG */
+static const uint32_t sf_kernel_static_gen5[][4] = {
+#include "exa_sf.g4b.gen5"
+};
+
+static const uint32_t sf_kernel_mask_static_gen5[][4] = {
+#include "exa_sf_mask.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_nomask_affine_static_gen5 [][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_affine.g4b.gen5"
+#include "exa_wm_src_sample_argb.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_nomask_projective_static_gen5 [][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_projective.g4b.gen5"
+#include "exa_wm_src_sample_argb.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_maskca_affine_static_gen5 [][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_affine.g4b.gen5"
+#include "exa_wm_src_sample_argb.g4b.gen5"
+#include "exa_wm_mask_affine.g4b.gen5"
+#include "exa_wm_mask_sample_argb.g4b.gen5"
+#include "exa_wm_ca.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_maskca_projective_static_gen5 [][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_projective.g4b.gen5"
+#include "exa_wm_src_sample_argb.g4b.gen5"
+#include "exa_wm_mask_projective.g4b.gen5"
+#include "exa_wm_mask_sample_argb.g4b.gen5"
+#include "exa_wm_ca.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_maskca_srcalpha_affine_static_gen5 [][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_affine.g4b.gen5"
+#include "exa_wm_src_sample_a.g4b.gen5"
+#include "exa_wm_mask_affine.g4b.gen5"
+#include "exa_wm_mask_sample_argb.g4b.gen5"
+#include "exa_wm_ca_srcalpha.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_maskca_srcalpha_projective_static_gen5 [][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_projective.g4b.gen5"
+#include "exa_wm_src_sample_a.g4b.gen5"
+#include "exa_wm_mask_projective.g4b.gen5"
+#include "exa_wm_mask_sample_argb.g4b.gen5"
+#include "exa_wm_ca_srcalpha.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_masknoca_affine_static_gen5 [][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_affine.g4b.gen5"
+#include "exa_wm_src_sample_argb.g4b.gen5"
+#include "exa_wm_mask_affine.g4b.gen5"
+#include "exa_wm_mask_sample_a.g4b.gen5"
+#include "exa_wm_noca.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
+static const uint32_t ps_kernel_masknoca_projective_static_gen5 [][4] = {
+#include "exa_wm_xy.g4b.gen5"
+#include "exa_wm_src_projective.g4b.gen5"
+#include "exa_wm_src_sample_argb.g4b.gen5"
+#include "exa_wm_mask_projective.g4b.gen5"
+#include "exa_wm_mask_sample_a.g4b.gen5"
+#include "exa_wm_noca.g4b.gen5"
+#include "exa_wm_write.g4b.gen5"
+};
+
#define WM_STATE_DECL(kernel) \
struct brw_wm_unit_state wm_state_ ## kernel[SAMPLER_STATE_FILTER_COUNT] \
[SAMPLER_STATE_EXTEND_COUNT] \
@@ -431,11 +514,13 @@ typedef enum {
#define KERNEL(kernel_enum, kernel, masked) \
[kernel_enum] = {&kernel, sizeof(kernel), masked}
-static struct wm_kernel_info {
+struct wm_kernel_info {
void *data;
unsigned int size;
Bool has_mask;
-} wm_kernels[] = {
+};
+
+static struct wm_kernel_info wm_kernels[] = {
KERNEL(WM_KERNEL_NOMASK_AFFINE,
ps_kernel_nomask_affine_static, FALSE),
KERNEL(WM_KERNEL_NOMASK_PROJECTIVE,
@@ -453,6 +538,25 @@ static struct wm_kernel_info {
KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE,
ps_kernel_masknoca_projective_static, TRUE),
};
+
+static struct wm_kernel_info wm_kernels_gen5[] = {
+ KERNEL(WM_KERNEL_NOMASK_AFFINE,
+ ps_kernel_nomask_affine_static_gen5, FALSE),
+ KERNEL(WM_KERNEL_NOMASK_PROJECTIVE,
+ ps_kernel_nomask_projective_static_gen5, FALSE),
+ KERNEL(WM_KERNEL_MASKCA_AFFINE,
+ ps_kernel_maskca_affine_static_gen5, TRUE),
+ KERNEL(WM_KERNEL_MASKCA_PROJECTIVE,
+ ps_kernel_maskca_projective_static_gen5, TRUE),
+ KERNEL(WM_KERNEL_MASKCA_SRCALPHA_AFFINE,
+ ps_kernel_maskca_srcalpha_affine_static_gen5, TRUE),
+ KERNEL(WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE,
+ ps_kernel_maskca_srcalpha_projective_static_gen5, TRUE),
+ KERNEL(WM_KERNEL_MASKNOCA_AFFINE,
+ ps_kernel_masknoca_affine_static_gen5, TRUE),
+ KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE,
+ ps_kernel_masknoca_projective_static_gen5, TRUE),
+};
#undef KERNEL
typedef struct _brw_cc_unit_state_padded {
@@ -768,7 +872,12 @@ gen4_create_wm_state(ScrnInfoPtr scrn,
wm_state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */
wm_state->wm4.stats_enable = 1; /* statistic */
- wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
+
+ if (IS_IGDNG(pI830))
+ wm_state->wm4.sampler_count = 0; /* hardware requirement */
+ else
+ wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
+
wm_state->wm4.sampler_state_pointer =
intel_emit_reloc(wm_state_bo, offsetof(struct brw_wm_unit_state, wm4),
sampler_bo,
@@ -794,6 +903,12 @@ gen4_create_wm_state(ScrnInfoPtr scrn,
wm_state->thread3.urb_entry_read_length = 2;
}
+ /* binding table entry count is only used for prefetching, and it has to
+ * be set 0 for IGDNG
+ */
+ if (IS_IGDNG(pI830))
+ wm_state->thread1.binding_table_entry_count = 0;
+
drm_intel_bo_unmap(wm_state_bo);
return wm_state_bo;
@@ -819,11 +934,15 @@ gen4_create_cc_viewport(ScrnInfoPtr scrn)
static drm_intel_bo *
gen4_create_vs_unit_state(ScrnInfoPtr scrn)
{
+ I830Ptr pI830 = I830PTR(scrn);
struct brw_vs_unit_state vs_state;
memset(&vs_state, 0, sizeof(vs_state));
/* Set up the vertex shader to be disabled (passthrough) */
- vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES;
+ if (IS_IGDNG(pI830))
+ vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES >> 2; /* hardware requirement */
+ else
+ vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES;
vs_state.thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
vs_state.vs6.vs_enable = 0;
vs_state.vs6.vert_cache_disable = 1;
@@ -1040,10 +1159,13 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
ADVANCE_BATCH();
}
{
- BEGIN_BATCH(12);
+ if (IS_IGDNG(pI830))
+ BEGIN_BATCH(14);
+ else
+ BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_G4X(pI830))
+ if (IS_G4X(pI830) || IS_IGDNG(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
@@ -1055,15 +1177,28 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
/* Zero out the two base address registers so all offsets are
* absolute.
*/
- OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
- /* general state max addr, disabled */
- OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
- /* media object state max addr, disabled */
- OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
-
+ if (IS_IGDNG(pI830)) {
+ OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6);
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction base address */
+ /* general state max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ /* media object state max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ /* Instruction max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ } else {
+ OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
+ /* general state max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ /* media object state max addr, disabled */
+ OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ }
/* Set system instruction pointer */
OUT_BATCH(BRW_STATE_SIP | 0);
OUT_RELOC(render_state->sip_kernel_bo,
@@ -1072,12 +1207,16 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
ADVANCE_BATCH();
}
{
+ int pipe_ctrl;
BEGIN_BATCH(26);
/* Pipe control */
- OUT_BATCH(BRW_PIPE_CONTROL |
- BRW_PIPE_CONTROL_NOWRITE |
- BRW_PIPE_CONTROL_IS_FLUSH |
- 2);
+
+ if (IS_IGDNG(pI830))
+ pipe_ctrl = BRW_PIPE_CONTROL_NOWRITE;
+ else
+ pipe_ctrl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
+
+ OUT_BATCH(BRW_PIPE_CONTROL | pipe_ctrl | 2);
OUT_BATCH(0); /* Destination address */
OUT_BATCH(0); /* Immediate data low DW */
OUT_BATCH(0); /* Immediate data high DW */
@@ -1174,44 +1313,92 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
src_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
w_component = BRW_VFCOMPONENT_STORE_SRC;
}
- BEGIN_BATCH(pMask?7:5);
- /* Set up our vertex elements, sourced from the single vertex buffer.
- * that will be set up later.
- */
-
- OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * (1 + nelem)) - 1));
+
+ if (IS_IGDNG(pI830)) {
+ BEGIN_BATCH(pMask?9:7);
+ /*
+ * The reason to add this extra vertex element in the header is that
+ * IGDNG has different vertex header definition and origin method to
+ * set destination element offset doesn't exist anymore, which means
+ * hardware requires a predefined vertex element layout.
+ *
+ * haihao proposed this approach to fill the first vertex element, so
+ * origin layout for Gen4 doesn't need to change, and origin shader
+ * programs behavior is also kept.
+ *
+ * I think this is not bad. - zhenyu
+ */
+
+ OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * (2 + nelem)) - 1));
+ OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ VE0_VALID |
+ (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+ (0 << VE0_OFFSET_SHIFT));
+
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
+ } else {
+ BEGIN_BATCH(pMask?7:5);
+ /* Set up our vertex elements, sourced from the single vertex buffer.
+ * that will be set up later.
+ */
+ OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * (1 + nelem)) - 1));
+ }
+
/* x,y */
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
- (0 << VE0_OFFSET_SHIFT));
- OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
- (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
- (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+ (0 << VE0_OFFSET_SHIFT));
+
+ if (IS_IGDNG(pI830))
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
+ else
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+ (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
/* u0, v0, w0 */
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(src_format << VE0_FORMAT_SHIFT) |
- ((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
- OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
- (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
- (w_component << VE1_VFCOMPONENT_2_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
- ((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
+ ((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
+
+ if (IS_IGDNG(pI830))
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (w_component << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
+ else
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (w_component << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+ ((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
/* u1, v1, w1 */
if (pMask) {
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(src_format << VE0_FORMAT_SHIFT) |
- (((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */
+ (((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */
- OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
- (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
- (w_component << VE1_VFCOMPONENT_2_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
- ((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
+ if (IS_IGDNG(pI830))
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (w_component << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
+ else
+ OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (w_component << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+ ((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
}
ADVANCE_BATCH();
@@ -1583,7 +1770,12 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
VB0_VERTEXDATA |
(render_state->vertex_size << VB0_BUFFER_PITCH_SHIFT));
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, render_state->vb_offset * 4);
- OUT_BATCH(3);
+
+ if (IS_IGDNG(pI830))
+ OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, render_state->vb_offset * 4 + i * 4);
+ else
+ OUT_BATCH(3);
+
OUT_BATCH(0); // ignore for VERTEXDATA, but still there
OUT_BATCH(BRW_3DPRIMITIVE |
@@ -1644,14 +1836,25 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
render_state->vs_state_bo = gen4_create_vs_unit_state(pScrn);
/* Set up the two SF states (one for blending with a mask, one without) */
- sf_kernel_bo = intel_bo_alloc_for_data(pScrn,
- sf_kernel_static,
- sizeof(sf_kernel_static),
- "sf kernel");
- sf_kernel_mask_bo = intel_bo_alloc_for_data(pScrn,
- sf_kernel_mask_static,
- sizeof(sf_kernel_mask_static),
- "sf mask kernel");
+ if (IS_IGDNG(pI830)) {
+ sf_kernel_bo = intel_bo_alloc_for_data(pScrn,
+ sf_kernel_static_gen5,
+ sizeof(sf_kernel_static_gen5),
+ "sf kernel gen5");
+ sf_kernel_mask_bo = intel_bo_alloc_for_data(pScrn,
+ sf_kernel_mask_static_gen5,
+ sizeof(sf_kernel_mask_static_gen5),
+ "sf mask kernel");
+ } else {
+ sf_kernel_bo = intel_bo_alloc_for_data(pScrn,
+ sf_kernel_static,
+ sizeof(sf_kernel_static),
+ "sf kernel");
+ sf_kernel_mask_bo = intel_bo_alloc_for_data(pScrn,
+ sf_kernel_mask_static,
+ sizeof(sf_kernel_mask_static),
+ "sf mask kernel");
+ }
render_state->sf_state_bo = gen4_create_sf_state(pScrn, sf_kernel_bo);
render_state->sf_mask_state_bo = gen4_create_sf_state(pScrn,
sf_kernel_mask_bo);
@@ -1659,10 +1862,16 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
drm_intel_bo_unreference(sf_kernel_mask_bo);
for (m = 0; m < WM_KERNEL_COUNT; m++) {
- render_state->wm_kernel_bo[m] =
- intel_bo_alloc_for_data(pScrn,
- wm_kernels[m].data, wm_kernels[m].size,
- "WM kernel");
+ if (IS_IGDNG(pI830))
+ render_state->wm_kernel_bo[m] =
+ intel_bo_alloc_for_data(pScrn,
+ wm_kernels_gen5[m].data, wm_kernels_gen5[m].size,
+ "WM kernel gen5");
+ else
+ render_state->wm_kernel_bo[m] =
+ intel_bo_alloc_for_data(pScrn,
+ wm_kernels[m].data, wm_kernels[m].size,
+ "WM kernel");
}
/* Set up the WM states: each filter/extend type for source and mask, per
@@ -1682,11 +1891,18 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
border_color_bo);
for (m = 0; m < WM_KERNEL_COUNT; m++) {
- render_state->wm_state_bo[m][i][j][k][l] =
- gen4_create_wm_state(pScrn,
- wm_kernels[m].has_mask,
- render_state->wm_kernel_bo[m],
- sampler_state_bo);
+ if (IS_IGDNG(pI830))
+ render_state->wm_state_bo[m][i][j][k][l] =
+ gen4_create_wm_state(pScrn,
+ wm_kernels_gen5[m].has_mask,
+ render_state->wm_kernel_bo[m],
+ sampler_state_bo);
+ else
+ render_state->wm_state_bo[m][i][j][k][l] =
+ gen4_create_wm_state(pScrn,
+ wm_kernels[m].has_mask,
+ render_state->wm_kernel_bo[m],
+ sampler_state_bo);
}
drm_intel_bo_unreference(sampler_state_bo);
}
commit 9fb34012f667e37f480085696ef9c2632d6eb7e1
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Thu Jun 25 15:30:04 2009 +0800
Add new compiled shader program for IGDNG
Also check intel-gen4asm tool here for new -g option, which is
required to compile new programs.
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/configure.ac b/configure.ac
index 397336c..486fed7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -47,6 +47,15 @@ AC_PROG_CC
AM_PROG_CC_C_O
AC_CHECK_PROG(gen4asm, [intel-gen4asm], yes, no)
+
+if test x$gen4asm != xno; then
+ intel-gen4asm -g 5 src/render_program/exa_sf.g4a > /dev/null
+
+ if test "$?" != "0"; then
+ echo "Error: Require new intel-gen4asm with -g option!"
+ exit 1
+ fi
+fi
AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes)
AC_CHECK_HEADERS(sys/mman.h)
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am
index 820303f..72923d6 100644
--- a/src/render_program/Makefile.am
+++ b/src/render_program/Makefile.am
@@ -46,21 +46,43 @@ INTEL_G4B = \
exa_wm_xy.g4b
+INTEL_G4B_GEN5 = \
+ packed_yuv_sf.g4b.gen5 \
+ packed_yuv_wm.g4b.gen5 \
+ exa_sf.g4b.gen5 \
+ exa_sf_mask.g4b.gen5 \
+ exa_wm_src_affine.g4b.gen5 \
+ exa_wm_src_projective.g4b.gen5 \
+ exa_wm_src_sample_argb.g4b.gen5 \
+ exa_wm_src_sample_a.g4b.gen5 \
+ exa_wm_src_sample_planar.g4b.gen5 \
+ exa_wm_mask_affine.g4b.gen5 \
+ exa_wm_mask_projective.g4b.gen5 \
+ exa_wm_mask_sample_argb.g4b.gen5 \
+ exa_wm_mask_sample_a.g4b.gen5 \
+ exa_wm_noca.g4b.gen5 \
+ exa_wm_ca.g4b.gen5 \
+ exa_wm_ca_srcalpha.g4b.gen5 \
+ exa_wm_write.g4b.gen5 \
+ exa_wm_yuv_rgb.g4b.gen5 \
+ exa_wm_xy.g4b.gen5
+
EXTRA_DIST = \
$(INTEL_G4A) \
$(INTEL_G4I) \
- $(INTEL_G4B)
+ $(INTEL_G4B) \
+ $(INTEL_G4B_GEN5)
if HAVE_GEN4ASM
SUFFIXES = .g4a .g4b
.g4a.g4b:
- m4 -I$(srcdir) -s $< > $*.g4m && intel-gen4asm -o $@ $*.g4m && rm $*.g4m
+ m4 -I$(srcdir) -s $< > $*.g4m && intel-gen4asm -o $@ $*.g4m && intel-gen4asm -g 5 -o $@.gen5 $*.g4m && rm $*.g4m
$(INTEL_G4B): $(INTEL_G4I)
BUILT_SOURCES= $(INTEL_G4B)
clean-local:
- -rm -f $(INTEL_G4B)
+ -rm -f $(INTEL_G4B) $(INTEL_G4B_GEN5)
endif
diff --git a/src/render_program/exa_sf.g4b.gen5 b/src/render_program/exa_sf.g4b.gen5
new file mode 100644
index 0000000..a838f47
--- /dev/null
+++ b/src/render_program/exa_sf.g4b.gen5
@@ -0,0 +1,15 @@
+ { 0x00400031, 0x20c01fbd, 0x1069002c, 0x02100001 },
+ { 0x00400001, 0x206003be, 0x00690060, 0x00000000 },
+ { 0x00400040, 0x20e077bd, 0x00690080, 0x006940a0 },
+ { 0x00400041, 0x202077be, 0x006900e0, 0x000000c0 },
+ { 0x00400040, 0x20e077bd, 0x006900a0, 0x00694060 },
+ { 0x00400041, 0x204077be, 0x006900e0, 0x000000c8 },
+ { 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_sf_mask.g4b.gen5 b/src/render_program/exa_sf_mask.g4b.gen5
new file mode 100644
index 0000000..ca4d8c4
--- /dev/null
+++ b/src/render_program/exa_sf_mask.g4b.gen5
@@ -0,0 +1,15 @@
+ { 0x00400031, 0x20c01fbd, 0x1069002c, 0x02100001 },
+ { 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
+ { 0x00600040, 0x20e077bd, 0x008d0080, 0x008d40a0 },
+ { 0x00600041, 0x202077be, 0x008d00e0, 0x000000c0 },
+ { 0x00600040, 0x20e077bd, 0x008d00a0, 0x008d4060 },
+ { 0x00600041, 0x204077be, 0x008d00e0, 0x000000c8 },
+ { 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_wm_ca.g4b.gen5 b/src/render_program/exa_wm_ca.g4b.gen5
new file mode 100644
index 0000000..372e8b2
--- /dev/null
+++ b/src/render_program/exa_wm_ca.g4b.gen5
@@ -0,0 +1,4 @@
+ { 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d02c0 },
+ { 0x00802041, 0x220077bd, 0x008d0200, 0x008d0300 },
+ { 0x00802041, 0x224077bd, 0x008d0240, 0x008d0340 },
+ { 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 },
diff --git a/src/render_program/exa_wm_ca_srcalpha.g4b.gen5 b/src/render_program/exa_wm_ca_srcalpha.g4b.gen5
new file mode 100644
index 0000000..963d676
--- /dev/null
+++ b/src/render_program/exa_wm_ca_srcalpha.g4b.gen5
@@ -0,0 +1,4 @@
+ { 0x00802041, 0x21c077bd, 0x008d02c0, 0x008d0280 },
+ { 0x00802041, 0x220077bd, 0x008d0300, 0x008d0280 },
+ { 0x00802041, 0x224077bd, 0x008d0340, 0x008d0280 },
+ { 0x00802041, 0x228077bd, 0x008d0380, 0x008d0280 },
diff --git a/src/render_program/exa_wm_mask_affine.g4b.gen5 b/src/render_program/exa_wm_mask_affine.g4b.gen5
new file mode 100644
index 0000000..14a5451
--- /dev/null
+++ b/src/render_program/exa_wm_mask_affine.g4b.gen5
@@ -0,0 +1,8 @@
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x210077be, 0x008d03c0, 0x000000ac },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x214077be, 0x008d03c0, 0x000000bc },
diff --git a/src/render_program/exa_wm_mask_projective.g4b.gen5 b/src/render_program/exa_wm_mask_projective.g4b.gen5
new file mode 100644
index 0000000..c357459
--- /dev/null
+++ b/src/render_program/exa_wm_mask_projective.g4b.gen5
@@ -0,0 +1,16 @@
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000c0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000c4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000cc },
+ { 0x00600031, 0x21801fbd, 0x108d03c0, 0x02100001 },
+ { 0x00600031, 0x21a01fbd, 0x108d03e0, 0x02100001 },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000ac },
+ { 0x00802041, 0x210077be, 0x008d03c0, 0x008d0180 },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000bc },
+ { 0x00802041, 0x214077be, 0x008d03c0, 0x008d0180 },
diff --git a/src/render_program/exa_wm_mask_sample_a.g4b.gen5 b/src/render_program/exa_wm_mask_sample_a.g4b.gen5
new file mode 100644
index 0000000..d9740ac
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_a.g4b.gen5
@@ -0,0 +1,2 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
+ { 0x07800031, 0x23801d29, 0x208d0000, 0x0a2a0102 },
diff --git a/src/render_program/exa_wm_mask_sample_argb.g4b.gen5 b/src/render_program/exa_wm_mask_sample_argb.g4b.gen5
new file mode 100644
index 0000000..f0a6ddd
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_argb.g4b.gen5
@@ -0,0 +1,2 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
+ { 0x07800031, 0x22c01d29, 0x208d0000, 0x0a8a0102 },
diff --git a/src/render_program/exa_wm_noca.g4b.gen5 b/src/render_program/exa_wm_noca.g4b.gen5
new file mode 100644
index 0000000..1506334
--- /dev/null
+++ b/src/render_program/exa_wm_noca.g4b.gen5
@@ -0,0 +1,4 @@
+ { 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d0380 },
+ { 0x00802041, 0x220077bd, 0x008d0200, 0x008d0380 },
+ { 0x00802041, 0x224077bd, 0x008d0240, 0x008d0380 },
+ { 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 },
diff --git a/src/render_program/exa_wm_src_affine.g4b.gen5 b/src/render_program/exa_wm_src_affine.g4b.gen5
new file mode 100644
index 0000000..d30da87
--- /dev/null
+++ b/src/render_program/exa_wm_src_affine.g4b.gen5
@@ -0,0 +1,8 @@
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x204077be, 0x008d03c0, 0x0000006c },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x208077be, 0x008d03c0, 0x0000007c },
diff --git a/src/render_program/exa_wm_src_projective.g4b.gen5 b/src/render_program/exa_wm_src_projective.g4b.gen5
new file mode 100644
index 0000000..ae3db8c
--- /dev/null
+++ b/src/render_program/exa_wm_src_projective.g4b.gen5
@@ -0,0 +1,16 @@
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000080 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000084 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000008c },
+ { 0x00600031, 0x21801fbd, 0x108d03c0, 0x02100001 },
+ { 0x00600031, 0x21a01fbd, 0x108d03e0, 0x02100001 },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000006c },
+ { 0x00802041, 0x204077be, 0x008d03c0, 0x008d0180 },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000007c },
+ { 0x00802041, 0x208077be, 0x008d03c0, 0x008d0180 },
diff --git a/src/render_program/exa_wm_src_sample_a.g4b.gen5 b/src/render_program/exa_wm_src_sample_a.g4b.gen5
new file mode 100644
index 0000000..8cd411c
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_a.g4b.gen5
@@ -0,0 +1,2 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
+ { 0x01800031, 0x22801d29, 0x208d0000, 0x0a2a0001 },
diff --git a/src/render_program/exa_wm_src_sample_argb.g4b.gen5 b/src/render_program/exa_wm_src_sample_argb.g4b.gen5
new file mode 100644
index 0000000..f8cb41e
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g4b.gen5
@@ -0,0 +1,2 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
+ { 0x01800031, 0x21c01d29, 0x208d0000, 0x0a8a0001 },
diff --git a/src/render_program/exa_wm_src_sample_planar.g4b.gen5 b/src/render_program/exa_wm_src_sample_planar.g4b.gen5
new file mode 100644
index 0000000..a381e68
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_planar.g4b.gen5
@@ -0,0 +1,4 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 },
+ { 0x01800031, 0x22001d29, 0x208d0000, 0x0a2a0001 },
+ { 0x01800031, 0x21c01d29, 0x208d0000, 0x0a2a0203 },
+ { 0x01800031, 0x22401d29, 0x208d0000, 0x0a2a0405 },
diff --git a/src/render_program/exa_wm_write.g4b.gen5 b/src/render_program/exa_wm_write.g4b.gen5
new file mode 100644
index 0000000..c40560f
--- /dev/null
+++ b/src/render_program/exa_wm_write.g4b.gen5
@@ -0,0 +1,18 @@
+ { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 },
+ { 0x00600001, 0x206003be, 0x008d0200, 0x00000000 },
+ { 0x00600001, 0x208003be, 0x008d0240, 0x00000000 },
+ { 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 },
+ { 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 },
+ { 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 },
+ { 0x00601001, 0x210003be, 0x008d0260, 0x00000000 },
+ { 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 },
+ { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
+ { 0x00800031, 0x24001d28, 0x548d0000, 0x94084800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_wm_xy.g4b.gen5 b/src/render_program/exa_wm_xy.g4b.gen5
new file mode 100644
index 0000000..327fc29
--- /dev/null
+++ b/src/render_program/exa_wm_xy.g4b.gen5
@@ -0,0 +1,4 @@
+ { 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 },
+ { 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 },
+ { 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 },
+ { 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 },
diff --git a/src/render_program/exa_wm_yuv_rgb.g4b.gen5 b/src/render_program/exa_wm_yuv_rgb.g4b.gen5
new file mode 100644
index 0000000..01f6e2b
--- /dev/null
+++ b/src/render_program/exa_wm_yuv_rgb.g4b.gen5
@@ -0,0 +1,12 @@
+ { 0x00802040, 0x23007fbd, 0x008d0200, 0xbd808081 },
+ { 0x00802041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 },
+ { 0x00802040, 0x22c07fbd, 0x008d01c0, 0xbf008084 },
+ { 0x00802040, 0x23407fbd, 0x008d0240, 0xbf008084 },
+ { 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 },
+ { 0x80802048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba },
+ { 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 },
+ { 0x00802048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 },
+ { 0x80802048, 0x22007fbd, 0x008d0340, 0xbec8b439 },
+ { 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 },
+ { 0x80802048, 0x22407fbd, 0x008d0340, 0x40011687 },
+ { 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 },
diff --git a/src/render_program/packed_yuv_sf.g4b.gen5 b/src/render_program/packed_yuv_sf.g4b.gen5
new file mode 100644
index 0000000..d4d235a
--- /dev/null
+++ b/src/render_program/packed_yuv_sf.g4b.gen5
@@ -0,0 +1,17 @@
+ { 0x00000031, 0x20c01fbd, 0x1000002c, 0x02100081 },
+ { 0x00000031, 0x20c41fbd, 0x10000034, 0x02100081 },
+ { 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
+ { 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
+ { 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
+ { 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
+ { 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
+ { 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
+ { 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/packed_yuv_wm.g4b.gen5 b/src/render_program/packed_yuv_wm.g4b.gen5
new file mode 100644
index 0000000..43fefa6
--- /dev/null
+++ b/src/render_program/packed_yuv_wm.g4b.gen5
@@ -0,0 +1,79 @@
+ { 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
+ { 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
+ { 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
+ { 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
+ { 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
+ { 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
+ { 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
+ { 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
+ { 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
+ { 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
+ { 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
+ { 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
+ { 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
+ { 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
+ { 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
+ { 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
+ { 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
+ { 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
+ { 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
+ { 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
+ { 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
+ { 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
+ { 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
+ { 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
+ { 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
+ { 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
+ { 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
+ { 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
+ { 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
+ { 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
+ { 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
+ { 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
+ { 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
+ { 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
+ { 0x00600041, 0x208077bd, 0x008d0080, 0x00000060 },
+ { 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000060 },
+ { 0x00600040, 0x208077bd, 0x008d0080, 0x0000006c },
+ { 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000006c },
+ { 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
+ { 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
+ { 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000074 },
+ { 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000074 },
+ { 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000007c },
+ { 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000007c },
+ { 0x00600001, 0x202003be, 0x008d0080, 0x00000000 },
+ { 0x00600001, 0x204003be, 0x008d00a0, 0x00000000 },
+ { 0x00600001, 0x206003be, 0x008d00c0, 0x00000000 },
+ { 0x00600001, 0x208003be, 0x008d00e0, 0x00000000 },
+ { 0x00800031, 0x21801d29, 0x208d0000, 0x0a8a0001 },
+ { 0x00802040, 0x21c07fbd, 0x008d01c0, 0xbd808081 },
+ { 0x00802041, 0x21c07fbd, 0x008d01c0, 0x3f94fdf4 },
+ { 0x00802040, 0x21807fbd, 0x008d0180, 0xbf008084 },
+ { 0x00802040, 0x22007fbd, 0x008d0200, 0xbf008084 },
+ { 0x00600041, 0x20007fbc, 0x008d0180, 0x3fcc49ba },
+ { 0x80600048, 0x20407fbe, 0x008d01c0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d01a0, 0x3fcc49ba },
+ { 0x80600048, 0x20c07fbe, 0x008d01e0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d0180, 0xbf5020c5 },
+ { 0x00600048, 0x20007fbc, 0x008d0200, 0xbec8b439 },
+ { 0x80600048, 0x20607fbe, 0x008d01c0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d01a0, 0xbf5020c5 },
+ { 0x00600048, 0x20007fbc, 0x008d0220, 0xbec8b439 },
+ { 0x80600048, 0x20e07fbe, 0x008d01e0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d0200, 0x40011687 },
+ { 0x80600048, 0x20807fbe, 0x008d01c0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d0220, 0x40011687 },
+ { 0x80600048, 0x21007fbe, 0x008d01e0, 0x3f800000 },
+ { 0x00600001, 0x20a003fe, 0x00000000, 0x3f800000 },
+ { 0x00600001, 0x212003fe, 0x00000000, 0x3f800000 },
+ { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
+ { 0x00800031, 0x24001d28, 0x548d0000, 0x94084800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
commit 488acc4595bb7f40130afcb8bcb05656ff3ae82c
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Thu Jun 25 14:05:40 2009 +0800
Move shader programs under its own subdirectory
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/configure.ac b/configure.ac
index 0864d7c..397336c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -195,4 +195,5 @@ AC_OUTPUT([
src/sil164/Makefile
src/tfp410/Makefile
man/Makefile
+ src/render_program/Makefile
])
diff --git a/src/Makefile.am b/src/Makefile.am
index 6496dec..ea52fcb 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -18,7 +18,7 @@
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 reg_dumper
+SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 reg_dumper render_program
# this is obnoxious:
# -module lets us name the module exactly how we want
@@ -27,7 +27,7 @@ SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 reg_dumper
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \
- @PCIACCESS_CFLAGS@ -I$(top_srcdir)/uxa
+ @PCIACCESS_CFLAGS@ -I$(top_srcdir)/uxa -I$(top_srcdir)/src/render_program
intel_drv_la_LTLIBRARIES = intel_drv.la
intel_drv_la_LDFLAGS = -module -avoid-version
@@ -110,75 +110,11 @@ intel_drv_la_SOURCES = \
i965_render.c \
drmmode_display.c
-INTEL_G4A = \
- packed_yuv_sf.g4a \
- packed_yuv_wm.g4a \
- exa_sf.g4a \
- exa_sf_mask.g4a \
- exa_wm_src_affine.g4a \
- exa_wm_src_projective.g4a \
- exa_wm_src_sample_argb.g4a \
- exa_wm_src_sample_a.g4a \
- exa_wm_src_sample_planar.g4a \
- exa_wm_mask_affine.g4a \
- exa_wm_mask_projective.g4a \
- exa_wm_mask_sample_argb.g4a \
- exa_wm_mask_sample_a.g4a \
- exa_wm_noca.g4a \
- exa_wm_ca.g4a \
- exa_wm_ca_srcalpha.g4a \
- exa_wm_write.g4a \
- exa_wm_yuv_rgb.g4a \
- exa_wm_xy.g4a
-
-INTEL_G4I = \
- exa_wm.g4i \
- exa_wm_affine.g4i \
- exa_wm_projective.g4i
-
-INTEL_G4B = \
- packed_yuv_sf.g4b \
- packed_yuv_wm.g4b \
- exa_sf.g4b \
- exa_sf_mask.g4b \
- exa_wm_src_affine.g4b \
- exa_wm_src_projective.g4b \
- exa_wm_src_sample_argb.g4b \
- exa_wm_src_sample_a.g4b \
- exa_wm_src_sample_planar.g4b \
- exa_wm_mask_affine.g4b \
- exa_wm_mask_projective.g4b \
- exa_wm_mask_sample_argb.g4b \
- exa_wm_mask_sample_a.g4b \
- exa_wm_noca.g4b \
- exa_wm_ca.g4b \
- exa_wm_ca_srcalpha.g4b \
- exa_wm_write.g4b \
- exa_wm_yuv_rgb.g4b \
- exa_wm_xy.g4b
-
EXTRA_DIST = \
$(XMODE_SRCS) \
- $(INTEL_G4A) \
- $(INTEL_G4I) \
- $(INTEL_G4B) \
$(INTEL_DRI_SRCS) \
$(INTEL_XVMC_SRCS)
-if HAVE_GEN4ASM
-
-SUFFIXES = .g4a .g4b
-.g4a.g4b:
- m4 -I$(srcdir) -s $< > $*.g4m && intel-gen4asm -o $@ $*.g4m && rm $*.g4m
-
-$(INTEL_G4B): $(INTEL_G4I)
-
-BUILT_SOURCES= $(INTEL_G4B)
-
-clean-local:
- -rm -f $(INTEL_G4B)
-endif
-
if DRI
intel_drv_la_SOURCES += \
$(INTEL_DRI_SRCS)
diff --git a/src/exa_sf.g4a b/src/exa_sf.g4a
deleted file mode 100644
index 3e660ac..0000000
--- a/src/exa_sf.g4a
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Keith Packard <keithp at keithp.com>
- * Eric Anholt <eric at anholt.net>
- *
- */
-
-/*
- * Inputs (note all sub-register addresses are bytes, not float indices)
- *
- * Note that the vertices will have been reordered:
- *
- * V0 is topmost (leftmost among topmost) (upper left)
- * V1 is next clockwise (lower right)
- * V2 is remaining (lower left)
- *
- * V0 ...................... XX
- * | .
- * | .
- * | .
- * V2------------------------V1
- *
- * G0 thread state -- just pass along
- *
- * G1 and G2 are fixed by SF spec
- *
- * G1.0 reserved
- * G1.4 Provoking vertex
- * G1.8 Determinant
- * G1.12 X1 - X0
- * G1.16 X2 - X0
- * G1.20 Y1 - Y0
- * G1.24 Y2 - Y0
- * G1.30 reserved
- *
- * G2.0 Z0
- * G2.4 1/W0
- * G2.8 Z1
- * G2.12 1/W1
- * G2.16 Z2
- * G2.20 1/W2
- * G2.24 reserved
- * G2.30 reserved
- *
- * G3 is V0 Vertex Attribute Data from URB (upper left)
- *
- * G3.0 u0
- * G3.4 v0
- *
- * G4 is V1 Vertex Attribute Data from URB (lower right)
- *
- * G4.0 u1
- * G4.4 v1
- *
- * G5 is V2 Vertex Attribute Data from URB (lower left)
- *
- */
-
-/* Compute inverses of the input deltas */
-send (4) 0 g6<1>F g1.12<4,4,1>F math inv mlen 1 rlen 1 { align1 };
-
-/* texture location at V0 */
-mov (4) m3<1>F g3<4,4,1>F { align1 };
-
-/* compute V1 - V2 (motion in X) for texture coordinates */
-add (4) g7<1>F g4<4,4,1>F -g5<4,4,1>F { align1 };
-
-/* multiply by 1/dx */
-mul (4) m1<1>F g7<4,4,1>F g6.0<0,1,0>F { align1 };
-
-/* Compute V2 - V0 (motion in Y) for texture coordinates */
-add (4) g7<1>F g5<4,4,1>F -g3<4,4,1>F { align1 };
-
-/* multiply by 1/dy */
-mul (4) m2<1>F g7<4,4,1>F g6.8<0,1,0>F {align1 };
-
-/* and we're done */
-send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
diff --git a/src/exa_sf.g4b b/src/exa_sf.g4b
deleted file mode 100644
index 223c9c9..0000000
--- a/src/exa_sf.g4b
+++ /dev/null
@@ -1,15 +0,0 @@
- { 0x00400031, 0x20c01fbd, 0x0069002c, 0x01110001 },
- { 0x00400001, 0x206003be, 0x00690060, 0x00000000 },
- { 0x00400040, 0x20e077bd, 0x00690080, 0x006940a0 },
- { 0x00400041, 0x202077be, 0x006900e0, 0x000000c0 },
- { 0x00400040, 0x20e077bd, 0x006900a0, 0x00694060 },
- { 0x00400041, 0x204077be, 0x006900e0, 0x000000c8 },
- { 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/exa_sf_mask.g4a b/src/exa_sf_mask.g4a
deleted file mode 100644
index 5078d01..0000000
--- a/src/exa_sf_mask.g4a
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Keith Packard <keithp at keithp.com>
- * Eric Anholt <eric at anholt.net>
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- */
-
-/*
- * Inputs (note all sub-register addresses are bytes, not float indices)
- *
- * Note that the vertices will have been reordered:
- *
- * V0 is topmost (leftmost among topmost) (upper left)
- * V1 is next clockwise (lower right)
- * V2 is remaining (lower left)
- *
- * V0 ...................... XX
- * | .
- * | .
- * | .
- * V2------------------------V1
- *
- * G0 thread state -- just pass along
- *
- * G1 and G2 are fixed by SF spec
- *
- * G1.0 reserved
- * G1.4 Provoking vertex
- * G1.8 Determinant
- * G1.12 X1 - X0
- * G1.16 X2 - X0
- * G1.20 Y1 - Y0
- * G1.24 Y2 - Y0
- * G1.30 reserved
- *
- * G2.0 Z0
- * G2.4 1/W0
- * G2.8 Z1
- * G2.12 1/W1
- * G2.16 Z2
- * G2.20 1/W2
- * G2.24 reserved
- * G2.30 reserved
- *
- * G3 is V0 Vertex Attribute Data from URB (upper left)
- *
- * G3.0 u0
- * G3.4 v0
- *
- * G4 is V1 Vertex Attribute Data from URB (lower right)
- *
- * G4.0 u1
- * G4.4 v1
- *
- * G5 is V2 Vertex Attribute Data from URB (lower left)
- *
- */
-
-/* Compute inverses of the input deltas */
-send (4) 0 g6<1>F g1.12<4,4,1>F math inv mlen 1 rlen 1 { align1 };
-
-/* texture location at V0 */
-mov (8) m3<1>F g3<8,8,1>F { align1 };
-
-/* compute V1 - V2 (motion in X) for texture coordinates */
-add (8) g7<1>F g4<8,8,1>F -g5<8,8,1>F { align1 };
-
-/* multiply by 1/dx */
-mul (8) m1<1>F g7<8,8,1>F g6.0<0,1,0>F { align1 };
-
-/* Compute V2 - V0 (motion in Y) for texture coordinates */
-add (8) g7<1>F g5<8,8,1>F -g3<8,8,1>F { align1 };
-
-/* multiply by 1/dy */
-mul (8) m2<1>F g7<8,8,1>F g6.8<0,1,0>F {align1 };
-
-/* and we're done */
-send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
diff --git a/src/exa_sf_mask.g4b b/src/exa_sf_mask.g4b
deleted file mode 100644
index be0a77b..0000000
--- a/src/exa_sf_mask.g4b
+++ /dev/null
@@ -1,15 +0,0 @@
- { 0x00400031, 0x20c01fbd, 0x0069002c, 0x01110001 },
- { 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
- { 0x00600040, 0x20e077bd, 0x008d0080, 0x008d40a0 },
- { 0x00600041, 0x202077be, 0x008d00e0, 0x000000c0 },
- { 0x00600040, 0x20e077bd, 0x008d00a0, 0x008d4060 },
- { 0x00600041, 0x204077be, 0x008d00e0, 0x000000c8 },
- { 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/exa_wm.g4i b/src/exa_wm.g4i
deleted file mode 100644
index 5d3d45b..0000000
--- a/src/exa_wm.g4i
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/*
- * Input parameters
- */
-
-/* Destination X/Y */
-define(`dst_x_uw', `g1.8<2,4,0>UW')
-define(`dst_y_uw', `g1.10<2,4,0>UW')
-define(`screen_x0', `g1.0<0,1,0>F')
-define(`screen_y0', `g1.4<0,1,0>F')
-
-/* Source transformation parameters */
-define(`src_du_dx', `g3.0<0,1,0>F')
-define(`src_du_dy', `g3.4<0,1,0>F')
-define(`src_uo', `g3.12<0,1,0>F')
-define(`src_dv_dx', `g3.16<0,1,0>F')
-define(`src_dv_dy', `g3.20<0,1,0>F')
-define(`src_vo', `g3.28<0,1,0>F')
-define(`src_dw_dx', `g4.0<0,1,0>F')
-define(`src_dw_dy', `g4.4<0,1,0>F')
-define(`src_wo', `g4.12<0,1,0>F')
-
-define(`mask_du_dx', `g5.0<0,1,0>F')
-define(`mask_du_dy', `g5.4<0,1,0>F')
-define(`mask_uo', `g5.12<0,1,0>F')
-define(`mask_dv_dx', `g5.16<0,1,0>F')
-define(`mask_dv_dy', `g5.20<0,1,0>F')
-define(`mask_vo', `g5.28<0,1,0>F')
-define(`mask_dw_dx', `g6.0<0,1,0>F')
-define(`mask_dw_dy', `g6.4<0,1,0>F')
-define(`mask_wo', `g6.12<0,1,0>F')
-
-/*
- * Local variables. Pairs must be aligned on even reg boundry
- */
-
-/* this holds the X dest coordinates */
-define(`dst_x', `g8')
-define(`dst_x_0', `dst_x')
-define(`dst_x_1', `g9')
-
-/* this holds the Y dest coordinates */
-define(`dst_y', `g10')
-define(`dst_y_0', `dst_y')
-define(`dst_y_1', `g11')
-
-/* When computing x * dn/dx, use this */
-define(`temp_x', `g30')
-define(`temp_x_0', `temp_x')
-define(`temp_x_1', `g31')
-
-/* When computing y * dn/dy, use this */
-define(`temp_y', `g28')
-define(`temp_y_0', temp_y)
-define(`temp_y_1', `g29')
-
-/* when loading x/y, use these to hold them in UW format */
-define(`temp_x_uw', temp_x)
-define(`temp_y_uw', temp_y)
-
-/* compute source and mask u/v to this pair to send to sampler */
-define(`src_msg', `m1')
-define(`src_msg_ind',`1')
-define(`src_u', `m2')
-define(`src_v', `m4')
-define(`src_w', `g12')
-define(`src_w_0', `src_w')
-define(`src_w_1', `g13')
-
-define(`mask_msg', `m7')
-define(`mask_msg_ind',`7')
-define(`mask_u', `m8')
-define(`mask_v', `m10')
-define(`mask_w', `src_w')
-define(`mask_w_0', `src_w_0')
-define(`mask_w_1', `src_w_1')
-
-/* sample src to these registers */
-define(`src_sample_base', `g14')
-
-define(`src_sample_r', `g14')
-define(`src_sample_r_01', `g14')
-define(`src_sample_r_23', `g15')
-
-define(`src_sample_g', `g16')
-define(`src_sample_g_01', `g16')
-define(`src_sample_g_23', `g17')
-
-define(`src_sample_b', `g18')
-define(`src_sample_b_01', `g18')
-define(`src_sample_b_23', `g19')
-
-define(`src_sample_a', `g20')
-define(`src_sample_a_01', `g20')
-define(`src_sample_a_23', `g21')
-
-/* sample mask to these registers */
-define(`mask_sample_base', `g22')
-
-define(`mask_sample_r', `g22')
-define(`mask_sample_r_01', `g22')
-define(`mask_sample_r_23', `g23')
-
-define(`mask_sample_g', `g24')
-define(`mask_sample_g_01', `g24')
-define(`mask_sample_g_23', `g25')
-
-define(`mask_sample_b', `g26')
-define(`mask_sample_b_01', `g26')
-define(`mask_sample_b_23', `g27')
-
-define(`mask_sample_a', `g28')
-define(`mask_sample_a_01', `g28')
-define(`mask_sample_a_23', `g29')
-
-/* data port SIMD16 send registers */
-
-define(`data_port_msg_0', `m0')
-define(`data_port_msg_0_ind', `0')
-define(`data_port_msg_1', `m1')
-define(`data_port_r_01', `m2')
-define(`data_port_g_01', `m3')
-define(`data_port_b_01', `m4')
-define(`data_port_a_01', `m5')
-
-define(`data_port_r_23', `m6')
-define(`data_port_g_23', `m7')
-define(`data_port_b_23', `m8')
-define(`data_port_a_23', `m9')
-
diff --git a/src/exa_wm_affine.g4i b/src/exa_wm_affine.g4i
deleted file mode 100644
index e72656b..0000000
--- a/src/exa_wm_affine.g4i
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/*
- * Fragment to compute src u/v values under an affine transform
- */
-
-/********** Compute u *************/
-
-mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
-mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
-add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
-add (16) u<1>F temp_x<8,8,1>F uo { compr align1 };
-
-/********** Compute v *************/
-
-mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
-mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
-add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
-add (16) v<1>F temp_x<8,8,1>F vo { compr align1 };
diff --git a/src/exa_wm_ca.g4a b/src/exa_wm_ca.g4a
deleted file mode 100644
index 5d982b3..0000000
--- a/src/exa_wm_ca.g4a
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/*
- * Composite src and mask together, no component alpha
- */
-
-include(`exa_wm.g4i')
-
-/* mul mask rgba channels to src */
-mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_r_01<8,8,1>F { compr align1 };
-mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_g_01<8,8,1>F { compr align1 };
-mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_b_01<8,8,1>F { compr align1 };
-mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
diff --git a/src/exa_wm_ca.g4b b/src/exa_wm_ca.g4b
deleted file mode 100644
index 372e8b2..0000000
--- a/src/exa_wm_ca.g4b
+++ /dev/null
@@ -1,4 +0,0 @@
- { 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d02c0 },
- { 0x00802041, 0x220077bd, 0x008d0200, 0x008d0300 },
- { 0x00802041, 0x224077bd, 0x008d0240, 0x008d0340 },
- { 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 },
diff --git a/src/exa_wm_ca_srcalpha.g4a b/src/exa_wm_ca_srcalpha.g4a
deleted file mode 100644
index d1f847f..0000000
--- a/src/exa_wm_ca_srcalpha.g4a
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/*
- * Composite src and mask together, no component alpha
- */
-
-include(`exa_wm.g4i')
-
-mul (16) src_sample_r_01<1>F mask_sample_r_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 };
-mul (16) src_sample_g_01<1>F mask_sample_g_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 };
-mul (16) src_sample_b_01<1>F mask_sample_b_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 };
-mul (16) src_sample_a_01<1>F mask_sample_a_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 };
diff --git a/src/exa_wm_ca_srcalpha.g4b b/src/exa_wm_ca_srcalpha.g4b
deleted file mode 100644
index 963d676..0000000
--- a/src/exa_wm_ca_srcalpha.g4b
+++ /dev/null
@@ -1,4 +0,0 @@
- { 0x00802041, 0x21c077bd, 0x008d02c0, 0x008d0280 },
- { 0x00802041, 0x220077bd, 0x008d0300, 0x008d0280 },
- { 0x00802041, 0x224077bd, 0x008d0340, 0x008d0280 },
- { 0x00802041, 0x228077bd, 0x008d0380, 0x008d0280 },
diff --git a/src/exa_wm_mask_affine.g4a b/src/exa_wm_mask_affine.g4a
deleted file mode 100644
index 9c52d2f..0000000
--- a/src/exa_wm_mask_affine.g4a
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-include(`exa_wm.g4i')
-
-define(`du_dx', `mask_du_dx')
-define(`du_dy', `mask_du_dy')
-define(`uo', `mask_uo')
-
-define(`dv_dx', `mask_dv_dx')
-define(`dv_dy', `mask_dv_dy')
-define(`vo', `mask_vo')
-
-define(`u', `mask_u')
-define(`v', `mask_v')
-
-include(`exa_wm_affine.g4i')
diff --git a/src/exa_wm_mask_affine.g4b b/src/exa_wm_mask_affine.g4b
deleted file mode 100644
index 14a5451..0000000
--- a/src/exa_wm_mask_affine.g4b
+++ /dev/null
@@ -1,8 +0,0 @@
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x210077be, 0x008d03c0, 0x000000ac },
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x214077be, 0x008d03c0, 0x000000bc },
diff --git a/src/exa_wm_mask_projective.g4a b/src/exa_wm_mask_projective.g4a
deleted file mode 100644
index 9acaace..0000000
--- a/src/exa_wm_mask_projective.g4a
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-include(`exa_wm.g4i')
-
-define(`du_dx', `mask_du_dx')
-define(`du_dy', `mask_du_dy')
-define(`uo', `mask_uo')
-
-define(`dv_dx', `mask_dv_dx')
-define(`dv_dy', `mask_dv_dy')
-define(`vo', `mask_vo')
-
-define(`dw_dx', `mask_dw_dx')
-define(`dw_dy', `mask_dw_dy')
-define(`wo', `mask_wo')
-
-define(`u', `mask_u')
-define(`v', `mask_v')
-define(`w', `mask_w')
-
-define(`u_0', `mask_u_0')
-define(`v_0', `mask_v_0')
-define(`u_1', `mask_u_1')
-define(`v_1', `mask_v_1')
-define(`w_0', `mask_w_0')
-define(`w_1', `mask_w_1')
-
-include(`exa_wm_projective.g4i')
diff --git a/src/exa_wm_mask_projective.g4b b/src/exa_wm_mask_projective.g4b
deleted file mode 100644
index 78cb9ae..0000000
--- a/src/exa_wm_mask_projective.g4b
+++ /dev/null
@@ -1,16 +0,0 @@
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000c0 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x000000c4 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000cc },
- { 0x00600031, 0x21801fbd, 0x008d03c0, 0x01110001 },
- { 0x00600031, 0x21a01fbd, 0x008d03e0, 0x01110001 },
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000ac },
- { 0x00802041, 0x210077be, 0x008d03c0, 0x008d0180 },
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000bc },
- { 0x00802041, 0x214077be, 0x008d03c0, 0x008d0180 },
diff --git a/src/exa_wm_mask_sample_a.g4a b/src/exa_wm_mask_sample_a.g4a
deleted file mode 100644
index bbb19d7..0000000
--- a/src/exa_wm_mask_sample_a.g4a
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/* Sample the mask surface */
-
-include(`exa_wm.g4i')
-
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* load only alpha */
-mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable };
-
-/* mask_msg will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-send (16) mask_msg_ind /* msg reg index */
- mask_sample_a_01<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
- sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
-
diff --git a/src/exa_wm_mask_sample_a.g4b b/src/exa_wm_mask_sample_a.g4b
deleted file mode 100644
index 018bd36..0000000
--- a/src/exa_wm_mask_sample_a.g4b
+++ /dev/null
@@ -1,2 +0,0 @@
- { 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
- { 0x07800031, 0x23801d29, 0x008d0000, 0x02520102 },
diff --git a/src/exa_wm_mask_sample_argb.g4a b/src/exa_wm_mask_sample_argb.g4a
deleted file mode 100644
index def4cfe..0000000
--- a/src/exa_wm_mask_sample_argb.g4a
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/* Sample the mask surface */
-
-include(`exa_wm.g4i')
-
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* load argb */
-mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable };
-
-/* mask_msg will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-send (16) mask_msg_ind /* msg reg index */
- mask_sample_base<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
- sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
-
diff --git a/src/exa_wm_mask_sample_argb.g4b b/src/exa_wm_mask_sample_argb.g4b
deleted file mode 100644
index b159cba..0000000
--- a/src/exa_wm_mask_sample_argb.g4b
+++ /dev/null
@@ -1,2 +0,0 @@
- { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
- { 0x07800031, 0x22c01d29, 0x008d0000, 0x02580102 },
diff --git a/src/exa_wm_noca.g4a b/src/exa_wm_noca.g4a
deleted file mode 100644
index d0d60fa..0000000
--- a/src/exa_wm_noca.g4a
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/*
- * Composite src and mask together, no component alpha
- */
-
-include(`exa_wm.g4i')
-/* mul mask's alpha channel to src */
-
-mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
-mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
-mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
-mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
diff --git a/src/exa_wm_noca.g4b b/src/exa_wm_noca.g4b
deleted file mode 100644
index 1506334..0000000
--- a/src/exa_wm_noca.g4b
+++ /dev/null
@@ -1,4 +0,0 @@
- { 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d0380 },
- { 0x00802041, 0x220077bd, 0x008d0200, 0x008d0380 },
- { 0x00802041, 0x224077bd, 0x008d0240, 0x008d0380 },
- { 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 },
diff --git a/src/exa_wm_nomask.g4a b/src/exa_wm_nomask.g4a
deleted file mode 100644
index eb535fe..0000000
--- a/src/exa_wm_nomask.g4a
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- */
-
-/*
- * This's for exa composite operation in no mask picture case.
- * The simplest case is just sending what src picture has to dst picture.
- */
-
-/* I think this should be same as in g4a program for texture video,
- as we also use 16-pixel dispatch. and SF scale in g3 is useful for us. */
-
-/* The initial payload of the thread is always g0.
- * WM_URB (incoming URB entries) is g3
- * X0_R is g4
- * X1_R is g5
- * Y0_R is g6
- * Y1_R is g7
- */
-
-
-/* Load X and Y coordinates and compute per-pixel coordinates */
-add (16) g4<1>UW g1.8<2,4,0>UW 0x10101010V { align1 };
-add (16) g6<1>UW g1.10<2,4,0>UW 0x11001100V { align1 };
-
- /* Now, map these screen space coordinates into texture coordinates. */
-
- /* subtract screen-space X origin of vertex 0. */
-add (16) g12<1>F g4<8,8,1>UW -g1.0<0,1,0>F { compr align1 };
-
- /* subtract screen-space Y origin of vertex 0. */
-add (16) g16<1>F g6<8,8,1>UW -g1.4<0,1,0>F { compr align1 };
-
- /* g8/g9 = X * du/dx */
-mul (16) g8<1>F g12<8,8,1>F g3.0<0,1,0>F { compr align1 };
-
- /* g10/g11 = Y * du/dy */
-mul (16) g10<1>F g16<8,8,1>F g3.4<0,1,0>F { compr align1 };
-
- /* g8/g9 = X du/dx + Y du/dy */
-add (16) g8<1>F g8<8,8,1>F g10<8,8,1>F { compr align1 };
-
- /* m1/m2 = g8/g9 + uo */
-add (16) m1<1>F g8<8,8,1>F g3.12<0,1,0>F { compr align1 };
-
-
- /* g8/g9 = X * dv/dx */
-mul (16) g8<1>F g12<8,8,1>F g3.16<0,1,0>F { compr align1 };
-
- /* g10/g11 = Y * du/dy */
-mul (16) g10<1>F g16<8,8,1>F g3.20<0,1,0>F { compr align1 };
-
- /* g8/g9 = X du/dx + Y du/dy */
-add (16) g8<1>F g8<8,8,1>F g10<8,8,1>F { compr align1 };
-
- /* m3/m4 = g8/g9 + vo */
-add (16) m3<1>F g8<8,8,1>F g3.28<0,1,0>F { compr align1 };
-
-
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* m0 will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-send (16) 0 /* msg reg index */
- g12<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
- sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
-
-mov (8) g19<1>UD g19<8,8,1>UD { align1 }; /* wait sampler return */
-/* if we set up read-back reg correctly, emit dataport write 'send' cmd with EOT */
-
-/* m0, m1 are all direct passed by PS thread payload */
-mov (8) m1<1>F g1<8,8,1>F { align1 };
-
-/* prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2), then it's ready to write */
-/* g12 -> m2
- g13 -> m6
- g14 -> m3
- g15 -> m7
- g16 -> m4
- g17 -> m8
- g18 -> m5
- g19 -> m9
-*/
-mov (8) m2<1>F g12<8,8,1>F { align1 };
-mov (8) m3<1>F g14<8,8,1>F { align1 };
-mov (8) m4<1>F g16<8,8,1>F { align1 };
-mov (8) m5<1>F g18<8,8,1>F { align1 };
-mov (8) m6<1>F g13<8,8,1>F { align1 };
-mov (8) m7<1>F g15<8,8,1>F { align1 };
-mov (8) m8<1>F g17<8,8,1>F { align1 };
-mov (8) m9<1>F g19<8,8,1>F { align1 };
-
-/* m0, m1 are all direct passed by PS thread payload */
-mov (8) m1<1>UD g1<8,8,1>UD { align1 };
-
-/* write */
-send (16) 0 acc0<1>UW g0<8,8,1>UW write (
- 0, /* binding_table */
- 8, /* pixel scordboard clear, msg type simd16 single source */
- 4, /* render target write */
- 0 /* no write commit message */
- )
- mlen 10
- rlen 0
- { align1 EOT };
-
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
diff --git a/src/exa_wm_projective.g4i b/src/exa_wm_projective.g4i
deleted file mode 100644
index 7e2e0a8..0000000
--- a/src/exa_wm_projective.g4i
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/********** Compute w *************/
-
-mul (16) temp_x<1>F dst_x<8,8,1>F dw_dx { compr align1 };
-mul (16) temp_y<1>F dst_y<8,8,1>F dw_dy { compr align1 };
-add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
-add (16) temp_x<1>F temp_x<8,8,1>F wo { compr align1 };
-send (8) 0 w_0<1>F temp_x_0<8,8,1>F math inv mlen 1 rlen 1 { align1 };
-send (8) 0 w_1<1>F temp_x_1<8,8,1>F math inv mlen 1 rlen 1 { sechalf align1 };
-
-/********** Compute u *************/
-
-mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
-mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
-add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
-add (16) temp_x<1>F temp_x<8,8,1>F uo { compr align1 };
-mul (16) u<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
-
-/********** Compute v *************/
-
-mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
-mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
-add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
-add (16) temp_x<1>F temp_x<8,8,1>F vo { compr align1 };
-mul (16) v<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
diff --git a/src/exa_wm_src_affine.g4a b/src/exa_wm_src_affine.g4a
deleted file mode 100644
index 3194b5a..0000000
--- a/src/exa_wm_src_affine.g4a
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/*
- * Fragment to compute src u/v values under an affine transform
- */
-
-include(`exa_wm.g4i')
-
-define(`du_dx', `src_du_dx')
-define(`du_dy', `src_du_dy')
-define(`uo', `src_uo')
-
-define(`dv_dx', `src_dv_dx')
-define(`dv_dy', `src_dv_dy')
-define(`vo', `src_vo')
-
-define(`u', `src_u')
-define(`v', `src_v')
-
-include(`exa_wm_affine.g4i')
diff --git a/src/exa_wm_src_affine.g4b b/src/exa_wm_src_affine.g4b
deleted file mode 100644
index d30da87..0000000
--- a/src/exa_wm_src_affine.g4b
+++ /dev/null
@@ -1,8 +0,0 @@
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x204077be, 0x008d03c0, 0x0000006c },
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x208077be, 0x008d03c0, 0x0000007c },
diff --git a/src/exa_wm_src_projective.g4a b/src/exa_wm_src_projective.g4a
deleted file mode 100644
index 16c9cd5..0000000
--- a/src/exa_wm_src_projective.g4a
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-
-include(`exa_wm.g4i')
-define(`du_dx', `src_du_dx')
-define(`du_dy', `src_du_dy')
-define(`uo', `src_uo')
-define(`dv_dx', `src_dv_dx')
-define(`dv_dy', `src_dv_dy')
-define(`vo', `src_vo')
-define(`dw_dx', `src_dw_dx')
-define(`dw_dy', `src_dw_dy')
-define(`wo', `src_wo')
-define(`u', `src_u')
-define(`v', `src_v')
-define(`w', `src_w')
-define(`u_0', `src_u_0')
-define(`v_0', `src_v_0')
-define(`u_1', `src_u_1')
-define(`v_1', `src_v_1')
-define(`w_0', `src_w_0')
-define(`w_1', `src_w_1')
-
-include(`exa_wm_projective.g4i')
diff --git a/src/exa_wm_src_projective.g4b b/src/exa_wm_src_projective.g4b
deleted file mode 100644
index 198bab3..0000000
--- a/src/exa_wm_src_projective.g4b
+++ /dev/null
@@ -1,16 +0,0 @@
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000080 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x00000084 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000008c },
- { 0x00600031, 0x21801fbd, 0x008d03c0, 0x01110001 },
- { 0x00600031, 0x21a01fbd, 0x008d03e0, 0x01110001 },
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000006c },
- { 0x00802041, 0x204077be, 0x008d03c0, 0x008d0180 },
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000007c },
- { 0x00802041, 0x208077be, 0x008d03c0, 0x008d0180 },
diff --git a/src/exa_wm_src_sample_a.g4a b/src/exa_wm_src_sample_a.g4a
deleted file mode 100644
index 552aaee..0000000
--- a/src/exa_wm_src_sample_a.g4a
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/* Sample the src surface */
-
-include(`exa_wm.g4i')
-
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* load alpha */
-mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable };
-
-/* src_msg will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-send (16) src_msg_ind /* msg reg index */
- src_sample_a_01<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
- sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/exa_wm_src_sample_a.g4b b/src/exa_wm_src_sample_a.g4b
deleted file mode 100644
index ce8650a..0000000
--- a/src/exa_wm_src_sample_a.g4b
+++ /dev/null
@@ -1,2 +0,0 @@
- { 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
- { 0x01800031, 0x22801d29, 0x008d0000, 0x02520001 },
diff --git a/src/exa_wm_src_sample_argb.g4a b/src/exa_wm_src_sample_argb.g4a
deleted file mode 100644
index c20f53f..0000000
--- a/src/exa_wm_src_sample_argb.g4a
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/* Sample the src surface */
-
-include(`exa_wm.g4i')
-
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* load argb */
-mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable };
-
-/* src_msg will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-send (16) src_msg_ind /* msg reg index */
- src_sample_base<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
- sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/exa_wm_src_sample_argb.g4b b/src/exa_wm_src_sample_argb.g4b
deleted file mode 100644
index c5b9274..0000000
--- a/src/exa_wm_src_sample_argb.g4b
+++ /dev/null
@@ -1,2 +0,0 @@
- { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
- { 0x01800031, 0x21c01d29, 0x008d0000, 0x02580001 },
diff --git a/src/exa_wm_src_sample_planar.g4a b/src/exa_wm_src_sample_planar.g4a
deleted file mode 100644
index ca77b48..0000000
--- a/src/exa_wm_src_sample_planar.g4a
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/* Sample the src surface in planar format */
-
-include(`exa_wm.g4i')
-
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* load r */
-mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable };
-
-/* src_msg will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-
-/* sample Y */
-send (16) src_msg_ind /* msg reg index */
- src_sample_g<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
- sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
-
-/* sample U (Cr) */
-send (16) src_msg_ind /* msg reg index */
- src_sample_r<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
- sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
-
-/* sample V (Cb) */
-send (16) src_msg_ind /* msg reg index */
- src_sample_b<1>UW /* readback */
- g0<8,8,1>UW /* copy to msg start reg*/
- sampler (5,4,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/exa_wm_src_sample_planar.g4b b/src/exa_wm_src_sample_planar.g4b
deleted file mode 100644
index 77a5c23..0000000
--- a/src/exa_wm_src_sample_planar.g4b
+++ /dev/null
@@ -1,4 +0,0 @@
- { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 },
- { 0x01800031, 0x22001d29, 0x008d0000, 0x02520001 },
- { 0x01800031, 0x21c01d29, 0x008d0000, 0x02520203 },
- { 0x01800031, 0x22401d29, 0x008d0000, 0x02520405 },
diff --git a/src/exa_wm_write.g4a b/src/exa_wm_write.g4a
deleted file mode 100644
index faee80b..0000000
--- a/src/exa_wm_write.g4a
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-include(`exa_wm.g4i')
-
-/*
- * Prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2),
- *
- * Note that the SIMD16 write message takes data for the first
- * two sub-spans followed by the data for the second two sub-spans
- * instead of having the two sub-spans interleaved by channel. Weird.
- */
-
-mov (8) data_port_r_01<1>F src_sample_r_01<8,8,1>F { align1 };
-mov (8) data_port_g_01<1>F src_sample_g_01<8,8,1>F { align1 };
-mov (8) data_port_b_01<1>F src_sample_b_01<8,8,1>F { align1 };
-mov (8) data_port_a_01<1>F src_sample_a_01<8,8,1>F { align1 };
-
-mov (8) data_port_r_23<1>F src_sample_r_23<8,8,1>F { sechalf align1 };
-mov (8) data_port_g_23<1>F src_sample_g_23<8,8,1>F { sechalf align1 };
-mov (8) data_port_b_23<1>F src_sample_b_23<8,8,1>F { sechalf align1 };
-mov (8) data_port_a_23<1>F src_sample_a_23<8,8,1>F { sechalf align1 };
-
-/* m0, m1 are all direct passed by PS thread payload */
-mov (8) data_port_msg_1<1>UD g1<8,8,1>UD { mask_disable align1 };
-
-/* write */
-send (16)
- data_port_msg_0_ind
- acc0<1>UW
- g0<8,8,1>UW
- write (
- 0, /* binding_table */
- 8, /* pixel scordboard clear, msg type simd16 single source */
- 4, /* render target write */
- 0 /* no write commit message */
- )
- mlen 10
- rlen 0
- { align1 EOT };
-
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-
diff --git a/src/exa_wm_write.g4b b/src/exa_wm_write.g4b
deleted file mode 100644
index 92e7b24..0000000
--- a/src/exa_wm_write.g4b
+++ /dev/null
@@ -1,18 +0,0 @@
- { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 },
- { 0x00600001, 0x206003be, 0x008d0200, 0x00000000 },
- { 0x00600001, 0x208003be, 0x008d0240, 0x00000000 },
- { 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 },
- { 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 },
- { 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 },
- { 0x00601001, 0x210003be, 0x008d0260, 0x00000000 },
- { 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 },
- { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
- { 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/exa_wm_xy.g4a b/src/exa_wm_xy.g4a
deleted file mode 100644
index e99f5ac..0000000
--- a/src/exa_wm_xy.g4a
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.wang at intel.com>
- * Keith Packard <keithp at keithp.com>
- */
-
-/*
- * Register assignments:
- *
- * x g6/g7
- * y g8/g9
- *
- * temp x g10/g11
- * temp y g12/g13
- *
- * src w g14/g15
- * src u m1/m2
- * src v m3/m4
- */
-
-/* Fragment to compute per-pixel XY values */
-
-include(`exa_wm.g4i')
-
- /* Load X and Y coordinates and compute per-pixel coordinates */
-add (16) temp_x_uw<1>UW dst_x_uw 0x10101010V { align1 };
-add (16) temp_y_uw<1>UW dst_y_uw 0x11001100V { align1 };
-
- /* subtract screen-space origin of vertex 0 */
-add (16) dst_x<1>F temp_x_uw<8,8,1>UW -screen_x0 { compr align1 };
-add (16) dst_y<1>F temp_y_uw<8,8,1>UW -screen_y0 { compr align1 };
diff --git a/src/exa_wm_xy.g4b b/src/exa_wm_xy.g4b
deleted file mode 100644
index 327fc29..0000000
--- a/src/exa_wm_xy.g4b
+++ /dev/null
@@ -1,4 +0,0 @@
- { 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 },
- { 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 },
- { 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 },
- { 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 },
diff --git a/src/exa_wm_yuv_rgb.g4a b/src/exa_wm_yuv_rgb.g4a
deleted file mode 100644
index 4fb2576..0000000
--- a/src/exa_wm_yuv_rgb.g4a
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Keith Packard <keithp at keithp.com>
- * Eric Anholt <eric at anholt.net>
- *
- */
-
-include(`exa_wm.g4i')
-
-define(`YCbCr_base', `src_sample_base')
-
-define(`Cr', `src_sample_r')
-define(`Cr_01', `src_sample_r_01')
-define(`Cr_23', `src_sample_r_23')
-
-define(`Y', `src_sample_g')
-define(`Y_01', `src_sample_g_01')
-define(`Y_23', `src_sample_g_23')
-
-define(`Cb', `src_sample_b')
-define(`Cb_01', `src_sample_b_01')
-define(`Cb_23', `src_sample_b_23')
-
-define(`Crn', `mask_sample_r')
-define(`Crn_01', `mask_sample_r_01')
-define(`Crn_23', `mask_sample_r_23')
-
-define(`Yn', `mask_sample_g')
-define(`Yn_01', `mask_sample_g_01')
-define(`Yn_23', `mask_sample_g_23')
-
-define(`Cbn', `mask_sample_b')
-define(`Cbn_01', `mask_sample_b_01')
-define(`Cbn_23', `mask_sample_b_23')
-
- /* color space conversion function:
- * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1)
- * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1)
- * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1)
- */
-
- /* Normalize Y, Cb and Cr:
- *
- * Yn = (Y - 16/255) * 1.164
- * Crn = Cr - 128 / 255
- * Cbn = Cb - 128 / 255
- */
-add (16) Yn<1>F Y<8,8,1>F -0.0627451F { compr align1 };
-mul (16) Yn<1>F Yn<8,8,1>F 1.164F { compr align1 };
-
-add (16) Crn<1>F Cr<8,8,1>F -0.501961F { compr align1 };
-
-add (16) Cbn<1>F Cb<8,8,1>F -0.501961F { compr align1 };
-
- /*
- * R = Y + Cr * 1.596
- */
-mov (16) acc0<1>F Yn<8,8,1>F { compr align1 };
-mac.sat(16) src_sample_r<1>F Crn<8,8,1>F 1.596F { compr align1 };
-
- /*
- * G = Crn * -0.813 + Cbn * -0.392 + Y
- */
-mov (16) acc0<1>F Yn<8,8,1>F { compr align1 };
-mac (16) acc0<1>F Crn<8,8,1>F -0.813F { compr align1 };
-mac.sat(16) src_sample_g<1>F Cbn<8,8,1>F -0.392F { compr align1 };
-
- /*
- * B = Cbn * 2.017 + Y
- */
-mov (16) acc0<1>F Yn<8,8,1>F { compr align1 };
-mac.sat(16) src_sample_b<1>F Cbn<8,8,1>F 2.017F { compr align1 };
-
- /*
- * A = 1.0
- */
-mov (16) src_sample_a<1>F 1.0F { compr align1 };
diff --git a/src/exa_wm_yuv_rgb.g4b b/src/exa_wm_yuv_rgb.g4b
deleted file mode 100644
index 01f6e2b..0000000
--- a/src/exa_wm_yuv_rgb.g4b
+++ /dev/null
@@ -1,12 +0,0 @@
- { 0x00802040, 0x23007fbd, 0x008d0200, 0xbd808081 },
- { 0x00802041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 },
- { 0x00802040, 0x22c07fbd, 0x008d01c0, 0xbf008084 },
- { 0x00802040, 0x23407fbd, 0x008d0240, 0xbf008084 },
- { 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 },
- { 0x80802048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba },
- { 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 },
- { 0x00802048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 },
- { 0x80802048, 0x22007fbd, 0x008d0340, 0xbec8b439 },
- { 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 },
- { 0x80802048, 0x22407fbd, 0x008d0340, 0x40011687 },
- { 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 },
diff --git a/src/packed_yuv_sf.g4a b/src/packed_yuv_sf.g4a
deleted file mode 100644
index 5a02399..0000000
--- a/src/packed_yuv_sf.g4a
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Keith Packard <keithp at keithp.com>
- * Eric Anholt <eric at anholt.net>
- *
- */
-
-send (1) 0 g6<1>F g1.12<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
-send (1) 0 g6.4<1>F g1.20<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
-add (8) g7<1>F g4<8,8,1>F -g3<8,8,1>F { align1 };
-mul (1) g7<1>F g7<0,1,0>F g6<0,1,0>F { align1 };
-mul (1) g7.4<1>F g7.4<0,1,0>F g6.4<0,1,0>F { align1 };
-mov (8) m1<1>F g7<0,1,0>F { align1 };
-mov (8) m2<1>F g7.4<0,1,0>F { align1 };
-mov (8) m3<1>F g3<8,8,1>F { align1 };
-send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
diff --git a/src/packed_yuv_sf.g4b b/src/packed_yuv_sf.g4b
deleted file mode 100644
index 830d176..0000000
--- a/src/packed_yuv_sf.g4b
+++ /dev/null
@@ -1,17 +0,0 @@
- { 0x00000031, 0x20c01fbd, 0x0000002c, 0x01110081 },
- { 0x00000031, 0x20c41fbd, 0x00000034, 0x01110081 },
- { 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
- { 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
- { 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
- { 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
- { 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
- { 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
- { 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/packed_yuv_wm.g4a b/src/packed_yuv_wm.g4a
deleted file mode 100644
index 2be52b5..0000000
--- a/src/packed_yuv_wm.g4a
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright © 2006 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Keith Packard <keithp at keithp.com>
- * Eric Anholt <eric at anholt.net>
- *
- */
-
-include(`exa_wm.g4i')
-
-define(`YCbCr_base', `g12')
-define(`Cr', `g12')
-define(`Cr_01', `g12')
-define(`Cr_23', `g13')
-define(`Y', `g14')
-define(`Y_01', `g14')
-define(`Y_23', `g15')
-define(`Cb', `g16')
-define(`Cb_01', `g16')
-define(`Cb_23', `g17')
-
-/* The initial payload of the thread is always g0.
- * WM_URB (incoming URB entries) is g3
- * X0_R is g4
- * X1_R is g5
- * Y0_R is g6
- * Y1_R is g7
- */
-
- /* Set up the X/Y screen coordinates of the pixels in our 4 subspans. Each
- * subspan is a 2x2 rectangle, and the screen x/y of the upper left of each
- * subspan are given in GRF register 1.2 through 1.5 (which, with the word
- * addressing below, are 1.4 through 1.11).
- *
- * The result is WM_X*_R and WM_Y*R being:
- *
- * X0: {ss0.x, ss0.x+1, ss0.x, ss0.x+1, ss1.x, ss1.x+1, ss1.x, ss1.x+y}
- * Y0: {ss0.y, ss0.y, ss0.y+1, ss0.y+1, ss1.y, ss1.y, ss1.y+1, ss1.y+1}
- * X1: {ss2.x, ss2.x+1, ss2.x, ss2.x+1, ss3.x, ss3.x+1, ss3.x, ss3.x+y}
- * Y1: {ss2.y, ss2.y, ss2.y+1, ss2.y+1, ss3.y, ss3.y, ss3.y+1, ss3.y+1}
- */
-
- /* Set up ss0.x coordinates*/
-mov (1) g4<1>F g1.8<0,1,0>UW { align1 };
-add (1) g4.4<1>F g1.8<0,1,0>UW 1UD { align1 };
-mov (1) g4.8<1>F g1.8<0,1,0>UW { align1 };
-add (1) g4.12<1>F g1.8<0,1,0>UW 1UD { align1 };
- /* Set up ss0.y coordinates */
-mov (1) g6<1>F g1.10<0,1,0>UW { align1 };
-mov (1) g6.4<1>F g1.10<0,1,0>UW { align1 };
-add (1) g6.8<1>F g1.10<0,1,0>UW 1UD { align1 };
-add (1) g6.12<1>F g1.10<0,1,0>UW 1UD { align1 };
- /* set up ss1.x coordinates */
-mov (1) g4.16<1>F g1.12<0,1,0>UW { align1 };
-add (1) g4.20<1>F g1.12<0,1,0>UW 1UD { align1 };
-mov (1) g4.24<1>F g1.12<0,1,0>UW { align1 };
-add (1) g4.28<1>F g1.12<0,1,0>UW 1UD { align1 };
- /* set up ss1.y coordinates */
-mov (1) g6.16<1>F g1.14<0,1,0>UW { align1 };
-mov (1) g6.20<1>F g1.14<0,1,0>UW { align1 };
-add (1) g6.24<1>F g1.14<0,1,0>UW 1UD { align1 };
-add (1) g6.28<1>F g1.14<0,1,0>UW 1UD { align1 };
- /* Set up ss2.x coordinates */
-mov (1) g5<1>F g1.16<0,1,0>UW { align1 };
-add (1) g5.4<1>F g1.16<0,1,0>UW 1UD { align1 };
-mov (1) g5.8<1>F g1.16<0,1,0>UW { align1 };
-add (1) g5.12<1>F g1.16<0,1,0>UW 1UD { align1 };
- /* Set up ss2.y coordinates */
-mov (1) g7<1>F g1.18<0,1,0>UW { align1 };
-mov (1) g7.4<1>F g1.18<0,1,0>UW { align1 };
-add (1) g7.8<1>F g1.18<0,1,0>UW 1UD { align1 };
-add (1) g7.12<1>F g1.18<0,1,0>UW 1UD { align1 };
- /* Set up ss3.x coordinates */
-mov (1) g5.16<1>F g1.20<0,1,0>UW { align1 };
-add (1) g5.20<1>F g1.20<0,1,0>UW 1UD { align1 };
-mov (1) g5.24<1>F g1.20<0,1,0>UW { align1 };
-add (1) g5.28<1>F g1.20<0,1,0>UW 1UD { align1 };
- /* Set up ss3.y coordinates */
-mov (1) g7.16<1>F g1.22<0,1,0>UW { align1 };
-mov (1) g7.20<1>F g1.22<0,1,0>UW { align1 };
-add (1) g7.24<1>F g1.22<0,1,0>UW 1UD { align1 };
-add (1) g7.28<1>F g1.22<0,1,0>UW 1UD { align1 };
-
- /* Now, map these screen space coordinates into texture coordinates. */
- /* subtract screen-space X origin of vertex 0. */
-add (8) g4<1>F g4<8,8,1>F -g1<0,1,0>F { align1 };
-add (8) g5<1>F g5<8,8,1>F -g1<0,1,0>F { align1 };
- /* scale by texture X increment */
-mul (8) g4<1>F g4<8,8,1>F g3<0,1,0>F { align1 };
-mul (8) g5<1>F g5<8,8,1>F g3<0,1,0>F { align1 };
- /* add in texture X offset */
-add (8) g4<1>F g4<8,8,1>F g3.12<0,1,0>F { align1 };
-add (8) g5<1>F g5<8,8,1>F g3.12<0,1,0>F { align1 };
- /* subtract screen-space Y origin of vertex 0. */
-add (8) g6<1>F g6<8,8,1>F -g1.4<0,1,0>F { align1 };
-add (8) g7<1>F g7<8,8,1>F -g1.4<0,1,0>F { align1 };
- /* scale by texture Y increment */
-mul (8) g6<1>F g6<8,8,1>F g3.20<0,1,0>F { align1 };
-mul (8) g7<1>F g7<8,8,1>F g3.20<0,1,0>F { align1 };
- /* add in texture Y offset */
-add (8) g6<1>F g6<8,8,1>F g3.28<0,1,0>F { align1 };
-add (8) g7<1>F g7<8,8,1>F g3.28<0,1,0>F { align1 };
- /* sampler */
-mov (8) m1<1>F g4<8,8,1>F { align1 };
-mov (8) m2<1>F g5<8,8,1>F { align1 };
-mov (8) m3<1>F g6<8,8,1>F { align1 };
-mov (8) m4<1>F g7<8,8,1>F { align1 };
-
- /*
- * g0 holds the PS thread payload, which (oddly) contains
- * precisely what the sampler wants to see in m0
- */
-send (16)
- 0 /* load g0 to m0 */
- YCbCr_base<1>UW
- g0<8,8,1>UW
- sampler (1,0,F)
- mlen 5 rlen 8 { align1 };
-
- /* color space conversion function:
- * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1)
- * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1)
- * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1)
- *
- * Y is g14, g15.
- * Cr is g12, g13.
- * Cb is g16, g17.
- *
- * R is g2, g6.
- * G is g3, g7.
- * B is g4, g8.
- */
-
- /* Normalize Y, Cb and Cr:
- *
- * Y = (Y - 16/255) * 1.164
- * Cr = Cr - 128 / 255
- * Cb = Cb - 128 / 255
- */
-add (16) Y<1>F Y<8,8,1>F -0.0627451F { compr align1 };
-mul (16) Y<1>F Y<8,8,1>F 1.164F { compr align1 };
-
-add (16) Cr<1>F Cr<8,8,1>F -0.501961F { compr align1 };
-
-add (16) Cb<1>F Cb<8,8,1>F -0.501961F { compr align1 };
-
- /*
- * R = Y + Cr * 1.596
- */
-mul (8) null Cr_01<8,8,1>F 1.596F { align1 };
-mac.sat (8) data_port_r_01<1>F Y_01<8,8,1>F 1F { align1 };
-mul (8) null Cr_23<8,8,1>F 1.596F { align1 };
-mac.sat (8) data_port_r_23<1>F Y_23<8,8,1>F 1F { align1 };
-
- /*
- * G = Cr * -0.813 + Cb * -0.392 + Y
- */
-mul (8) null Cr_01<8,8,1>F -0.813F { align1 };
-mac (8) null Cb_01<8,8,1>F -0.392F { align1 };
-mac.sat (8) data_port_g_01<1>F Y_01<8,8,1>F 1F { align1 };
-mul (8) null Cr_23<8,8,1>F -0.813F { align1 };
-mac (8) null Cb_23<8,8,1>F -0.392F { align1 };
-mac.sat (8) data_port_g_23<1>F Y_23<8,8,1>F 1F { align1 };
-
- /*
- * B = Cb * 2.017 + Y
- */
-mul (8) null Cb_01<8,8,1>F 2.017F { align1 };
-mac.sat (8) data_port_b_01<1>F Y_01<8,8,1>F 1F { align1 };
-mul (8) null Cb_23<8,8,1>F 2.017F { align1 };
-mac.sat (8) data_port_b_23<1>F Y_23<8,8,1>F 1F { align1 };
-
- /*
- * A = 1.0
- */
-mov (8) data_port_a_01<1>F 1.0F { align1 };
-mov (8) data_port_a_23<1>F 1.0F { align1 };
-
- /*
- * Pass through control information:
- */
-mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
-
- /*
- * Send framebuffer write message: XXX: acc0?
- */
-send (16) 0 acc0<1>UW g0<8,8,1>UW write (
- 0, /* binding table index 0 */
- 8, /* pixel scoreboard clear */
- 4, /* render target write */
- 0 /* no write commit message */
- ) mlen 10 rlen 0 { align1 EOT };
- /* padding */
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
diff --git a/src/packed_yuv_wm.g4b b/src/packed_yuv_wm.g4b
deleted file mode 100644
index f2e650a..0000000
--- a/src/packed_yuv_wm.g4b
+++ /dev/null
@@ -1,79 +0,0 @@
- { 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
- { 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
- { 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
- { 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
- { 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
- { 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
- { 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
- { 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
- { 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
- { 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
- { 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
- { 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
- { 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
- { 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
- { 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
- { 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
- { 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
- { 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
- { 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
- { 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
- { 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
- { 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
- { 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
- { 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
- { 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
- { 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
- { 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
- { 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
- { 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
- { 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
- { 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
- { 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
- { 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
- { 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
- { 0x00600041, 0x208077bd, 0x008d0080, 0x00000060 },
- { 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000060 },
- { 0x00600040, 0x208077bd, 0x008d0080, 0x0000006c },
- { 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000006c },
- { 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
- { 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
- { 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000074 },
- { 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000074 },
- { 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000007c },
- { 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000007c },
- { 0x00600001, 0x202003be, 0x008d0080, 0x00000000 },
- { 0x00600001, 0x204003be, 0x008d00a0, 0x00000000 },
- { 0x00600001, 0x206003be, 0x008d00c0, 0x00000000 },
- { 0x00600001, 0x208003be, 0x008d00e0, 0x00000000 },
- { 0x00800031, 0x21801d29, 0x008d0000, 0x02580001 },
- { 0x00802040, 0x21c07fbd, 0x008d01c0, 0xbd808081 },
- { 0x00802041, 0x21c07fbd, 0x008d01c0, 0x3f94fdf4 },
- { 0x00802040, 0x21807fbd, 0x008d0180, 0xbf008084 },
- { 0x00802040, 0x22007fbd, 0x008d0200, 0xbf008084 },
- { 0x00600041, 0x20007fbc, 0x008d0180, 0x3fcc49ba },
- { 0x80600048, 0x20407fbe, 0x008d01c0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d01a0, 0x3fcc49ba },
- { 0x80600048, 0x20c07fbe, 0x008d01e0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d0180, 0xbf5020c5 },
- { 0x00600048, 0x20007fbc, 0x008d0200, 0xbec8b439 },
- { 0x80600048, 0x20607fbe, 0x008d01c0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d01a0, 0xbf5020c5 },
- { 0x00600048, 0x20007fbc, 0x008d0220, 0xbec8b439 },
- { 0x80600048, 0x20e07fbe, 0x008d01e0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d0200, 0x40011687 },
- { 0x80600048, 0x20807fbe, 0x008d01c0, 0x3f800000 },
- { 0x00600041, 0x20007fbc, 0x008d0220, 0x40011687 },
- { 0x80600048, 0x21007fbe, 0x008d01e0, 0x3f800000 },
- { 0x00600001, 0x20a003fe, 0x00000000, 0x3f800000 },
- { 0x00600001, 0x212003fe, 0x00000000, 0x3f800000 },
- { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
- { 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am
new file mode 100644
index 0000000..820303f
--- /dev/null
+++ b/src/render_program/Makefile.am
@@ -0,0 +1,66 @@
+INTEL_G4A = \
+ packed_yuv_sf.g4a \
+ packed_yuv_wm.g4a \
+ exa_sf.g4a \
+ exa_sf_mask.g4a \
+ exa_wm_src_affine.g4a \
+ exa_wm_src_projective.g4a \
+ exa_wm_src_sample_argb.g4a \
+ exa_wm_src_sample_a.g4a \
+ exa_wm_src_sample_planar.g4a \
+ exa_wm_mask_affine.g4a \
+ exa_wm_mask_projective.g4a \
+ exa_wm_mask_sample_argb.g4a \
+ exa_wm_mask_sample_a.g4a \
+ exa_wm_noca.g4a \
+ exa_wm_ca.g4a \
+ exa_wm_ca_srcalpha.g4a \
+ exa_wm_write.g4a \
+ exa_wm_yuv_rgb.g4a \
+ exa_wm_xy.g4a
+
+INTEL_G4I = \
+ exa_wm.g4i \
+ exa_wm_affine.g4i \
+ exa_wm_projective.g4i
+
+INTEL_G4B = \
+ packed_yuv_sf.g4b \
+ packed_yuv_wm.g4b \
+ exa_sf.g4b \
+ exa_sf_mask.g4b \
+ exa_wm_src_affine.g4b \
+ exa_wm_src_projective.g4b \
+ exa_wm_src_sample_argb.g4b \
+ exa_wm_src_sample_a.g4b \
+ exa_wm_src_sample_planar.g4b \
+ exa_wm_mask_affine.g4b \
+ exa_wm_mask_projective.g4b \
+ exa_wm_mask_sample_argb.g4b \
+ exa_wm_mask_sample_a.g4b \
+ exa_wm_noca.g4b \
+ exa_wm_ca.g4b \
+ exa_wm_ca_srcalpha.g4b \
+ exa_wm_write.g4b \
+ exa_wm_yuv_rgb.g4b \
+ exa_wm_xy.g4b
+
+
+EXTRA_DIST = \
+ $(INTEL_G4A) \
+ $(INTEL_G4I) \
+ $(INTEL_G4B)
+
+if HAVE_GEN4ASM
+
+SUFFIXES = .g4a .g4b
+.g4a.g4b:
+ m4 -I$(srcdir) -s $< > $*.g4m && intel-gen4asm -o $@ $*.g4m && rm $*.g4m
+
+$(INTEL_G4B): $(INTEL_G4I)
+
+BUILT_SOURCES= $(INTEL_G4B)
+
+clean-local:
+ -rm -f $(INTEL_G4B)
+endif
diff --git a/src/render_program/exa_sf.g4a b/src/render_program/exa_sf.g4a
new file mode 100644
index 0000000..3e660ac
--- /dev/null
+++ b/src/render_program/exa_sf.g4a
@@ -0,0 +1,107 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Keith Packard <keithp at keithp.com>
+ * Eric Anholt <eric at anholt.net>
+ *
+ */
+
+/*
+ * Inputs (note all sub-register addresses are bytes, not float indices)
+ *
+ * Note that the vertices will have been reordered:
+ *
+ * V0 is topmost (leftmost among topmost) (upper left)
+ * V1 is next clockwise (lower right)
+ * V2 is remaining (lower left)
+ *
+ * V0 ...................... XX
+ * | .
+ * | .
+ * | .
+ * V2------------------------V1
+ *
+ * G0 thread state -- just pass along
+ *
+ * G1 and G2 are fixed by SF spec
+ *
+ * G1.0 reserved
+ * G1.4 Provoking vertex
+ * G1.8 Determinant
+ * G1.12 X1 - X0
+ * G1.16 X2 - X0
+ * G1.20 Y1 - Y0
+ * G1.24 Y2 - Y0
+ * G1.30 reserved
+ *
+ * G2.0 Z0
+ * G2.4 1/W0
+ * G2.8 Z1
+ * G2.12 1/W1
+ * G2.16 Z2
+ * G2.20 1/W2
+ * G2.24 reserved
+ * G2.30 reserved
+ *
+ * G3 is V0 Vertex Attribute Data from URB (upper left)
+ *
+ * G3.0 u0
+ * G3.4 v0
+ *
+ * G4 is V1 Vertex Attribute Data from URB (lower right)
+ *
+ * G4.0 u1
+ * G4.4 v1
+ *
+ * G5 is V2 Vertex Attribute Data from URB (lower left)
+ *
+ */
+
+/* Compute inverses of the input deltas */
+send (4) 0 g6<1>F g1.12<4,4,1>F math inv mlen 1 rlen 1 { align1 };
+
+/* texture location at V0 */
+mov (4) m3<1>F g3<4,4,1>F { align1 };
+
+/* compute V1 - V2 (motion in X) for texture coordinates */
+add (4) g7<1>F g4<4,4,1>F -g5<4,4,1>F { align1 };
+
+/* multiply by 1/dx */
+mul (4) m1<1>F g7<4,4,1>F g6.0<0,1,0>F { align1 };
+
+/* Compute V2 - V0 (motion in Y) for texture coordinates */
+add (4) g7<1>F g5<4,4,1>F -g3<4,4,1>F { align1 };
+
+/* multiply by 1/dy */
+mul (4) m2<1>F g7<4,4,1>F g6.8<0,1,0>F {align1 };
+
+/* and we're done */
+send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
diff --git a/src/render_program/exa_sf.g4b b/src/render_program/exa_sf.g4b
new file mode 100644
index 0000000..223c9c9
--- /dev/null
+++ b/src/render_program/exa_sf.g4b
@@ -0,0 +1,15 @@
+ { 0x00400031, 0x20c01fbd, 0x0069002c, 0x01110001 },
+ { 0x00400001, 0x206003be, 0x00690060, 0x00000000 },
+ { 0x00400040, 0x20e077bd, 0x00690080, 0x006940a0 },
+ { 0x00400041, 0x202077be, 0x006900e0, 0x000000c0 },
+ { 0x00400040, 0x20e077bd, 0x006900a0, 0x00694060 },
+ { 0x00400041, 0x204077be, 0x006900e0, 0x000000c8 },
+ { 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_sf_mask.g4a b/src/render_program/exa_sf_mask.g4a
new file mode 100644
index 0000000..5078d01
--- /dev/null
+++ b/src/render_program/exa_sf_mask.g4a
@@ -0,0 +1,107 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Keith Packard <keithp at keithp.com>
+ * Eric Anholt <eric at anholt.net>
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ */
+
+/*
+ * Inputs (note all sub-register addresses are bytes, not float indices)
+ *
+ * Note that the vertices will have been reordered:
+ *
+ * V0 is topmost (leftmost among topmost) (upper left)
+ * V1 is next clockwise (lower right)
+ * V2 is remaining (lower left)
+ *
+ * V0 ...................... XX
+ * | .
+ * | .
+ * | .
+ * V2------------------------V1
+ *
+ * G0 thread state -- just pass along
+ *
+ * G1 and G2 are fixed by SF spec
+ *
+ * G1.0 reserved
+ * G1.4 Provoking vertex
+ * G1.8 Determinant
+ * G1.12 X1 - X0
+ * G1.16 X2 - X0
+ * G1.20 Y1 - Y0
+ * G1.24 Y2 - Y0
+ * G1.30 reserved
+ *
+ * G2.0 Z0
+ * G2.4 1/W0
+ * G2.8 Z1
+ * G2.12 1/W1
+ * G2.16 Z2
+ * G2.20 1/W2
+ * G2.24 reserved
+ * G2.30 reserved
+ *
+ * G3 is V0 Vertex Attribute Data from URB (upper left)
+ *
+ * G3.0 u0
+ * G3.4 v0
+ *
+ * G4 is V1 Vertex Attribute Data from URB (lower right)
+ *
+ * G4.0 u1
+ * G4.4 v1
+ *
+ * G5 is V2 Vertex Attribute Data from URB (lower left)
+ *
+ */
+
+/* Compute inverses of the input deltas */
+send (4) 0 g6<1>F g1.12<4,4,1>F math inv mlen 1 rlen 1 { align1 };
+
+/* texture location at V0 */
+mov (8) m3<1>F g3<8,8,1>F { align1 };
+
+/* compute V1 - V2 (motion in X) for texture coordinates */
+add (8) g7<1>F g4<8,8,1>F -g5<8,8,1>F { align1 };
+
+/* multiply by 1/dx */
+mul (8) m1<1>F g7<8,8,1>F g6.0<0,1,0>F { align1 };
+
+/* Compute V2 - V0 (motion in Y) for texture coordinates */
+add (8) g7<1>F g5<8,8,1>F -g3<8,8,1>F { align1 };
+
+/* multiply by 1/dy */
+mul (8) m2<1>F g7<8,8,1>F g6.8<0,1,0>F {align1 };
+
+/* and we're done */
+send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
diff --git a/src/render_program/exa_sf_mask.g4b b/src/render_program/exa_sf_mask.g4b
new file mode 100644
index 0000000..be0a77b
--- /dev/null
+++ b/src/render_program/exa_sf_mask.g4b
@@ -0,0 +1,15 @@
+ { 0x00400031, 0x20c01fbd, 0x0069002c, 0x01110001 },
+ { 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
+ { 0x00600040, 0x20e077bd, 0x008d0080, 0x008d40a0 },
+ { 0x00600041, 0x202077be, 0x008d00e0, 0x000000c0 },
+ { 0x00600040, 0x20e077bd, 0x008d00a0, 0x008d4060 },
+ { 0x00600041, 0x204077be, 0x008d00e0, 0x000000c8 },
+ { 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_wm.g4i b/src/render_program/exa_wm.g4i
new file mode 100644
index 0000000..5d3d45b
--- /dev/null
+++ b/src/render_program/exa_wm.g4i
@@ -0,0 +1,156 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/*
+ * Input parameters
+ */
+
+/* Destination X/Y */
+define(`dst_x_uw', `g1.8<2,4,0>UW')
+define(`dst_y_uw', `g1.10<2,4,0>UW')
+define(`screen_x0', `g1.0<0,1,0>F')
+define(`screen_y0', `g1.4<0,1,0>F')
+
+/* Source transformation parameters */
+define(`src_du_dx', `g3.0<0,1,0>F')
+define(`src_du_dy', `g3.4<0,1,0>F')
+define(`src_uo', `g3.12<0,1,0>F')
+define(`src_dv_dx', `g3.16<0,1,0>F')
+define(`src_dv_dy', `g3.20<0,1,0>F')
+define(`src_vo', `g3.28<0,1,0>F')
+define(`src_dw_dx', `g4.0<0,1,0>F')
+define(`src_dw_dy', `g4.4<0,1,0>F')
+define(`src_wo', `g4.12<0,1,0>F')
+
+define(`mask_du_dx', `g5.0<0,1,0>F')
+define(`mask_du_dy', `g5.4<0,1,0>F')
+define(`mask_uo', `g5.12<0,1,0>F')
+define(`mask_dv_dx', `g5.16<0,1,0>F')
+define(`mask_dv_dy', `g5.20<0,1,0>F')
+define(`mask_vo', `g5.28<0,1,0>F')
+define(`mask_dw_dx', `g6.0<0,1,0>F')
+define(`mask_dw_dy', `g6.4<0,1,0>F')
+define(`mask_wo', `g6.12<0,1,0>F')
+
+/*
+ * Local variables. Pairs must be aligned on even reg boundry
+ */
+
+/* this holds the X dest coordinates */
+define(`dst_x', `g8')
+define(`dst_x_0', `dst_x')
+define(`dst_x_1', `g9')
+
+/* this holds the Y dest coordinates */
+define(`dst_y', `g10')
+define(`dst_y_0', `dst_y')
+define(`dst_y_1', `g11')
+
+/* When computing x * dn/dx, use this */
+define(`temp_x', `g30')
+define(`temp_x_0', `temp_x')
+define(`temp_x_1', `g31')
+
+/* When computing y * dn/dy, use this */
+define(`temp_y', `g28')
+define(`temp_y_0', temp_y)
+define(`temp_y_1', `g29')
+
+/* when loading x/y, use these to hold them in UW format */
+define(`temp_x_uw', temp_x)
+define(`temp_y_uw', temp_y)
+
+/* compute source and mask u/v to this pair to send to sampler */
+define(`src_msg', `m1')
+define(`src_msg_ind',`1')
+define(`src_u', `m2')
+define(`src_v', `m4')
+define(`src_w', `g12')
+define(`src_w_0', `src_w')
+define(`src_w_1', `g13')
+
+define(`mask_msg', `m7')
+define(`mask_msg_ind',`7')
+define(`mask_u', `m8')
+define(`mask_v', `m10')
+define(`mask_w', `src_w')
+define(`mask_w_0', `src_w_0')
+define(`mask_w_1', `src_w_1')
+
+/* sample src to these registers */
+define(`src_sample_base', `g14')
+
+define(`src_sample_r', `g14')
+define(`src_sample_r_01', `g14')
+define(`src_sample_r_23', `g15')
+
+define(`src_sample_g', `g16')
+define(`src_sample_g_01', `g16')
+define(`src_sample_g_23', `g17')
+
+define(`src_sample_b', `g18')
+define(`src_sample_b_01', `g18')
+define(`src_sample_b_23', `g19')
+
+define(`src_sample_a', `g20')
+define(`src_sample_a_01', `g20')
+define(`src_sample_a_23', `g21')
+
+/* sample mask to these registers */
+define(`mask_sample_base', `g22')
+
+define(`mask_sample_r', `g22')
+define(`mask_sample_r_01', `g22')
+define(`mask_sample_r_23', `g23')
+
+define(`mask_sample_g', `g24')
+define(`mask_sample_g_01', `g24')
+define(`mask_sample_g_23', `g25')
+
+define(`mask_sample_b', `g26')
+define(`mask_sample_b_01', `g26')
+define(`mask_sample_b_23', `g27')
+
+define(`mask_sample_a', `g28')
+define(`mask_sample_a_01', `g28')
+define(`mask_sample_a_23', `g29')
+
+/* data port SIMD16 send registers */
+
+define(`data_port_msg_0', `m0')
+define(`data_port_msg_0_ind', `0')
+define(`data_port_msg_1', `m1')
+define(`data_port_r_01', `m2')
+define(`data_port_g_01', `m3')
+define(`data_port_b_01', `m4')
+define(`data_port_a_01', `m5')
+
+define(`data_port_r_23', `m6')
+define(`data_port_g_23', `m7')
+define(`data_port_b_23', `m8')
+define(`data_port_a_23', `m9')
+
diff --git a/src/render_program/exa_wm_affine.g4i b/src/render_program/exa_wm_affine.g4i
new file mode 100644
index 0000000..e72656b
--- /dev/null
+++ b/src/render_program/exa_wm_affine.g4i
@@ -0,0 +1,44 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/*
+ * Fragment to compute src u/v values under an affine transform
+ */
+
+/********** Compute u *************/
+
+mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
+mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
+add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
+add (16) u<1>F temp_x<8,8,1>F uo { compr align1 };
+
+/********** Compute v *************/
+
+mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
+mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
+add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
+add (16) v<1>F temp_x<8,8,1>F vo { compr align1 };
diff --git a/src/render_program/exa_wm_ca.g4a b/src/render_program/exa_wm_ca.g4a
new file mode 100644
index 0000000..5d982b3
--- /dev/null
+++ b/src/render_program/exa_wm_ca.g4a
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/*
+ * Composite src and mask together, no component alpha
+ */
+
+include(`exa_wm.g4i')
+
+/* mul mask rgba channels to src */
+mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_r_01<8,8,1>F { compr align1 };
+mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_g_01<8,8,1>F { compr align1 };
+mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_b_01<8,8,1>F { compr align1 };
+mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
diff --git a/src/render_program/exa_wm_ca.g4b b/src/render_program/exa_wm_ca.g4b
new file mode 100644
index 0000000..372e8b2
--- /dev/null
+++ b/src/render_program/exa_wm_ca.g4b
@@ -0,0 +1,4 @@
+ { 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d02c0 },
+ { 0x00802041, 0x220077bd, 0x008d0200, 0x008d0300 },
+ { 0x00802041, 0x224077bd, 0x008d0240, 0x008d0340 },
+ { 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 },
diff --git a/src/render_program/exa_wm_ca_srcalpha.g4a b/src/render_program/exa_wm_ca_srcalpha.g4a
new file mode 100644
index 0000000..d1f847f
--- /dev/null
+++ b/src/render_program/exa_wm_ca_srcalpha.g4a
@@ -0,0 +1,37 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/*
+ * Composite src and mask together, no component alpha
+ */
+
+include(`exa_wm.g4i')
+
+mul (16) src_sample_r_01<1>F mask_sample_r_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 };
+mul (16) src_sample_g_01<1>F mask_sample_g_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 };
+mul (16) src_sample_b_01<1>F mask_sample_b_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 };
+mul (16) src_sample_a_01<1>F mask_sample_a_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 };
diff --git a/src/render_program/exa_wm_ca_srcalpha.g4b b/src/render_program/exa_wm_ca_srcalpha.g4b
new file mode 100644
index 0000000..963d676
--- /dev/null
+++ b/src/render_program/exa_wm_ca_srcalpha.g4b
@@ -0,0 +1,4 @@
+ { 0x00802041, 0x21c077bd, 0x008d02c0, 0x008d0280 },
+ { 0x00802041, 0x220077bd, 0x008d0300, 0x008d0280 },
+ { 0x00802041, 0x224077bd, 0x008d0340, 0x008d0280 },
+ { 0x00802041, 0x228077bd, 0x008d0380, 0x008d0280 },
diff --git a/src/render_program/exa_wm_mask_affine.g4a b/src/render_program/exa_wm_mask_affine.g4a
new file mode 100644
index 0000000..9c52d2f
--- /dev/null
+++ b/src/render_program/exa_wm_mask_affine.g4a
@@ -0,0 +1,41 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+include(`exa_wm.g4i')
+
+define(`du_dx', `mask_du_dx')
+define(`du_dy', `mask_du_dy')
+define(`uo', `mask_uo')
+
+define(`dv_dx', `mask_dv_dx')
+define(`dv_dy', `mask_dv_dy')
+define(`vo', `mask_vo')
+
+define(`u', `mask_u')
+define(`v', `mask_v')
+
+include(`exa_wm_affine.g4i')
diff --git a/src/render_program/exa_wm_mask_affine.g4b b/src/render_program/exa_wm_mask_affine.g4b
new file mode 100644
index 0000000..14a5451
--- /dev/null
+++ b/src/render_program/exa_wm_mask_affine.g4b
@@ -0,0 +1,8 @@
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x210077be, 0x008d03c0, 0x000000ac },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x214077be, 0x008d03c0, 0x000000bc },
diff --git a/src/render_program/exa_wm_mask_projective.g4a b/src/render_program/exa_wm_mask_projective.g4a
new file mode 100644
index 0000000..9acaace
--- /dev/null
+++ b/src/render_program/exa_wm_mask_projective.g4a
@@ -0,0 +1,53 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+include(`exa_wm.g4i')
+
+define(`du_dx', `mask_du_dx')
+define(`du_dy', `mask_du_dy')
+define(`uo', `mask_uo')
+
+define(`dv_dx', `mask_dv_dx')
+define(`dv_dy', `mask_dv_dy')
+define(`vo', `mask_vo')
+
+define(`dw_dx', `mask_dw_dx')
+define(`dw_dy', `mask_dw_dy')
+define(`wo', `mask_wo')
+
+define(`u', `mask_u')
+define(`v', `mask_v')
+define(`w', `mask_w')
+
+define(`u_0', `mask_u_0')
+define(`v_0', `mask_v_0')
+define(`u_1', `mask_u_1')
+define(`v_1', `mask_v_1')
+define(`w_0', `mask_w_0')
+define(`w_1', `mask_w_1')
+
+include(`exa_wm_projective.g4i')
diff --git a/src/render_program/exa_wm_mask_projective.g4b b/src/render_program/exa_wm_mask_projective.g4b
new file mode 100644
index 0000000..78cb9ae
--- /dev/null
+++ b/src/render_program/exa_wm_mask_projective.g4b
@@ -0,0 +1,16 @@
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000c0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000c4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000cc },
+ { 0x00600031, 0x21801fbd, 0x008d03c0, 0x01110001 },
+ { 0x00600031, 0x21a01fbd, 0x008d03e0, 0x01110001 },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000ac },
+ { 0x00802041, 0x210077be, 0x008d03c0, 0x008d0180 },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000bc },
+ { 0x00802041, 0x214077be, 0x008d03c0, 0x008d0180 },
diff --git a/src/render_program/exa_wm_mask_sample_a.g4a b/src/render_program/exa_wm_mask_sample_a.g4a
new file mode 100644
index 0000000..bbb19d7
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_a.g4a
@@ -0,0 +1,48 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/* Sample the mask surface */
+
+include(`exa_wm.g4i')
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load only alpha */
+mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable };
+
+/* mask_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+send (16) mask_msg_ind /* msg reg index */
+ mask_sample_a_01<1>UW /* readback */
+ g0<8,8,1>UW /* copy to msg start reg*/
+ sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
+
diff --git a/src/render_program/exa_wm_mask_sample_a.g4b b/src/render_program/exa_wm_mask_sample_a.g4b
new file mode 100644
index 0000000..018bd36
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_a.g4b
@@ -0,0 +1,2 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
+ { 0x07800031, 0x23801d29, 0x008d0000, 0x02520102 },
diff --git a/src/render_program/exa_wm_mask_sample_argb.g4a b/src/render_program/exa_wm_mask_sample_argb.g4a
new file mode 100644
index 0000000..def4cfe
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_argb.g4a
@@ -0,0 +1,48 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/* Sample the mask surface */
+
+include(`exa_wm.g4i')
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load argb */
+mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable };
+
+/* mask_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+send (16) mask_msg_ind /* msg reg index */
+ mask_sample_base<1>UW /* readback */
+ g0<8,8,1>UW /* copy to msg start reg*/
+ sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
+
diff --git a/src/render_program/exa_wm_mask_sample_argb.g4b b/src/render_program/exa_wm_mask_sample_argb.g4b
new file mode 100644
index 0000000..b159cba
--- /dev/null
+++ b/src/render_program/exa_wm_mask_sample_argb.g4b
@@ -0,0 +1,2 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
+ { 0x07800031, 0x22c01d29, 0x008d0000, 0x02580102 },
diff --git a/src/render_program/exa_wm_noca.g4a b/src/render_program/exa_wm_noca.g4a
new file mode 100644
index 0000000..d0d60fa
--- /dev/null
+++ b/src/render_program/exa_wm_noca.g4a
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/*
+ * Composite src and mask together, no component alpha
+ */
+
+include(`exa_wm.g4i')
+/* mul mask's alpha channel to src */
+
+mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
+mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
+mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
+mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 };
diff --git a/src/render_program/exa_wm_noca.g4b b/src/render_program/exa_wm_noca.g4b
new file mode 100644
index 0000000..1506334
--- /dev/null
+++ b/src/render_program/exa_wm_noca.g4b
@@ -0,0 +1,4 @@
+ { 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d0380 },
+ { 0x00802041, 0x220077bd, 0x008d0200, 0x008d0380 },
+ { 0x00802041, 0x224077bd, 0x008d0240, 0x008d0380 },
+ { 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 },
diff --git a/src/render_program/exa_wm_nomask.g4a b/src/render_program/exa_wm_nomask.g4a
new file mode 100644
index 0000000..eb535fe
--- /dev/null
+++ b/src/render_program/exa_wm_nomask.g4a
@@ -0,0 +1,143 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ */
+
+/*
+ * This's for exa composite operation in no mask picture case.
+ * The simplest case is just sending what src picture has to dst picture.
+ */
+
+/* I think this should be same as in g4a program for texture video,
+ as we also use 16-pixel dispatch. and SF scale in g3 is useful for us. */
+
+/* The initial payload of the thread is always g0.
+ * WM_URB (incoming URB entries) is g3
+ * X0_R is g4
+ * X1_R is g5
+ * Y0_R is g6
+ * Y1_R is g7
+ */
+
+
+/* Load X and Y coordinates and compute per-pixel coordinates */
+add (16) g4<1>UW g1.8<2,4,0>UW 0x10101010V { align1 };
+add (16) g6<1>UW g1.10<2,4,0>UW 0x11001100V { align1 };
+
+ /* Now, map these screen space coordinates into texture coordinates. */
+
+ /* subtract screen-space X origin of vertex 0. */
+add (16) g12<1>F g4<8,8,1>UW -g1.0<0,1,0>F { compr align1 };
+
+ /* subtract screen-space Y origin of vertex 0. */
+add (16) g16<1>F g6<8,8,1>UW -g1.4<0,1,0>F { compr align1 };
+
+ /* g8/g9 = X * du/dx */
+mul (16) g8<1>F g12<8,8,1>F g3.0<0,1,0>F { compr align1 };
+
+ /* g10/g11 = Y * du/dy */
+mul (16) g10<1>F g16<8,8,1>F g3.4<0,1,0>F { compr align1 };
+
+ /* g8/g9 = X du/dx + Y du/dy */
+add (16) g8<1>F g8<8,8,1>F g10<8,8,1>F { compr align1 };
+
+ /* m1/m2 = g8/g9 + uo */
+add (16) m1<1>F g8<8,8,1>F g3.12<0,1,0>F { compr align1 };
+
+
+ /* g8/g9 = X * dv/dx */
+mul (16) g8<1>F g12<8,8,1>F g3.16<0,1,0>F { compr align1 };
+
+ /* g10/g11 = Y * du/dy */
+mul (16) g10<1>F g16<8,8,1>F g3.20<0,1,0>F { compr align1 };
+
+ /* g8/g9 = X du/dx + Y du/dy */
+add (16) g8<1>F g8<8,8,1>F g10<8,8,1>F { compr align1 };
+
+ /* m3/m4 = g8/g9 + vo */
+add (16) m3<1>F g8<8,8,1>F g3.28<0,1,0>F { compr align1 };
+
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* m0 will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+send (16) 0 /* msg reg index */
+ g12<1>UW /* readback */
+ g0<8,8,1>UW /* copy to msg start reg*/
+ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
+
+mov (8) g19<1>UD g19<8,8,1>UD { align1 }; /* wait sampler return */
+/* if we set up read-back reg correctly, emit dataport write 'send' cmd with EOT */
+
+/* m0, m1 are all direct passed by PS thread payload */
+mov (8) m1<1>F g1<8,8,1>F { align1 };
+
+/* prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2), then it's ready to write */
+/* g12 -> m2
+ g13 -> m6
+ g14 -> m3
+ g15 -> m7
+ g16 -> m4
+ g17 -> m8
+ g18 -> m5
+ g19 -> m9
+*/
+mov (8) m2<1>F g12<8,8,1>F { align1 };
+mov (8) m3<1>F g14<8,8,1>F { align1 };
+mov (8) m4<1>F g16<8,8,1>F { align1 };
+mov (8) m5<1>F g18<8,8,1>F { align1 };
+mov (8) m6<1>F g13<8,8,1>F { align1 };
+mov (8) m7<1>F g15<8,8,1>F { align1 };
+mov (8) m8<1>F g17<8,8,1>F { align1 };
+mov (8) m9<1>F g19<8,8,1>F { align1 };
+
+/* m0, m1 are all direct passed by PS thread payload */
+mov (8) m1<1>UD g1<8,8,1>UD { align1 };
+
+/* write */
+send (16) 0 acc0<1>UW g0<8,8,1>UW write (
+ 0, /* binding_table */
+ 8, /* pixel scordboard clear, msg type simd16 single source */
+ 4, /* render target write */
+ 0 /* no write commit message */
+ )
+ mlen 10
+ rlen 0
+ { align1 EOT };
+
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
diff --git a/src/render_program/exa_wm_projective.g4i b/src/render_program/exa_wm_projective.g4i
new file mode 100644
index 0000000..7e2e0a8
--- /dev/null
+++ b/src/render_program/exa_wm_projective.g4i
@@ -0,0 +1,51 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/********** Compute w *************/
+
+mul (16) temp_x<1>F dst_x<8,8,1>F dw_dx { compr align1 };
+mul (16) temp_y<1>F dst_y<8,8,1>F dw_dy { compr align1 };
+add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
+add (16) temp_x<1>F temp_x<8,8,1>F wo { compr align1 };
+send (8) 0 w_0<1>F temp_x_0<8,8,1>F math inv mlen 1 rlen 1 { align1 };
+send (8) 0 w_1<1>F temp_x_1<8,8,1>F math inv mlen 1 rlen 1 { sechalf align1 };
+
+/********** Compute u *************/
+
+mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 };
+mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 };
+add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
+add (16) temp_x<1>F temp_x<8,8,1>F uo { compr align1 };
+mul (16) u<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
+
+/********** Compute v *************/
+
+mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 };
+mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 };
+add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
+add (16) temp_x<1>F temp_x<8,8,1>F vo { compr align1 };
+mul (16) v<1>F temp_x<8,8,1>F w<8,8,1>F { compr align1 };
diff --git a/src/render_program/exa_wm_src_affine.g4a b/src/render_program/exa_wm_src_affine.g4a
new file mode 100644
index 0000000..3194b5a
--- /dev/null
+++ b/src/render_program/exa_wm_src_affine.g4a
@@ -0,0 +1,45 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/*
+ * Fragment to compute src u/v values under an affine transform
+ */
+
+include(`exa_wm.g4i')
+
+define(`du_dx', `src_du_dx')
+define(`du_dy', `src_du_dy')
+define(`uo', `src_uo')
+
+define(`dv_dx', `src_dv_dx')
+define(`dv_dy', `src_dv_dy')
+define(`vo', `src_vo')
+
+define(`u', `src_u')
+define(`v', `src_v')
+
+include(`exa_wm_affine.g4i')
diff --git a/src/render_program/exa_wm_src_affine.g4b b/src/render_program/exa_wm_src_affine.g4b
new file mode 100644
index 0000000..d30da87
--- /dev/null
+++ b/src/render_program/exa_wm_src_affine.g4b
@@ -0,0 +1,8 @@
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x204077be, 0x008d03c0, 0x0000006c },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x208077be, 0x008d03c0, 0x0000007c },
diff --git a/src/render_program/exa_wm_src_projective.g4a b/src/render_program/exa_wm_src_projective.g4a
new file mode 100644
index 0000000..16c9cd5
--- /dev/null
+++ b/src/render_program/exa_wm_src_projective.g4a
@@ -0,0 +1,49 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+
+include(`exa_wm.g4i')
+define(`du_dx', `src_du_dx')
+define(`du_dy', `src_du_dy')
+define(`uo', `src_uo')
+define(`dv_dx', `src_dv_dx')
+define(`dv_dy', `src_dv_dy')
+define(`vo', `src_vo')
+define(`dw_dx', `src_dw_dx')
+define(`dw_dy', `src_dw_dy')
+define(`wo', `src_wo')
+define(`u', `src_u')
+define(`v', `src_v')
+define(`w', `src_w')
+define(`u_0', `src_u_0')
+define(`v_0', `src_v_0')
+define(`u_1', `src_u_1')
+define(`v_1', `src_v_1')
+define(`w_0', `src_w_0')
+define(`w_1', `src_w_1')
+
+include(`exa_wm_projective.g4i')
diff --git a/src/render_program/exa_wm_src_projective.g4b b/src/render_program/exa_wm_src_projective.g4b
new file mode 100644
index 0000000..198bab3
--- /dev/null
+++ b/src/render_program/exa_wm_src_projective.g4b
@@ -0,0 +1,16 @@
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000080 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000084 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000008c },
+ { 0x00600031, 0x21801fbd, 0x008d03c0, 0x01110001 },
+ { 0x00600031, 0x21a01fbd, 0x008d03e0, 0x01110001 },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000006c },
+ { 0x00802041, 0x204077be, 0x008d03c0, 0x008d0180 },
+ { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
+ { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
+ { 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000007c },
+ { 0x00802041, 0x208077be, 0x008d03c0, 0x008d0180 },
diff --git a/src/render_program/exa_wm_src_sample_a.g4a b/src/render_program/exa_wm_src_sample_a.g4a
new file mode 100644
index 0000000..552aaee
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_a.g4a
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/* Sample the src surface */
+
+include(`exa_wm.g4i')
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load alpha */
+mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable };
+
+/* src_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_a_01<1>UW /* readback */
+ g0<8,8,1>UW /* copy to msg start reg*/
+ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/render_program/exa_wm_src_sample_a.g4b b/src/render_program/exa_wm_src_sample_a.g4b
new file mode 100644
index 0000000..ce8650a
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_a.g4b
@@ -0,0 +1,2 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 },
+ { 0x01800031, 0x22801d29, 0x008d0000, 0x02520001 },
diff --git a/src/render_program/exa_wm_src_sample_argb.g4a b/src/render_program/exa_wm_src_sample_argb.g4a
new file mode 100644
index 0000000..c20f53f
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g4a
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/* Sample the src surface */
+
+include(`exa_wm.g4i')
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load argb */
+mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable };
+
+/* src_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_base<1>UW /* readback */
+ g0<8,8,1>UW /* copy to msg start reg*/
+ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/render_program/exa_wm_src_sample_argb.g4b b/src/render_program/exa_wm_src_sample_argb.g4b
new file mode 100644
index 0000000..c5b9274
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g4b
@@ -0,0 +1,2 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
+ { 0x01800031, 0x21c01d29, 0x008d0000, 0x02580001 },
diff --git a/src/render_program/exa_wm_src_sample_planar.g4a b/src/render_program/exa_wm_src_sample_planar.g4a
new file mode 100644
index 0000000..ca77b48
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_planar.g4a
@@ -0,0 +1,65 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/* Sample the src surface in planar format */
+
+include(`exa_wm.g4i')
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load r */
+mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable };
+
+/* src_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+
+/* sample Y */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_g<1>UW /* readback */
+ g0<8,8,1>UW /* copy to msg start reg*/
+ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
+
+/* sample U (Cr) */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_r<1>UW /* readback */
+ g0<8,8,1>UW /* copy to msg start reg*/
+ sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
+
+/* sample V (Cb) */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_b<1>UW /* readback */
+ g0<8,8,1>UW /* copy to msg start reg*/
+ sampler (5,4,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/render_program/exa_wm_src_sample_planar.g4b b/src/render_program/exa_wm_src_sample_planar.g4b
new file mode 100644
index 0000000..77a5c23
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_planar.g4b
@@ -0,0 +1,4 @@
+ { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 },
+ { 0x01800031, 0x22001d29, 0x008d0000, 0x02520001 },
+ { 0x01800031, 0x21c01d29, 0x008d0000, 0x02520203 },
+ { 0x01800031, 0x22401d29, 0x008d0000, 0x02520405 },
diff --git a/src/render_program/exa_wm_write.g4a b/src/render_program/exa_wm_write.g4a
new file mode 100644
index 0000000..faee80b
--- /dev/null
+++ b/src/render_program/exa_wm_write.g4a
@@ -0,0 +1,74 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+include(`exa_wm.g4i')
+
+/*
+ * Prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2),
+ *
+ * Note that the SIMD16 write message takes data for the first
+ * two sub-spans followed by the data for the second two sub-spans
+ * instead of having the two sub-spans interleaved by channel. Weird.
+ */
+
+mov (8) data_port_r_01<1>F src_sample_r_01<8,8,1>F { align1 };
+mov (8) data_port_g_01<1>F src_sample_g_01<8,8,1>F { align1 };
+mov (8) data_port_b_01<1>F src_sample_b_01<8,8,1>F { align1 };
+mov (8) data_port_a_01<1>F src_sample_a_01<8,8,1>F { align1 };
+
+mov (8) data_port_r_23<1>F src_sample_r_23<8,8,1>F { sechalf align1 };
+mov (8) data_port_g_23<1>F src_sample_g_23<8,8,1>F { sechalf align1 };
+mov (8) data_port_b_23<1>F src_sample_b_23<8,8,1>F { sechalf align1 };
+mov (8) data_port_a_23<1>F src_sample_a_23<8,8,1>F { sechalf align1 };
+
+/* m0, m1 are all direct passed by PS thread payload */
+mov (8) data_port_msg_1<1>UD g1<8,8,1>UD { mask_disable align1 };
+
+/* write */
+send (16)
+ data_port_msg_0_ind
+ acc0<1>UW
+ g0<8,8,1>UW
+ write (
+ 0, /* binding_table */
+ 8, /* pixel scordboard clear, msg type simd16 single source */
+ 4, /* render target write */
+ 0 /* no write commit message */
+ )
+ mlen 10
+ rlen 0
+ { align1 EOT };
+
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+
diff --git a/src/render_program/exa_wm_write.g4b b/src/render_program/exa_wm_write.g4b
new file mode 100644
index 0000000..92e7b24
--- /dev/null
+++ b/src/render_program/exa_wm_write.g4b
@@ -0,0 +1,18 @@
+ { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 },
+ { 0x00600001, 0x206003be, 0x008d0200, 0x00000000 },
+ { 0x00600001, 0x208003be, 0x008d0240, 0x00000000 },
+ { 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 },
+ { 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 },
+ { 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 },
+ { 0x00601001, 0x210003be, 0x008d0260, 0x00000000 },
+ { 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 },
+ { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
+ { 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_wm_xy.g4a b/src/render_program/exa_wm_xy.g4a
new file mode 100644
index 0000000..e99f5ac
--- /dev/null
+++ b/src/render_program/exa_wm_xy.g4a
@@ -0,0 +1,52 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang at intel.com>
+ * Keith Packard <keithp at keithp.com>
+ */
+
+/*
+ * Register assignments:
+ *
+ * x g6/g7
+ * y g8/g9
+ *
+ * temp x g10/g11
+ * temp y g12/g13
+ *
+ * src w g14/g15
+ * src u m1/m2
+ * src v m3/m4
+ */
+
+/* Fragment to compute per-pixel XY values */
+
+include(`exa_wm.g4i')
+
+ /* Load X and Y coordinates and compute per-pixel coordinates */
+add (16) temp_x_uw<1>UW dst_x_uw 0x10101010V { align1 };
+add (16) temp_y_uw<1>UW dst_y_uw 0x11001100V { align1 };
+
+ /* subtract screen-space origin of vertex 0 */
+add (16) dst_x<1>F temp_x_uw<8,8,1>UW -screen_x0 { compr align1 };
+add (16) dst_y<1>F temp_y_uw<8,8,1>UW -screen_y0 { compr align1 };
diff --git a/src/render_program/exa_wm_xy.g4b b/src/render_program/exa_wm_xy.g4b
new file mode 100644
index 0000000..327fc29
--- /dev/null
+++ b/src/render_program/exa_wm_xy.g4b
@@ -0,0 +1,4 @@
+ { 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 },
+ { 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 },
+ { 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 },
+ { 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 },
diff --git a/src/render_program/exa_wm_yuv_rgb.g4a b/src/render_program/exa_wm_yuv_rgb.g4a
new file mode 100644
index 0000000..4fb2576
--- /dev/null
+++ b/src/render_program/exa_wm_yuv_rgb.g4a
@@ -0,0 +1,98 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Keith Packard <keithp at keithp.com>
+ * Eric Anholt <eric at anholt.net>
+ *
+ */
+
+include(`exa_wm.g4i')
+
+define(`YCbCr_base', `src_sample_base')
+
+define(`Cr', `src_sample_r')
+define(`Cr_01', `src_sample_r_01')
+define(`Cr_23', `src_sample_r_23')
+
+define(`Y', `src_sample_g')
+define(`Y_01', `src_sample_g_01')
+define(`Y_23', `src_sample_g_23')
+
+define(`Cb', `src_sample_b')
+define(`Cb_01', `src_sample_b_01')
+define(`Cb_23', `src_sample_b_23')
+
+define(`Crn', `mask_sample_r')
+define(`Crn_01', `mask_sample_r_01')
+define(`Crn_23', `mask_sample_r_23')
+
+define(`Yn', `mask_sample_g')
+define(`Yn_01', `mask_sample_g_01')
+define(`Yn_23', `mask_sample_g_23')
+
+define(`Cbn', `mask_sample_b')
+define(`Cbn_01', `mask_sample_b_01')
+define(`Cbn_23', `mask_sample_b_23')
+
+ /* color space conversion function:
+ * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1)
+ * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1)
+ * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1)
+ */
+
+ /* Normalize Y, Cb and Cr:
+ *
+ * Yn = (Y - 16/255) * 1.164
+ * Crn = Cr - 128 / 255
+ * Cbn = Cb - 128 / 255
+ */
+add (16) Yn<1>F Y<8,8,1>F -0.0627451F { compr align1 };
+mul (16) Yn<1>F Yn<8,8,1>F 1.164F { compr align1 };
+
+add (16) Crn<1>F Cr<8,8,1>F -0.501961F { compr align1 };
+
+add (16) Cbn<1>F Cb<8,8,1>F -0.501961F { compr align1 };
+
+ /*
+ * R = Y + Cr * 1.596
+ */
+mov (16) acc0<1>F Yn<8,8,1>F { compr align1 };
+mac.sat(16) src_sample_r<1>F Crn<8,8,1>F 1.596F { compr align1 };
+
+ /*
+ * G = Crn * -0.813 + Cbn * -0.392 + Y
+ */
+mov (16) acc0<1>F Yn<8,8,1>F { compr align1 };
+mac (16) acc0<1>F Crn<8,8,1>F -0.813F { compr align1 };
+mac.sat(16) src_sample_g<1>F Cbn<8,8,1>F -0.392F { compr align1 };
+
+ /*
+ * B = Cbn * 2.017 + Y
+ */
+mov (16) acc0<1>F Yn<8,8,1>F { compr align1 };
+mac.sat(16) src_sample_b<1>F Cbn<8,8,1>F 2.017F { compr align1 };
+
+ /*
+ * A = 1.0
+ */
+mov (16) src_sample_a<1>F 1.0F { compr align1 };
diff --git a/src/render_program/exa_wm_yuv_rgb.g4b b/src/render_program/exa_wm_yuv_rgb.g4b
new file mode 100644
index 0000000..01f6e2b
--- /dev/null
+++ b/src/render_program/exa_wm_yuv_rgb.g4b
@@ -0,0 +1,12 @@
+ { 0x00802040, 0x23007fbd, 0x008d0200, 0xbd808081 },
+ { 0x00802041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 },
+ { 0x00802040, 0x22c07fbd, 0x008d01c0, 0xbf008084 },
+ { 0x00802040, 0x23407fbd, 0x008d0240, 0xbf008084 },
+ { 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 },
+ { 0x80802048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba },
+ { 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 },
+ { 0x00802048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 },
+ { 0x80802048, 0x22007fbd, 0x008d0340, 0xbec8b439 },
+ { 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 },
+ { 0x80802048, 0x22407fbd, 0x008d0340, 0x40011687 },
+ { 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 },
diff --git a/src/render_program/packed_yuv_sf.g4a b/src/render_program/packed_yuv_sf.g4a
new file mode 100644
index 0000000..5a02399
--- /dev/null
+++ b/src/render_program/packed_yuv_sf.g4a
@@ -0,0 +1,45 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Keith Packard <keithp at keithp.com>
+ * Eric Anholt <eric at anholt.net>
+ *
+ */
+
+send (1) 0 g6<1>F g1.12<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
+send (1) 0 g6.4<1>F g1.20<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
+add (8) g7<1>F g4<8,8,1>F -g3<8,8,1>F { align1 };
+mul (1) g7<1>F g7<0,1,0>F g6<0,1,0>F { align1 };
+mul (1) g7.4<1>F g7.4<0,1,0>F g6.4<0,1,0>F { align1 };
+mov (8) m1<1>F g7<0,1,0>F { align1 };
+mov (8) m2<1>F g7.4<0,1,0>F { align1 };
+mov (8) m3<1>F g3<8,8,1>F { align1 };
+send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
diff --git a/src/render_program/packed_yuv_sf.g4b b/src/render_program/packed_yuv_sf.g4b
new file mode 100644
index 0000000..830d176
--- /dev/null
+++ b/src/render_program/packed_yuv_sf.g4b
@@ -0,0 +1,17 @@
+ { 0x00000031, 0x20c01fbd, 0x0000002c, 0x01110081 },
+ { 0x00000031, 0x20c41fbd, 0x00000034, 0x01110081 },
+ { 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
+ { 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
+ { 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
+ { 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
+ { 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
+ { 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
+ { 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/packed_yuv_wm.g4a b/src/render_program/packed_yuv_wm.g4a
new file mode 100644
index 0000000..2be52b5
--- /dev/null
+++ b/src/render_program/packed_yuv_wm.g4a
@@ -0,0 +1,221 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Keith Packard <keithp at keithp.com>
+ * Eric Anholt <eric at anholt.net>
+ *
+ */
+
+include(`exa_wm.g4i')
+
+define(`YCbCr_base', `g12')
+define(`Cr', `g12')
+define(`Cr_01', `g12')
+define(`Cr_23', `g13')
+define(`Y', `g14')
+define(`Y_01', `g14')
+define(`Y_23', `g15')
+define(`Cb', `g16')
+define(`Cb_01', `g16')
+define(`Cb_23', `g17')
+
+/* The initial payload of the thread is always g0.
+ * WM_URB (incoming URB entries) is g3
+ * X0_R is g4
+ * X1_R is g5
+ * Y0_R is g6
+ * Y1_R is g7
+ */
+
+ /* Set up the X/Y screen coordinates of the pixels in our 4 subspans. Each
+ * subspan is a 2x2 rectangle, and the screen x/y of the upper left of each
+ * subspan are given in GRF register 1.2 through 1.5 (which, with the word
+ * addressing below, are 1.4 through 1.11).
+ *
+ * The result is WM_X*_R and WM_Y*R being:
+ *
+ * X0: {ss0.x, ss0.x+1, ss0.x, ss0.x+1, ss1.x, ss1.x+1, ss1.x, ss1.x+y}
+ * Y0: {ss0.y, ss0.y, ss0.y+1, ss0.y+1, ss1.y, ss1.y, ss1.y+1, ss1.y+1}
+ * X1: {ss2.x, ss2.x+1, ss2.x, ss2.x+1, ss3.x, ss3.x+1, ss3.x, ss3.x+y}
+ * Y1: {ss2.y, ss2.y, ss2.y+1, ss2.y+1, ss3.y, ss3.y, ss3.y+1, ss3.y+1}
+ */
+
+ /* Set up ss0.x coordinates*/
+mov (1) g4<1>F g1.8<0,1,0>UW { align1 };
+add (1) g4.4<1>F g1.8<0,1,0>UW 1UD { align1 };
+mov (1) g4.8<1>F g1.8<0,1,0>UW { align1 };
+add (1) g4.12<1>F g1.8<0,1,0>UW 1UD { align1 };
+ /* Set up ss0.y coordinates */
+mov (1) g6<1>F g1.10<0,1,0>UW { align1 };
+mov (1) g6.4<1>F g1.10<0,1,0>UW { align1 };
+add (1) g6.8<1>F g1.10<0,1,0>UW 1UD { align1 };
+add (1) g6.12<1>F g1.10<0,1,0>UW 1UD { align1 };
+ /* set up ss1.x coordinates */
+mov (1) g4.16<1>F g1.12<0,1,0>UW { align1 };
+add (1) g4.20<1>F g1.12<0,1,0>UW 1UD { align1 };
+mov (1) g4.24<1>F g1.12<0,1,0>UW { align1 };
+add (1) g4.28<1>F g1.12<0,1,0>UW 1UD { align1 };
+ /* set up ss1.y coordinates */
+mov (1) g6.16<1>F g1.14<0,1,0>UW { align1 };
+mov (1) g6.20<1>F g1.14<0,1,0>UW { align1 };
+add (1) g6.24<1>F g1.14<0,1,0>UW 1UD { align1 };
+add (1) g6.28<1>F g1.14<0,1,0>UW 1UD { align1 };
+ /* Set up ss2.x coordinates */
+mov (1) g5<1>F g1.16<0,1,0>UW { align1 };
+add (1) g5.4<1>F g1.16<0,1,0>UW 1UD { align1 };
+mov (1) g5.8<1>F g1.16<0,1,0>UW { align1 };
+add (1) g5.12<1>F g1.16<0,1,0>UW 1UD { align1 };
+ /* Set up ss2.y coordinates */
+mov (1) g7<1>F g1.18<0,1,0>UW { align1 };
+mov (1) g7.4<1>F g1.18<0,1,0>UW { align1 };
+add (1) g7.8<1>F g1.18<0,1,0>UW 1UD { align1 };
+add (1) g7.12<1>F g1.18<0,1,0>UW 1UD { align1 };
+ /* Set up ss3.x coordinates */
+mov (1) g5.16<1>F g1.20<0,1,0>UW { align1 };
+add (1) g5.20<1>F g1.20<0,1,0>UW 1UD { align1 };
+mov (1) g5.24<1>F g1.20<0,1,0>UW { align1 };
+add (1) g5.28<1>F g1.20<0,1,0>UW 1UD { align1 };
+ /* Set up ss3.y coordinates */
+mov (1) g7.16<1>F g1.22<0,1,0>UW { align1 };
+mov (1) g7.20<1>F g1.22<0,1,0>UW { align1 };
+add (1) g7.24<1>F g1.22<0,1,0>UW 1UD { align1 };
+add (1) g7.28<1>F g1.22<0,1,0>UW 1UD { align1 };
+
+ /* Now, map these screen space coordinates into texture coordinates. */
+ /* subtract screen-space X origin of vertex 0. */
+add (8) g4<1>F g4<8,8,1>F -g1<0,1,0>F { align1 };
+add (8) g5<1>F g5<8,8,1>F -g1<0,1,0>F { align1 };
+ /* scale by texture X increment */
+mul (8) g4<1>F g4<8,8,1>F g3<0,1,0>F { align1 };
+mul (8) g5<1>F g5<8,8,1>F g3<0,1,0>F { align1 };
+ /* add in texture X offset */
+add (8) g4<1>F g4<8,8,1>F g3.12<0,1,0>F { align1 };
+add (8) g5<1>F g5<8,8,1>F g3.12<0,1,0>F { align1 };
+ /* subtract screen-space Y origin of vertex 0. */
+add (8) g6<1>F g6<8,8,1>F -g1.4<0,1,0>F { align1 };
+add (8) g7<1>F g7<8,8,1>F -g1.4<0,1,0>F { align1 };
+ /* scale by texture Y increment */
+mul (8) g6<1>F g6<8,8,1>F g3.20<0,1,0>F { align1 };
+mul (8) g7<1>F g7<8,8,1>F g3.20<0,1,0>F { align1 };
+ /* add in texture Y offset */
+add (8) g6<1>F g6<8,8,1>F g3.28<0,1,0>F { align1 };
+add (8) g7<1>F g7<8,8,1>F g3.28<0,1,0>F { align1 };
+ /* sampler */
+mov (8) m1<1>F g4<8,8,1>F { align1 };
+mov (8) m2<1>F g5<8,8,1>F { align1 };
+mov (8) m3<1>F g6<8,8,1>F { align1 };
+mov (8) m4<1>F g7<8,8,1>F { align1 };
+
+ /*
+ * g0 holds the PS thread payload, which (oddly) contains
+ * precisely what the sampler wants to see in m0
+ */
+send (16)
+ 0 /* load g0 to m0 */
+ YCbCr_base<1>UW
+ g0<8,8,1>UW
+ sampler (1,0,F)
+ mlen 5 rlen 8 { align1 };
+
+ /* color space conversion function:
+ * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1)
+ * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1)
+ * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1)
+ *
+ * Y is g14, g15.
+ * Cr is g12, g13.
+ * Cb is g16, g17.
+ *
+ * R is g2, g6.
+ * G is g3, g7.
+ * B is g4, g8.
+ */
+
+ /* Normalize Y, Cb and Cr:
+ *
+ * Y = (Y - 16/255) * 1.164
+ * Cr = Cr - 128 / 255
+ * Cb = Cb - 128 / 255
+ */
+add (16) Y<1>F Y<8,8,1>F -0.0627451F { compr align1 };
+mul (16) Y<1>F Y<8,8,1>F 1.164F { compr align1 };
+
+add (16) Cr<1>F Cr<8,8,1>F -0.501961F { compr align1 };
+
+add (16) Cb<1>F Cb<8,8,1>F -0.501961F { compr align1 };
+
+ /*
+ * R = Y + Cr * 1.596
+ */
+mul (8) null Cr_01<8,8,1>F 1.596F { align1 };
+mac.sat (8) data_port_r_01<1>F Y_01<8,8,1>F 1F { align1 };
+mul (8) null Cr_23<8,8,1>F 1.596F { align1 };
+mac.sat (8) data_port_r_23<1>F Y_23<8,8,1>F 1F { align1 };
+
+ /*
+ * G = Cr * -0.813 + Cb * -0.392 + Y
+ */
+mul (8) null Cr_01<8,8,1>F -0.813F { align1 };
+mac (8) null Cb_01<8,8,1>F -0.392F { align1 };
+mac.sat (8) data_port_g_01<1>F Y_01<8,8,1>F 1F { align1 };
+mul (8) null Cr_23<8,8,1>F -0.813F { align1 };
+mac (8) null Cb_23<8,8,1>F -0.392F { align1 };
+mac.sat (8) data_port_g_23<1>F Y_23<8,8,1>F 1F { align1 };
+
+ /*
+ * B = Cb * 2.017 + Y
+ */
+mul (8) null Cb_01<8,8,1>F 2.017F { align1 };
+mac.sat (8) data_port_b_01<1>F Y_01<8,8,1>F 1F { align1 };
+mul (8) null Cb_23<8,8,1>F 2.017F { align1 };
+mac.sat (8) data_port_b_23<1>F Y_23<8,8,1>F 1F { align1 };
+
+ /*
+ * A = 1.0
+ */
+mov (8) data_port_a_01<1>F 1.0F { align1 };
+mov (8) data_port_a_23<1>F 1.0F { align1 };
+
+ /*
+ * Pass through control information:
+ */
+mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
+
+ /*
+ * Send framebuffer write message: XXX: acc0?
+ */
+send (16) 0 acc0<1>UW g0<8,8,1>UW write (
+ 0, /* binding table index 0 */
+ 8, /* pixel scoreboard clear */
+ 4, /* render target write */
+ 0 /* no write commit message */
+ ) mlen 10 rlen 0 { align1 EOT };
+ /* padding */
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
diff --git a/src/render_program/packed_yuv_wm.g4b b/src/render_program/packed_yuv_wm.g4b
new file mode 100644
index 0000000..f2e650a
--- /dev/null
+++ b/src/render_program/packed_yuv_wm.g4b
@@ -0,0 +1,79 @@
+ { 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
+ { 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
+ { 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
+ { 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
+ { 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
+ { 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
+ { 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
+ { 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
+ { 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
+ { 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
+ { 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
+ { 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
+ { 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
+ { 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
+ { 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
+ { 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
+ { 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
+ { 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
+ { 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
+ { 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
+ { 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
+ { 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
+ { 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
+ { 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
+ { 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
+ { 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
+ { 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
+ { 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
+ { 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
+ { 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
+ { 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
+ { 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
+ { 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
+ { 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
+ { 0x00600041, 0x208077bd, 0x008d0080, 0x00000060 },
+ { 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000060 },
+ { 0x00600040, 0x208077bd, 0x008d0080, 0x0000006c },
+ { 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000006c },
+ { 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
+ { 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
+ { 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000074 },
+ { 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000074 },
+ { 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000007c },
+ { 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000007c },
+ { 0x00600001, 0x202003be, 0x008d0080, 0x00000000 },
+ { 0x00600001, 0x204003be, 0x008d00a0, 0x00000000 },
+ { 0x00600001, 0x206003be, 0x008d00c0, 0x00000000 },
+ { 0x00600001, 0x208003be, 0x008d00e0, 0x00000000 },
+ { 0x00800031, 0x21801d29, 0x008d0000, 0x02580001 },
+ { 0x00802040, 0x21c07fbd, 0x008d01c0, 0xbd808081 },
+ { 0x00802041, 0x21c07fbd, 0x008d01c0, 0x3f94fdf4 },
+ { 0x00802040, 0x21807fbd, 0x008d0180, 0xbf008084 },
+ { 0x00802040, 0x22007fbd, 0x008d0200, 0xbf008084 },
+ { 0x00600041, 0x20007fbc, 0x008d0180, 0x3fcc49ba },
+ { 0x80600048, 0x20407fbe, 0x008d01c0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d01a0, 0x3fcc49ba },
+ { 0x80600048, 0x20c07fbe, 0x008d01e0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d0180, 0xbf5020c5 },
+ { 0x00600048, 0x20007fbc, 0x008d0200, 0xbec8b439 },
+ { 0x80600048, 0x20607fbe, 0x008d01c0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d01a0, 0xbf5020c5 },
+ { 0x00600048, 0x20007fbc, 0x008d0220, 0xbec8b439 },
+ { 0x80600048, 0x20e07fbe, 0x008d01e0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d0200, 0x40011687 },
+ { 0x80600048, 0x20807fbe, 0x008d01c0, 0x3f800000 },
+ { 0x00600041, 0x20007fbc, 0x008d0220, 0x40011687 },
+ { 0x80600048, 0x21007fbe, 0x008d01e0, 0x3f800000 },
+ { 0x00600001, 0x20a003fe, 0x00000000, 0x3f800000 },
+ { 0x00600001, 0x212003fe, 0x00000000, 0x3f800000 },
+ { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
+ { 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
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