xf86-video-intel: 6 commits - src/common.h src/i810_driver.c src/i810_reg.h src/i830_debug.c src/i830_driver.c src/i830.h src/i830_uxa.c src/reg_dumper/gtt.c
Zhenyu Wang
zhen at kemper.freedesktop.org
Tue Jun 9 19:49:23 PDT 2009
src/common.h | 27 +-
src/i810_driver.c | 6
src/i810_reg.h | 492 ++++++++++++++++++++++++++++++++++++++++
src/i830.h | 1
src/i830_debug.c | 615 ++++++++++++++++++++++++++++++++++++++++++++++++++-
src/i830_driver.c | 24 +
src/i830_uxa.c | 8
src/reg_dumper/gtt.c | 2
8 files changed, 1149 insertions(+), 26 deletions(-)
New commits:
commit 88da9b48737229b305da4423e9aa43a09ccdcfac
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Wed Jun 10 10:45:51 2009 +0800
Add new chipset register dumps
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/i830_debug.c b/src/i830_debug.c
index f070978..1126c26 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -128,18 +128,42 @@ DEBUGSTRING(i830_debug_dspcntr)
{
char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A';
- return XNFprintf("%s, pipe %c", enabled, plane);
+ if (IS_IGDNG(pI830))
+ return XNFprintf("%s", enabled);
+ else
+ return XNFprintf("%s, pipe %c", enabled, plane);
}
DEBUGSTRING(i830_debug_pipeconf)
{
char *enabled = val & PIPEACONF_ENABLE ? "enabled" : "disabled";
char *bit30;
+ char *bpc = NULL;
if (IS_I965G(pI830))
bit30 = val & I965_PIPECONF_ACTIVE ? "active" : "inactive";
else
bit30 = val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
- return XNFprintf("%s, %s", enabled, bit30);
+
+ if (IS_IGDNG(pI830)) {
+ switch (val & (7<<5)) {
+ case PIPECONF_8BPP:
+ bpc = "8bpc";
+ break;
+ case PIPECONF_10BPP:
+ bpc = "10bpc";
+ break;
+ case PIPECONF_6BPP:
+ bpc = "6bpc";
+ break;
+ case PIPECONF_12BPP:
+ bpc = "12bpc";
+ break;
+ }
+ }
+ if (IS_IGDNG(pI830))
+ return XNFprintf("%s, %s, %s", enabled, bit30, bpc);
+ else
+ return XNFprintf("%s, %s", enabled, bit30);
}
DEBUGSTRING(i830_debug_pipestat)
@@ -387,8 +411,12 @@ DEBUGSTRING(i830_debug_adpa)
char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-';
char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-';
- return XNFprintf("%s, pipe %c, %chsync, %cvsync",
- enable, pipe, hsync, vsync);
+ if (IS_IGDNG(pI830))
+ return XNFprintf("%s, transcoder %c, %chsync, %cvsync",
+ enable, pipe, hsync, vsync);
+ else
+ return XNFprintf("%s, pipe %c, %chsync, %cvsync",
+ enable, pipe, hsync, vsync);
}
DEBUGSTRING(i830_debug_lvds)
@@ -580,12 +608,14 @@ DEBUGSTRING(i810_debug_965_fence_end)
#define DEFINEREG2(reg, func) \
{ reg, #reg, func, 0 }
-static struct i830SnapshotRec {
+struct i830SnapshotRec {
int reg;
char *name;
char *(*debug_output)(I830Ptr pI830, int reg, uint32_t val);
uint32_t val;
-} i830_snapshot[] = {
+};
+
+static struct i830SnapshotRec i830_snapshot[] = {
DEFINEREG2(DCC, i830_debug_dcc),
DEFINEREG2(CHDECMISC, i830_debug_chdecmisc),
DEFINEREG_16BIT(C0DRB0),
@@ -820,17 +850,551 @@ static struct i830SnapshotRec {
DEFINEFENCE_965(14),
DEFINEFENCE_965(15),
};
-#undef DEFINEREG
#define NUM_I830_SNAPSHOTREGS (sizeof(i830_snapshot) / sizeof(i830_snapshot[0]))
+DEBUGSTRING(igdng_debug_rr_hw_ctl)
+{
+ return XNFprintf("low %d, high %d", val & RR_HW_LOW_POWER_FRAMES_MASK,
+ (val & RR_HW_HIGH_POWER_FRAMES_MASK) >> 8 );
+}
+
+DEBUGSTRING(igdng_debug_m_tu)
+{
+ return XNFprintf("TU %d, val 0x%x %d", (val >> 25) + 1, val & 0xffffff, val & 0xffffff);
+}
+
+DEBUGSTRING(igdng_debug_n)
+{
+ return XNFprintf("val 0x%x %d", val & 0xffffff, val & 0xffffff);
+}
+
+DEBUGSTRING(igdng_debug_fdi_tx_ctl)
+{
+ char *train = NULL, *voltage = NULL, *pre_emphasis = NULL, *portw = NULL;
+
+ switch (val & FDI_LINK_TRAIN_NONE) {
+ case FDI_LINK_TRAIN_PATTERN_1:
+ train = "pattern_1";
+ break;
+ case FDI_LINK_TRAIN_PATTERN_2:
+ train = "pattern_2";
+ break;
+ case FDI_LINK_TRAIN_PATTERN_IDLE:
+ train = "pattern_idle";
+ break;
+ case FDI_LINK_TRAIN_NONE:
+ train = "not train";
+ break;
+ }
+
+ switch (val & (7<<25)) {
+ case FDI_LINK_TRAIN_VOLTAGE_0_4V:
+ voltage = "0.4V";
+ break;
+ case FDI_LINK_TRAIN_VOLTAGE_0_6V:
+ voltage = "0.6V";
+ break;
+ case FDI_LINK_TRAIN_VOLTAGE_0_8V:
+ voltage = "0.8V";
+ break;
+ case FDI_LINK_TRAIN_VOLTAGE_1_2V:
+ voltage = "1.2V";
+ break;
+ default:
+ voltage = "reserved";
+ }
+
+ switch (val & (7<<22)) {
+ case FDI_LINK_TRAIN_PRE_EMPHASIS_NONE:
+ pre_emphasis = "none";
+ break;
+ case FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X:
+ pre_emphasis = "1.5x";
+ break;
+ case FDI_LINK_TRAIN_PRE_EMPHASIS_2X:
+ pre_emphasis = "2x";
+ break;
+ case FDI_LINK_TRAIN_PRE_EMPHASIS_3X:
+ pre_emphasis = "3x";
+ break;
+ default:
+ pre_emphasis = "reserved";
+ }
+
+ switch (val & (7<<19)) {
+ case FDI_DP_PORT_WIDTH_X1:
+ portw = "X1";
+ break;
+ case FDI_DP_PORT_WIDTH_X2:
+ portw = "X2";
+ break;
+ case FDI_DP_PORT_WIDTH_X3:
+ portw = "X3";
+ break;
+ case FDI_DP_PORT_WIDTH_X4:
+ portw = "X4";
+ break;
+ }
+
+ return XNFprintf("%s, train pattern %s, voltage swing %s,"
+ "pre-emphasis %s, port width %s, enhanced framing %s, FDI PLL %s, scrambing %s, master mode %s",
+ val & FDI_TX_ENABLE ? "enable" : "disable",
+ train, voltage, pre_emphasis, portw,
+ val & FDI_TX_ENHANCE_FRAME_ENABLE ? "enable" : "disable",
+ val & FDI_TX_PLL_ENABLE ? "enable" : "disable",
+ val & (1 << 7) ? "disable" : "enable",
+ val & (1 << 0) ? "enable" : "disable");
+}
+
+DEBUGSTRING(igdng_debug_fdi_rx_ctl)
+{
+ char *train = NULL, *portw = NULL, *bpc = NULL;
+
+ switch (val & FDI_LINK_TRAIN_NONE) {
+ case FDI_LINK_TRAIN_PATTERN_1:
+ train = "pattern_1";
+ break;
+ case FDI_LINK_TRAIN_PATTERN_2:
+ train = "pattern_2";
+ break;
+ case FDI_LINK_TRAIN_PATTERN_IDLE:
+ train = "pattern_idle";
+ break;
+ case FDI_LINK_TRAIN_NONE:
+ train = "not train";
+ break;
+ }
+
+ switch (val & (7<<19)) {
+ case FDI_DP_PORT_WIDTH_X1:
+ portw = "X1";
+ break;
+ case FDI_DP_PORT_WIDTH_X2:
+ portw = "X2";
+ break;
+ case FDI_DP_PORT_WIDTH_X3:
+ portw = "X3";
+ break;
+ case FDI_DP_PORT_WIDTH_X4:
+ portw = "X4";
+ break;
+ }
+
+ switch (val & (7<<16)) {
+ case FDI_8BPC:
+ bpc = "8bpc";
+ break;
+ case FDI_10BPC:
+ bpc = "10bpc";
+ break;
+ case FDI_6BPC:
+ bpc = "6bpc";
+ break;
+ case FDI_12BPC:
+ bpc = "12bpc";
+ break;
+ }
+
+ return XNFprintf("%s, train pattern %s, port width %s, %s,"
+ "link_reverse_strap_overwrite %s, dmi_link_reverse %s, FDI PLL %s,"
+ "FS ecc %s, FE ecc %s, FS err report %s, FE err report %s,"
+ "scrambing %s, enhanced framing %s, %s",
+ val & FDI_RX_ENABLE ? "enable" : "disable",
+ train, portw, bpc,
+ val & FDI_LINK_REVERSE_OVERWRITE ? "yes" : "no",
+ val & FDI_DMI_LINK_REVERSE_MASK ? "yes" : "no",
+ val & FDI_RX_PLL_ENABLE ? "enable" : "disable",
+ val & FDI_FS_ERR_CORRECT_ENABLE ? "enable" : "disable",
+ val & FDI_FE_ERR_CORRECT_ENABLE ? "enable" : "disable",
+ val & FDI_FS_ERR_REPORT_ENABLE ? "enable" : "disable",
+ val & FDI_FE_ERR_REPORT_ENABLE ? "enable" : "disable",
+ val & (1 << 7) ? "disable" : "enable",
+ val & FDI_RX_ENHANCE_FRAME_ENABLE ? "enable" : "disable",
+ val & FDI_SEL_PCDCLK ? "PCDClk" : "RawClk");
+}
+
+DEBUGSTRING(igdng_debug_dspstride)
+{
+ return XNFprintf("%d", val >> 6);
+}
+
+DEBUGSTRING(igdng_debug_pch_dpll)
+{
+ char *enable = val & DPLL_VCO_ENABLE ? "enable" : "disable";
+ char *highspeed = val & DPLL_DVO_HIGH_SPEED ? "yes" : "no";
+ char *mode = NULL;
+ char *p2 = NULL;
+ int fpa0_p1, fpa1_p1;
+ char *refclk = NULL;
+ int sdvo_mul;
+
+ if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_LVDS) {
+ mode = "LVDS";
+ if (val & DPLLB_LVDS_P2_CLOCK_DIV_7)
+ p2 = "Div 7";
+ else
+ p2 = "Div 14";
+ } else if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_DAC_SERIAL) {
+ mode = "Non-LVDS";
+ if (val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
+ p2 = "Div 5";
+ else
+ p2 = "Div 10";
+ }
+ fpa0_p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> 16);
+ fpa1_p1 = ffs((val & DPLL_FPA1_P1_POST_DIV_MASK));
+
+ switch (val & PLL_REF_INPUT_MASK) {
+ case PLL_REF_INPUT_DREFCLK:
+ refclk = "default 120Mhz";
+ break;
+ case PLL_REF_INPUT_SUPER_SSC:
+ refclk = "SuperSSC 120Mhz";
+ break;
+ case PLL_REF_INPUT_TVCLKINBC:
+ refclk = "SDVO TVClkIn";
+ break;
+ case PLLB_REF_INPUT_SPREADSPECTRUMIN:
+ refclk = "SSC";
+ break;
+ case PLL_REF_INPUT_DMICLK:
+ refclk = "DMI RefCLK";
+ break;
+ }
+
+ sdvo_mul = ((val & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) >> 9) + 1;
+
+ return XNFprintf("%s, sdvo high speed %s, mode %s, p2 %s, "
+ "FPA0 P1 %d, FPA1 P1 %d, refclk %s, sdvo/hdmi mul %d",
+ enable, highspeed, mode, p2, fpa0_p1, fpa1_p1, refclk, sdvo_mul);
+}
+
+DEBUGSTRING(igdng_debug_dref_ctl)
+{
+ char *cpu_source;
+ char *ssc_source = val & DREF_SSC_SOURCE_ENABLE ? "enable" : "disable";
+ char *nonspread_source = val & DREF_NONSPREAD_SOURCE_ENABLE ? "enable":"disable";
+ char *superspread_source = val & DREF_SUPERSPREAD_SOURCE_ENABLE ? "enable":"disable";
+ char *ssc4_mode = val & DREF_SSC4_CENTERSPREAD ? "centerspread" : "downspread";
+ char *ssc1 = val & DREF_SSC1_ENABLE ? "enable" : "disable";
+ char *ssc4 = val & DREF_SSC4_ENABLE ? "enable" : "disable";
+
+ switch (val & DREF_CPU_SOURCE_OUTPUT_NONSPREAD) {
+ case DREF_CPU_SOURCE_OUTPUT_DISABLE:
+ cpu_source = "disable";
+ break;
+ case DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD:
+ cpu_source = "downspread";
+ break;
+ case DREF_CPU_SOURCE_OUTPUT_NONSPREAD:
+ cpu_source = "nonspread";
+ break;
+ default:
+ cpu_source = "reserved";
+ }
+ return XNFprintf("cpu source %s, ssc_source %s, nonspread_source %s, "
+ "superspread_source %s, ssc4_mode %s, ssc1 %s, ssc4 %s",
+ cpu_source, ssc_source, nonspread_source, superspread_source,
+ ssc4_mode, ssc1, ssc4);
+}
+
+DEBUGSTRING(igdng_debug_rawclk_freq)
+{
+ char *tp1 = NULL, *tp2 = NULL;
+
+ switch (val & FDL_TP1_TIMER_MASK) {
+ case 0:
+ tp1 = "0.5us";
+ break;
+ case (1 << 12):
+ tp1 = "1.0us";
+ break;
+ case (2 << 12):
+ tp1 = "2.0us";
+ break;
+ case (3 << 12):
+ tp1 = "4.0us";
+ break;
+ }
+ switch (val & FDL_TP2_TIMER_MASK) {
+ case 0:
+ tp2 = "1.5us";
+ break;
+ case (1 << 10):
+ tp2 = "3.0us";
+ break;
+ case (2 << 10):
+ tp2 = "6.0us";
+ break;
+ case (3 << 10):
+ tp2 = "12.0us";
+ break;
+ }
+ return XNFprintf("FDL_TP1 timer %s, FDL_TP2 timer %s, freq %d",
+ tp1, tp2, val & RAWCLK_FREQ_MASK);
+
+}
+
+DEBUGSTRING(igdng_debug_fdi_rx_misc)
+{
+ return XNFprintf("FDI Delay %d", val & ((1 << 13) - 1));
+}
+
+DEBUGSTRING(igdng_debug_transconf)
+{
+ return XNFprintf("%s, %s",
+ val & TRANS_ENABLE ? "enable" : "disable",
+ val & TRANS_STATE_ENABLE ? "active" : "inactive");
+}
+
+DEBUGSTRING(igdng_debug_panel_fitting)
+{
+ char *vadapt = NULL, *filter_sel = NULL;
+
+ switch (val & (3 << 25)) {
+ case 0:
+ vadapt = "least";
+ break;
+ case (1<<25):
+ vadapt = "moderate";
+ break;
+ case (2<<25):
+ vadapt = "reserved";
+ break;
+ case (3<<25):
+ vadapt = "most";
+ break;
+ }
+
+ switch (val & (3 << 23)) {
+ case 0:
+ filter_sel = "programmed";
+ break;
+ case (1<<25):
+ filter_sel = "hardcoded";
+ break;
+ case (2<<25):
+ filter_sel = "edge_enhance";
+ break;
+ case (3<<25):
+ filter_sel = "edge_soften";
+ break;
+ }
+
+ return XNFprintf("%s, auto_scale %s, auto_scale_cal %s, v_filter %s, vadapt %s, mode %s, filter_sel %s,"
+ "chroma pre-filter %s, vert3tap %s, v_inter_invert %s",
+ val & PF_ENABLE ? "enable" : "disable",
+ val & (1 << 30) ? "no" : "yes",
+ val & (1 << 29) ? "yes" : "no",
+ val & (1 << 28) ? "bypass" : "enable",
+ val & (1 << 27) ? "enable" : "disable",
+ vadapt, filter_sel,
+ val & (1 << 22) ? "enable" : "disable",
+ val & (1 << 21) ? "force" : "auto",
+ val & (1 << 20) ? "field 0" : "field 1");
+}
+
+static struct i830SnapshotRec igdng_snapshot[] = {
+ DEFINEREG2(CPU_VGACNTRL, i830_debug_vgacntrl),
+ DEFINEREG(DIGITAL_PORT_HOTPLUG_CNTRL),
+
+ DEFINEREG2(RR_HW_CTL, igdng_debug_rr_hw_ctl),
+
+ DEFINEREG(FDI_PLL_BIOS_0),
+ DEFINEREG(FDI_PLL_BIOS_1),
+ DEFINEREG(FDI_PLL_BIOS_2),
+
+ DEFINEREG(DISPLAY_PORT_PLL_BIOS_0),
+ DEFINEREG(DISPLAY_PORT_PLL_BIOS_1),
+ DEFINEREG(DISPLAY_PORT_PLL_BIOS_2),
+
+ DEFINEREG(FDI_PLL_FREQ_CTL),
+
+ DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
+
+ DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
+ DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
+ DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
+ DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
+ DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
+ DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
+ DEFINEREG(VSYNCSHIFT_A),
+ DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
+
+ DEFINEREG2(PIPEA_DATA_M1, igdng_debug_m_tu),
+ DEFINEREG2(PIPEA_DATA_N1, igdng_debug_n),
+ DEFINEREG2(PIPEA_DATA_M2, igdng_debug_m_tu),
+ DEFINEREG2(PIPEA_DATA_N2, igdng_debug_n),
+
+ DEFINEREG2(PIPEA_LINK_M1, igdng_debug_n),
+ DEFINEREG2(PIPEA_LINK_N1, igdng_debug_n),
+ DEFINEREG2(PIPEA_LINK_M2, igdng_debug_n),
+ DEFINEREG2(PIPEA_LINK_N2, igdng_debug_n),
+
+ DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
+ DEFINEREG(DSPABASE),
+ DEFINEREG2(DSPASTRIDE, igdng_debug_dspstride),
+ DEFINEREG(DSPASURF),
+ DEFINEREG2(DSPATILEOFF, i830_debug_xy),
+
+ DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
+
+ DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
+ DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
+ DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
+ DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
+ DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
+ DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
+ DEFINEREG(VSYNCSHIFT_B),
+
+ DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
+ DEFINEREG(DSPBBASE),
+ DEFINEREG2(DSPBSTRIDE, igdng_debug_dspstride),
+ DEFINEREG(DSPBSURF),
+ DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
+
+ DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
+
+ DEFINEREG2(PIPEB_DATA_M1, igdng_debug_m_tu),
+ DEFINEREG2(PIPEB_DATA_N1, igdng_debug_n),
+ DEFINEREG2(PIPEB_DATA_M2, igdng_debug_m_tu),
+ DEFINEREG2(PIPEB_DATA_N2, igdng_debug_n),
+
+ DEFINEREG2(PIPEB_LINK_M1, igdng_debug_n),
+ DEFINEREG2(PIPEB_LINK_N1, igdng_debug_n),
+ DEFINEREG2(PIPEB_LINK_M2, igdng_debug_n),
+ DEFINEREG2(PIPEB_LINK_N2, igdng_debug_n),
+
+ DEFINEREG2(PFA_CTRL_1, igdng_debug_panel_fitting),
+ DEFINEREG2(PFB_CTRL_1, igdng_debug_panel_fitting),
+
+ /* PCH */
+
+ DEFINEREG2(PCH_DREF_CONTROL, igdng_debug_dref_ctl),
+ DEFINEREG2(PCH_RAWCLK_FREQ, igdng_debug_rawclk_freq),
+ DEFINEREG(PCH_DPLL_TMR_CFG),
+ DEFINEREG(PCH_SSC4_PARMS),
+ DEFINEREG(PCH_SSC4_AUX_PARMS),
+
+ DEFINEREG2(PCH_DPLL_A, igdng_debug_pch_dpll),
+ DEFINEREG2(PCH_DPLL_B, igdng_debug_pch_dpll),
+ DEFINEREG2(PCH_FPA0, i830_debug_fp),
+ DEFINEREG2(PCH_FPA1, i830_debug_fp),
+ DEFINEREG2(PCH_FPB0, i830_debug_fp),
+ DEFINEREG2(PCH_FPB1, i830_debug_fp),
+
+ DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
+ DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
+ DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
+ DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
+ DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
+ DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
+
+ DEFINEREG2(TRANSA_DATA_M1, igdng_debug_m_tu),
+ DEFINEREG2(TRANSA_DATA_N1, igdng_debug_n),
+ DEFINEREG2(TRANSA_DATA_M2, igdng_debug_m_tu),
+ DEFINEREG2(TRANSA_DATA_N2, igdng_debug_n),
+ DEFINEREG2(TRANSA_DP_LINK_M1, igdng_debug_n),
+ DEFINEREG2(TRANSA_DP_LINK_N1, igdng_debug_n),
+ DEFINEREG2(TRANSA_DP_LINK_M2, igdng_debug_n),
+ DEFINEREG2(TRANSA_DP_LINK_N2, igdng_debug_n),
+
+ DEFINEREG2(TRANS_HTOTAL_B, i830_debug_hvtotal),
+ DEFINEREG2(TRANS_HBLANK_B, i830_debug_hvsyncblank),
+ DEFINEREG2(TRANS_HSYNC_B, i830_debug_hvsyncblank),
+ DEFINEREG2(TRANS_VTOTAL_B, i830_debug_hvtotal),
+ DEFINEREG2(TRANS_VBLANK_B, i830_debug_hvsyncblank),
+ DEFINEREG2(TRANS_VSYNC_B, i830_debug_hvsyncblank),
+
+ DEFINEREG2(TRANSB_DATA_M1, igdng_debug_m_tu),
+ DEFINEREG2(TRANSB_DATA_N1, igdng_debug_n),
+ DEFINEREG2(TRANSB_DATA_M2, igdng_debug_m_tu),
+ DEFINEREG2(TRANSB_DATA_N2, igdng_debug_n),
+ DEFINEREG2(TRANSB_DP_LINK_M1, igdng_debug_n),
+ DEFINEREG2(TRANSB_DP_LINK_N1, igdng_debug_n),
+ DEFINEREG2(TRANSB_DP_LINK_M2, igdng_debug_n),
+ DEFINEREG2(TRANSB_DP_LINK_N2, igdng_debug_n),
+
+ DEFINEREG2(TRANSACONF, igdng_debug_transconf),
+ DEFINEREG2(TRANSBCONF, igdng_debug_transconf),
+
+ DEFINEREG2(FDI_TXA_CTL, igdng_debug_fdi_tx_ctl),
+ DEFINEREG2(FDI_TXB_CTL, igdng_debug_fdi_tx_ctl),
+ DEFINEREG2(FDI_RXA_CTL, igdng_debug_fdi_rx_ctl),
+ DEFINEREG2(FDI_RXB_CTL, igdng_debug_fdi_rx_ctl),
+
+ DEFINEREG2(FDI_RXA_MISC, igdng_debug_fdi_rx_misc),
+ DEFINEREG2(FDI_RXB_MISC, igdng_debug_fdi_rx_misc),
+ DEFINEREG(FDI_RXA_TUSIZE1),
+ DEFINEREG(FDI_RXA_TUSIZE2),
+ DEFINEREG(FDI_RXB_TUSIZE1),
+ DEFINEREG(FDI_RXB_TUSIZE2),
+
+ DEFINEREG(FDI_PLL_CTL_1),
+ DEFINEREG(FDI_PLL_CTL_2),
+
+ DEFINEREG(FDI_RXA_IIR),
+ DEFINEREG(FDI_RXA_IMR),
+ DEFINEREG(FDI_RXB_IIR),
+ DEFINEREG(FDI_RXB_IMR),
+
+ DEFINEREG2(PCH_ADPA, i830_debug_adpa),
+ DEFINEREG(HDMIB),
+ DEFINEREG(HDMIC),
+ DEFINEREG(HDMID),
+};
+#define NUM_IGDNG_SNAPSHOTREGS (sizeof(igdng_snapshot) / sizeof(igdng_snapshot[0]))
+#undef DEFINEREG
+
#ifndef REG_DUMPER
void i830TakeRegSnapshot(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int i;
- for (i = 0; i < NUM_I830_SNAPSHOTREGS; i++) {
- i830_snapshot[i].val = INREG(i830_snapshot[i].reg);
+ if (IS_IGDNG(pI830)) {
+ for (i = 0; i < NUM_IGDNG_SNAPSHOTREGS; i++) {
+ igdng_snapshot[i].val = INREG(igdng_snapshot[i].reg);
+ }
+ } else {
+ for (i = 0; i < NUM_I830_SNAPSHOTREGS; i++) {
+ i830_snapshot[i].val = INREG(i830_snapshot[i].reg);
+ }
+ }
+}
+
+static void IGDNGCompareRegsToSnapshot(ScrnInfoPtr pScrn, char *where)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ int i;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Comparing regs from server start up to %s\n", where);
+ for (i = 0; i < NUM_IGDNG_SNAPSHOTREGS; i++) {
+ uint32_t val = INREG(igdng_snapshot[i].reg);
+ if (igdng_snapshot[i].val == val)
+ continue;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Register 0x%x (%s) changed from 0x%08x to 0x%08x\n",
+ igdng_snapshot[i].reg, igdng_snapshot[i].name,
+ (int)igdng_snapshot[i].val, (int)val);
+
+ if (igdng_snapshot[i].debug_output != NULL) {
+ char *before, *after;
+
+ before = igdng_snapshot[i].debug_output(pI830,
+ igdng_snapshot[i].reg,
+ igdng_snapshot[i].val);
+ after = igdng_snapshot[i].debug_output(pI830,
+ igdng_snapshot[i].reg,
+ val);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "%s before: %s\n", igdng_snapshot[i].name, before);
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "%s after: %s\n", igdng_snapshot[i].name, after);
+
+ }
}
}
@@ -839,6 +1403,10 @@ void i830CompareRegsToSnapshot(ScrnInfoPtr pScrn, char *where)
I830Ptr pI830 = I830PTR(pScrn);
int i;
+ if (IS_IGDNG(pI830)) {
+ IGDNGCompareRegsToSnapshot(pScrn, where);
+ return;
+ }
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Comparing regs from server start up to %s\n", where);
for (i = 0; i < NUM_I830_SNAPSHOTREGS; i++) {
@@ -913,6 +1481,31 @@ static void i830DumpAR(ScrnInfoPtr pScrn)
}
#endif
+static void IGDNGDumpRegs (ScrnInfoPtr pScrn)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ int i;
+
+ xf86DrvMsg (pScrn->scrnIndex, X_INFO, "DumpRegsBegin\n");
+ for (i = 0; i < NUM_IGDNG_SNAPSHOTREGS; i++) {
+ uint32_t val = INREG(igdng_snapshot[i].reg);
+
+ if (igdng_snapshot[i].debug_output != NULL) {
+ char *debug = igdng_snapshot[i].debug_output(pI830,
+ igdng_snapshot[i].reg,
+ val);
+ if (debug != NULL) {
+ xf86DrvMsg (pScrn->scrnIndex, X_INFO, "%20.20s: 0x%08x (%s)\n",
+ igdng_snapshot[i].name, (unsigned int)val, debug);
+ xfree(debug);
+ }
+ } else {
+ xf86DrvMsg (pScrn->scrnIndex, X_INFO, "%20.20s: 0x%08x\n",
+ igdng_snapshot[i].name, (unsigned int)val);
+ }
+ }
+}
+
void i830DumpRegs (ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
@@ -928,6 +1521,10 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
int crt;
#endif
+ if (IS_IGDNG(pI830)) {
+ IGDNGDumpRegs(pScrn);
+ return;
+ }
xf86DrvMsg (pScrn->scrnIndex, X_INFO, "DumpRegsBegin\n");
for (i = 0; i < NUM_I830_SNAPSHOTREGS; i++) {
uint32_t val = INREG(i830_snapshot[i].reg);
commit 0d56ef94be0592aec9aa83e4a5e4ff13348640c2
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Fri Jun 5 12:59:07 2009 +0800
Disable composite on new chipset for now
This depends on updated intel-gen4asm be ready for new chip.
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index eb35014..faf4d5d 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -722,6 +722,14 @@ i830_uxa_init (ScreenPtr pScreen)
i830->uxa_driver->done_composite = i830_done_composite;
}
+ /* FIXME */
+ if (IS_IGDNG(i830)) {
+ i830->uxa_driver->check_composite = NULL;
+ i830->uxa_driver->prepare_composite = NULL;
+ i830->uxa_driver->composite = NULL;
+ i830->uxa_driver->done_composite = NULL;
+ }
+
i830->uxa_driver->prepare_access = i830_uxa_prepare_access;
i830->uxa_driver->finish_access = i830_uxa_finish_access;
i830->uxa_driver->pixmap_is_offscreen = i830_uxa_pixmap_is_offscreen;
commit 440ccc44f51d3a5d6f46c28cfcc576cad155fbbc
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Fri Jun 5 12:56:04 2009 +0800
Add new register definitions
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/i810_reg.h b/src/i810_reg.h
index db542aa..ae1933d 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -982,13 +982,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
# define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
+/* IGDNG */
+# define DPLL_FPA0_P1_POST_DIV_SHIFT 16
+
# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
# define PLL_REF_INPUT_DREFCLK (0 << 13)
# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
+# define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* IGDNG: 120M SSC */
# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
# define PLL_REF_INPUT_MASK (3 << 13)
+# define PLL_REF_INPUT_DMICLK (5 << 13) /* IGDNG: DMI refclk */
# define PLL_LOAD_PULSE_PHASE_SHIFT 9
/*
* Parallel to Serial Load Pulse phase selection.
@@ -998,6 +1003,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
+/* IGDNG */
+# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
+# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
+# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1)<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT)
+# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
+# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
/**
* SDVO multiplier for 945G/GM. Not used on 965.
@@ -2146,10 +2157,33 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PIPEACONF_PIPE_LOCKED (1<<25)
#define PIPEACONF_PALETTE 0
#define PIPEACONF_GAMMA (1<<24)
+/* IGDNG: gamma */
+#define PIPECONF_PALETTE_8BIT (0<<24)
+#define PIPECONF_PALETTE_10BIT (1<<24)
+#define PIPECONF_PALETTE_12BIT (2<<24)
#define PIPECONF_FORCE_BORDER (1<<25)
#define PIPECONF_PROGRESSIVE (0 << 21)
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
+/* IGDNG */
+#define PIPECONF_MSA_TIMING_DELAY (0<<18) /* for eDP */
+#define PIPECONF_NO_DYNAMIC_RATE_CHANGE (0 << 16)
+#define PIPECONF_NO_ROTATION (0<<14)
+#define PIPECONF_FULL_COLOR_RANGE (0<<13)
+#define PIPECONF_CE_COLOR_RANGE (1<<13)
+#define PIPECONF_COLOR_SPACE_RGB (0<<11)
+#define PIPECONF_COLOR_SPACE_YUV601 (1<<11)
+#define PIPECONF_COLOR_SPACE_YUV709 (2<<11)
+#define PIPECONF_CONNECT_DEFAULT (0<<9)
+#define PIPECONF_8BPP (0<<5)
+#define PIPECONF_10BPP (1<<5)
+#define PIPECONF_6BPP (2<<5)
+#define PIPECONF_12BPP (3<<5)
+#define PIPECONF_ENABLE_DITHER (1<<4)
+#define PIPECONF_DITHER_SPATIAL (0<<2)
+#define PIPECONF_DITHER_ST1 (1<<2)
+#define PIPECONF_DITHER_ST2 (2<<2)
+#define PIPECONF_DITHER_TEMPORAL (3<<2)
#define PIPEAGCMAXRED 0x70010
#define PIPEAGCMAXGREEN 0x70014
@@ -2285,13 +2319,23 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DISPPLANE_8BPP (0x2<<26)
#define DISPPLANE_15_16BPP (0x4<<26)
#define DISPPLANE_16BPP (0x5<<26)
-#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
-#define DISPPLANE_32BPP (0x7<<26)
+#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) /* IGDNG: BGRX */
+#define DISPPLANE_32BPP (0x7<<26) /* IGDNG: not support */
+/* IGDNG */
+#define DISPPLANE_32BPP_10 (0x8<<26) /* 2:10:10:10 */
+#define DISPPLANE_32BPP_BGRX (0xa<<26)
+#define DISPPLANE_64BPP (0xc<<26)
+#define DISPPLANE_32BPP_RGBX (0xe<<26)
#define DISPPLANE_STEREO_ENABLE (1<<25)
#define DISPPLANE_STEREO_DISABLE 0
#define DISPPLANE_SEL_PIPE_MASK (1<<24)
-#define DISPPLANE_SEL_PIPE_A 0
+#define DISPPLANE_SEL_PIPE_A 0 /* IGDNG: don't use */
#define DISPPLANE_SEL_PIPE_B (1<<24)
+#define DISPPLANE_NORMAL_RANGE (0<<25)
+#define DISPPLANE_EXT_RANGE (1<<25)
+/* IGDNG */
+#define DISPPLANE_CSC_BYPASS (0<<24)
+#define DISPPLANE_CSC_PASSTHROUGH (1<<24)
#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
#define DISPPLANE_SRC_KEY_DISABLE 0
#define DISPPLANE_LINE_DOUBLE (1<<20)
@@ -2303,11 +2347,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
+/* IGDNG */
+#define DISPPLANE_X_TILE (1<<10)
+#define DISPPLANE_LINEAR (0<<10)
#define DSPABASE 0x70184
+/* IGDNG */
+#define DSPALINOFF 0x70184
#define DSPASTRIDE 0x70188
#define DSPBBASE 0x71184
+/* IGDNG */
+#define DSPBLINOFF 0x71184
#define DSPBADDR DSPBBASE
#define DSPBSTRIDE 0x71188
@@ -2919,4 +2970,439 @@ typedef enum {
#define MCHBAR_RENDER_STANDBY 0x111B8
#define RENDER_STANDBY_ENABLE (1 << 30)
+/* IGDNG */
+
+/* warmup time in us */
+#define WARMUP_PCH_REF_CLK_SSC_MOD 1
+#define WARMUP_PCH_FDI_RECEIVER_PLL 25
+#define WARMUP_PCH_DPLL 50
+#define WARMUP_CPU_DP_PLL 20
+#define WARMUP_CPU_FDI_TRANSMITTER_PLL 10
+#define WARMUP_DMI_LATENCY 20
+#define FDI_TRAIN_PATTERN_1_TIME 0.5
+#define FDI_TRAIN_PATTERN_2_TIME 1.5
+#define FDI_ONE_IDLE_PATTERN_TIME 31
+
+#define CPU_VGACNTRL 0x41000
+
+#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
+#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
+#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
+#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
+#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
+#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
+#define DIGITAL_PORTA_NO_DETECT (0 << 0)
+#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
+#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
+
+/* refresh rate hardware control */
+#define RR_HW_CTL 0x45300
+#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
+#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
+
+#define FDI_PLL_BIOS_0 0x46000
+#define FDI_PLL_BIOS_1 0x46004
+#define FDI_PLL_BIOS_2 0x46008
+#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
+#define DISPLAY_PORT_PLL_BIOS_1 0x46010
+#define DISPLAY_PORT_PLL_BIOS_2 0x46014
+
+#define FDI_PLL_FREQ_CTL 0x46030
+#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
+#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
+#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
+
+#define PIPEA_DATA_M1 0x60030
+#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
+#define TU_SIZE_MASK 0x7e000000
+#define PIPEA_DATA_M1_OFFSET 0
+#define PIPEA_DATA_N1 0x60034
+#define PIPEA_DATA_N1_OFFSET 0
+
+#define PIPEA_DATA_M2 0x60038
+#define PIPEA_DATA_M2_OFFSET 0
+#define PIPEA_DATA_N2 0x6003c
+#define PIPEA_DATA_N2_OFFSET 0
+
+#define PIPEA_LINK_M1 0x60040
+#define PIPEA_LINK_M1_OFFSET 0
+#define PIPEA_LINK_N1 0x60044
+#define PIPEA_LINK_N1_OFFSET 0
+
+#define PIPEA_LINK_M2 0x60048
+#define PIPEA_LINK_M2_OFFSET 0
+#define PIPEA_LINK_N2 0x6004c
+#define PIPEA_LINK_N2_OFFSET 0
+
+/* PIPEB timing regs are same start from 0x61000 */
+
+#define PIPEB_DATA_M1 0x61030
+#define PIPEB_DATA_M1_OFFSET 0
+#define PIPEB_DATA_N1 0x61034
+#define PIPEB_DATA_N1_OFFSET 0
+
+#define PIPEB_DATA_M2 0x61038
+#define PIPEB_DATA_M2_OFFSET 0
+#define PIPEB_DATA_N2 0x6103c
+#define PIPEB_DATA_N2_OFFSET 0
+
+#define PIPEB_LINK_M1 0x61040
+#define PIPEB_LINK_M1_OFFSET 0
+#define PIPEB_LINK_N1 0x61044
+#define PIPEB_LINK_N1_OFFSET 0
+
+#define PIPEB_LINK_M2 0x61048
+#define PIPEB_LINK_M2_OFFSET 0
+#define PIPEB_LINK_N2 0x6104c
+#define PIPEB_LINK_N2_OFFSET 0
+
+/* PIPECONF for pipe A/B addr is same */
+
+/* cusor A is only connected to pipe A,
+ cursor B is connected to pipe B. Otherwise no change. */
+
+/* Plane A/B, DSPACNTR/DSPBCNTR addr not changed */
+
+/* CPU panel fitter */
+#define PFA_CTL_1 0x68080
+#define PFB_CTL_1 0x68880
+#define PF_ENABLE (1<<31)
+
+/* CPU panel fitter */
+#define PFA_CTRL_1 0x68080
+#define PFB_CTRL_1 0x68880
+
+/* legacy palette */
+#define LGC_PALETTE_A 0x4a000
+#define LGC_PALETTE_B 0x4a800
+
+/* interrupts */
+#define DE_MASTER_IRQ_CONTROL (1 << 31)
+#define DE_SPRITEB_FLIP_DONE (1 << 29)
+#define DE_SPRITEA_FLIP_DONE (1 << 28)
+#define DE_PLANEB_FLIP_DONE (1 << 27)
+#define DE_PLANEA_FLIP_DONE (1 << 26)
+#define DE_PCU_EVENT (1 << 25)
+#define DE_GTT_FAULT (1 << 24)
+#define DE_POISON (1 << 23)
+#define DE_PERFORM_COUNTER (1 << 22)
+#define DE_PCH_EVENT (1 << 21)
+#define DE_AUX_CHANNEL_A (1 << 20)
+#define DE_DP_A_HOTPLUG (1 << 19)
+#define DE_GSE (1 << 18)
+#define DE_PIPEB_VBLANK (1 << 15)
+#define DE_PIPEB_EVEN_FIELD (1 << 14)
+#define DE_PIPEB_ODD_FIELD (1 << 13)
+#define DE_PIPEB_LINE_COMPARE (1 << 12)
+#define DE_PIPEB_VSYNC (1 << 11)
+#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
+#define DE_PIPEA_VBLANK (1 << 7)
+#define DE_PIPEA_EVEN_FIELD (1 << 6)
+#define DE_PIPEA_ODD_FIELD (1 << 5)
+#define DE_PIPEA_LINE_COMPARE (1 << 4)
+#define DE_PIPEA_VSYNC (1 << 3)
+#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
+
+#define DEISR 0x44000
+#define DEIMR 0x44004
+#define DEIIR 0x44008
+#define DEIER 0x4400c
+
+/* GT interrupt */
+#define GT_SYNC_STATUS (1 << 2)
+#define GT_USER_INTERRUPT (1 << 0)
+
+#define GTISR 0x44010
+#define GTIMR 0x44014
+#define GTIIR 0x44018
+#define GTIER 0x4401c
+
+/* PCH */
+
+/* south display engine interrupt */
+#define SDE_CRT_HOTPLUG (1 << 11)
+#define SDE_PORTD_HOTPLUG (1 << 10)
+#define SDE_PORTC_HOTPLUG (1 << 9)
+#define SDE_PORTB_HOTPLUG (1 << 8)
+#define SDE_SDVOB_HOTPLUG (1 << 6)
+
+#define SDEISR 0xc4000
+#define SDEIMR 0xc4004
+#define SDEIIR 0xc4008
+#define SDEIER 0xc400c
+
+/* digital port hotplug */
+#define PCH_PORT_HOTPLUG 0xc4030
+#define PORTD_HOTPLUG_ENABLE (1 << 20)
+#define PORTD_PULSE_DURATION_2ms (0)
+#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
+#define PORTD_PULSE_DURATION_6ms (2 << 18)
+#define PORTD_PULSE_DURATION_100ms (3 << 18)
+#define PORTD_HOTPLUG_NO_DETECT (0)
+#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
+#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
+#define PORTC_HOTPLUG_ENABLE (1 << 12)
+#define PORTC_PULSE_DURATION_2ms (0)
+#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
+#define PORTC_PULSE_DURATION_6ms (2 << 10)
+#define PORTC_PULSE_DURATION_100ms (3 << 10)
+#define PORTC_HOTPLUG_NO_DETECT (0)
+#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
+#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
+#define PORTB_HOTPLUG_ENABLE (1 << 4)
+#define PORTB_PULSE_DURATION_2ms (0)
+#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
+#define PORTB_PULSE_DURATION_6ms (2 << 2)
+#define PORTB_PULSE_DURATION_100ms (3 << 2)
+#define PORTB_HOTPLUG_NO_DETECT (0)
+#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
+#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
+
+#define PCH_GPIOA 0xc5010
+#define PCH_GPIOB 0xc5014
+#define PCH_GPIOC 0xc5018
+#define PCH_GPIOD 0xc501c
+#define PCH_GPIOE 0xc5020
+#define PCH_GPIOF 0xc5024
+#define PCH_GMBUS0 0xc5100
+#define PCH_GMBUS1 0xc5104
+#define PCH_GMBUS2 0xc5108
+#define PCH_GMBUS3 0xc510c
+#define PCH_GMBUS4 0xc5110
+#define PCH_GMBUS5 0xc5120
+
+#define PCH_DPLL_A 0xc6014
+#define PCH_DPLL_B 0xc6018
+
+#define PCH_FPA0 0xc6040
+#define PCH_FPA1 0xc6044
+#define PCH_FPB0 0xc6048
+#define PCH_FPB1 0xc604c
+
+#define PCH_DPLL_TEST 0xc606c
+
+#define PCH_DREF_CONTROL 0xC6200
+#define DREF_CONTROL_MASK 0x7fc3
+#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
+#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
+#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
+#define DREF_SSC_SOURCE_DISABLE (0<<11)
+#define DREF_SSC_SOURCE_ENABLE (2<<11)
+#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
+#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
+#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
+#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
+#define DREF_SSC4_DOWNSPREAD (0<<6)
+#define DREF_SSC4_CENTERSPREAD (1<<6)
+#define DREF_SSC1_DISABLE (0<<1)
+#define DREF_SSC1_ENABLE (1<<1)
+#define DREF_SSC4_DISABLE (0)
+#define DREF_SSC4_ENABLE (1)
+
+#define PCH_RAWCLK_FREQ 0xc6204
+#define FDL_TP1_TIMER_SHIFT 12
+#define FDL_TP1_TIMER_MASK (3<<12)
+#define FDL_TP2_TIMER_SHIFT 10
+#define FDL_TP2_TIMER_MASK (3<<10)
+#define RAWCLK_FREQ_MASK 0x3ff
+
+#define PCH_DPLL_TMR_CFG 0xc6208
+
+#define PCH_SSC4_PARMS 0xc6210
+#define PCH_SSC4_AUX_PARMS 0xc6214
+
+/* transcoder */
+
+#define TRANS_HTOTAL_A 0xe0000
+#define TRANS_HTOTAL_SHIFT 16
+#define TRANS_HACTIVE_SHIFT 0
+#define TRANS_HBLANK_A 0xe0004
+#define TRANS_HBLANK_END_SHIFT 16
+#define TRANS_HBLANK_START_SHIFT 0
+#define TRANS_HSYNC_A 0xe0008
+#define TRANS_HSYNC_END_SHIFT 16
+#define TRANS_HSYNC_START_SHIFT 0
+#define TRANS_VTOTAL_A 0xe000c
+#define TRANS_VTOTAL_SHIFT 16
+#define TRANS_VACTIVE_SHIFT 0
+#define TRANS_VBLANK_A 0xe0010
+#define TRANS_VBLANK_END_SHIFT 16
+#define TRANS_VBLANK_START_SHIFT 0
+#define TRANS_VSYNC_A 0xe0014
+#define TRANS_VSYNC_END_SHIFT 16
+#define TRANS_VSYNC_START_SHIFT 0
+
+#define TRANSA_DATA_M1 0xe0030
+#define TRANSA_DATA_N1 0xe0034
+#define TRANSA_DATA_M2 0xe0038
+#define TRANSA_DATA_N2 0xe003c
+#define TRANSA_DP_LINK_M1 0xe0040
+#define TRANSA_DP_LINK_N1 0xe0044
+#define TRANSA_DP_LINK_M2 0xe0048
+#define TRANSA_DP_LINK_N2 0xe004c
+
+#define TRANS_HTOTAL_B 0xe1000
+#define TRANS_HBLANK_B 0xe1004
+#define TRANS_HSYNC_B 0xe1008
+#define TRANS_VTOTAL_B 0xe100c
+#define TRANS_VBLANK_B 0xe1010
+#define TRANS_VSYNC_B 0xe1014
+
+#define TRANSB_DATA_M1 0xe1030
+#define TRANSB_DATA_N1 0xe1034
+#define TRANSB_DATA_M2 0xe1038
+#define TRANSB_DATA_N2 0xe103c
+#define TRANSB_DP_LINK_M1 0xe1040
+#define TRANSB_DP_LINK_N1 0xe1044
+#define TRANSB_DP_LINK_M2 0xe1048
+#define TRANSB_DP_LINK_N2 0xe104c
+
+#define TRANSACONF 0xf0008
+#define TRANSBCONF 0xf1008
+#define TRANS_DISABLE (0<<31)
+#define TRANS_ENABLE (1<<31)
+#define TRANS_STATE_MASK (1<<30)
+#define TRANS_STATE_DISABLE (0<<30)
+#define TRANS_STATE_ENABLE (1<<30)
+#define TRANS_FSYNC_DELAY_HB1 (0<<27)
+#define TRANS_FSYNC_DELAY_HB2 (1<<27)
+#define TRANS_FSYNC_DELAY_HB3 (2<<27)
+#define TRANS_FSYNC_DELAY_HB4 (3<<27)
+#define TRANS_DP_AUDIO_ONLY (1<<26)
+#define TRANS_DP_VIDEO_AUDIO (0<<26)
+#define TRANS_PROGRESSIVE (0<<21)
+#define TRANS_8BPC (0<<5)
+#define TRANS_10BPC (1<<5)
+#define TRANS_6BPC (2<<5)
+#define TRANS_12BPC (3<<5)
+
+#define FDI_RXA_CHICKEN 0xc200c
+#define FDI_RXB_CHICKEN 0xc2010
+#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
+
+/* CPU: FDI_TX */
+#define FDI_TXA_CTL 0x60100
+#define FDI_TXB_CTL 0x61100
+#define FDI_TX_DISABLE (0<<31)
+#define FDI_TX_ENABLE (1<<31)
+#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
+#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
+#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
+#define FDI_LINK_TRAIN_NONE (3<<28)
+#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
+#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
+#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
+#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
+#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
+#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
+#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
+#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
+#define FDI_DP_PORT_WIDTH_X1 (0<<19)
+#define FDI_DP_PORT_WIDTH_X2 (1<<19)
+#define FDI_DP_PORT_WIDTH_X3 (2<<19)
+#define FDI_DP_PORT_WIDTH_X4 (3<<19)
+#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
+/* IGDNG: hardwired to 1 */
+#define FDI_TX_PLL_ENABLE (1<<14)
+/* both Tx and Rx */
+#define FDI_SCRAMBLING_ENABLE (0<<7)
+#define FDI_SCRAMBLING_DISABLE (1<<7)
+
+/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
+#define FDI_RXA_CTL 0xf000c
+#define FDI_RXB_CTL 0xf100c
+#define FDI_RX_ENABLE (1<<31)
+#define FDI_RX_DISABLE (0<<31)
+/* train, dp width same as FDI_TX */
+#define FDI_DP_PORT_WIDTH_X8 (7<<19)
+#define FDI_8BPC (0<<16)
+#define FDI_10BPC (1<<16)
+#define FDI_6BPC (2<<16)
+#define FDI_12BPC (3<<16)
+#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
+#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
+#define FDI_RX_PLL_ENABLE (1<<13)
+#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
+#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
+#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
+#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
+#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
+#define FDI_SEL_RAWCLK (0<<4)
+#define FDI_SEL_PCDCLK (1<<4)
+
+#define FDI_RXA_MISC 0xf0010
+#define FDI_RXB_MISC 0xf1010
+#define FDI_RXA_TUSIZE1 0xf0030
+#define FDI_RXA_TUSIZE2 0xf0038
+#define FDI_RXB_TUSIZE1 0xf1030
+#define FDI_RXB_TUSIZE2 0xf1038
+
+/* FDI_RX interrupt register format */
+#define FDI_RX_INTER_LANE_ALIGN (1<<10)
+#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
+#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
+#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
+#define FDI_RX_FS_CODE_ERR (1<<6)
+#define FDI_RX_FE_CODE_ERR (1<<5)
+#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
+#define FDI_RX_HDCP_LINK_FAIL (1<<3)
+#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
+#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
+#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
+
+#define FDI_RXA_IIR 0xf0014
+#define FDI_RXA_IMR 0xf0018
+#define FDI_RXB_IIR 0xf1014
+#define FDI_RXB_IMR 0xf1018
+
+#define FDI_PLL_CTL_1 0xfe000
+#define FDI_PLL_CTL_2 0xfe004
+
+/* CRT */
+#define PCH_ADPA 0xe1100
+#define ADPA_TRANS_SELECT_MASK (1<<30)
+#define ADPA_TRANS_A_SELECT 0
+#define ADPA_TRANS_B_SELECT (1<<30)
+/* HPD is here */
+#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
+#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
+#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
+#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
+#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
+#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
+#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
+#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
+#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
+#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
+#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
+#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
+#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
+#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
+#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
+#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
+#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
+#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
+#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
+/* polarity control not changed */
+
+/* or SDVOB */
+#define HDMIB 0xe1140
+#define PORT_ENABLE (1 << 31)
+#define TRANSCODER_A (0)
+#define TRANSCODER_B (1 << 30)
+#define COLOR_FORMAT_8bpc (0)
+#define COLOR_FORMAT_12bpc (3 << 26)
+#define SDVOB_HOTPLUG_ENABLE (1 << 23)
+#define SDVO_ENCODING (0)
+#define TMDS_ENCODING (2 << 10)
+#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
+#define SDVOB_BORDER_ENABLE (1 << 7)
+#define AUDIO_ENABLE (1 << 6)
+#define VSYNC_ACTIVE_HIGH (1 << 4)
+#define HSYNC_ACTIVE_HIGH (1 << 3)
+#define PORT_DETECTED (1 << 2)
+
+#define HDMIC 0xe1150
+#define HDMID 0xe1160
+
#endif /* _I810_REG_H */
commit 0d8a9e2c6f58115b9b8449de52e795699ed032af
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Fri Jun 5 12:51:51 2009 +0800
Update intel_gtt utility for new chipset GTT check
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/reg_dumper/gtt.c b/src/reg_dumper/gtt.c
index 4a46f11..c331601 100644
--- a/src/reg_dumper/gtt.c
+++ b/src/reg_dumper/gtt.c
@@ -52,7 +52,7 @@ int main(int argc, char **argv)
exit(1);
}
- if (IS_G4X(pI830))
+ if (IS_G4X(pI830) || IS_IGDNG(pI830))
gtt = (unsigned char *)(pI830->mmio + MB(2));
else if (IS_I965G(pI830))
gtt = (unsigned char *)(pI830->mmio + KB(512));
commit fb524caa3e2f1f516717669642bb4b2244f9e7e4
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Mon Jun 8 10:22:14 2009 +0800
Remove fixed MMIO size
Use pci resource size instead, which will get the correct MMIO range.
New chipset uses obviously larger MMIO range.
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/i830.h b/src/i830.h
index c0e7dcd..a69f47c 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -415,6 +415,7 @@ typedef struct _I830Rec {
int Chipset;
unsigned long LinearAddr;
unsigned long MMIOAddr;
+ unsigned int MMIOSize;
IOADDRESS ioBase;
EntityInfoPtr pEnt;
struct pci_device *PciInfo;
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 8400872..9d38fba 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -425,7 +425,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
device = pI830->PciInfo;
err = pci_device_map_range (device,
pI830->MMIOAddr,
- I810_REG_SIZE,
+ pI830->MMIOSize,
PCI_DEV_MAP_FLAG_WRITABLE,
(void **) &pI830->MMIOBase);
if (err)
@@ -508,7 +508,7 @@ I830UnmapMMIO(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- pci_device_unmap_range (pI830->PciInfo, pI830->MMIOBase, I810_REG_SIZE);
+ pci_device_unmap_range (pI830->PciInfo, pI830->MMIOBase, pI830->MMIOSize);
pI830->MMIOBase = NULL;
if (IS_I9XX(pI830)) {
@@ -1218,6 +1218,7 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
if (pI830->pEnt->device->IOBase != 0) {
pI830->MMIOAddr = pI830->pEnt->device->IOBase;
from = X_CONFIG;
+ pI830->MMIOSize = I810_REG_SIZE;
} else {
pI830->MMIOAddr = I810_MEMBASE (pI830->PciInfo, mmio_bar);
if (pI830->MMIOAddr == 0) {
@@ -1226,10 +1227,11 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
PreInitCleanup(pScrn);
return FALSE;
}
+ pI830->MMIOSize = pI830->PciInfo->regions[mmio_bar].size;
}
- xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX\n",
- (unsigned long)pI830->MMIOAddr);
+ xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX size %u\n",
+ (unsigned long)pI830->MMIOAddr, pI830->MMIOSize);
/* Now figure out mapsize on 8xx chips */
if (IS_I830(pI830) || IS_845G(pI830)) {
commit 4f40b33ef4b069b18a6a18406da83a23ca6e1127
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Fri Jun 5 11:57:57 2009 +0800
Add new chipsets PCI ids
Desktop and mobile version of new chipsets are added.
Also do memory config like Intel 4 series chipset.
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
diff --git a/src/common.h b/src/common.h
index 335fe75..69f5604 100644
--- a/src/common.h
+++ b/src/common.h
@@ -310,6 +310,16 @@ extern int I810_DEBUG;
#define PCI_CHIP_G41_G_BRIDGE 0x2E30
#endif
+#ifndef PCI_CHIP_IGDNG_D_G
+#define PCI_CHIP_IGDNG_D_G 0x0042
+#define PCI_CHIP_IGDNG_D_G_BRIDGE 0x0040
+#endif
+
+#ifndef PCI_CHIP_IGDNG_M_G
+#define PCI_CHIP_IGDNG_M_G 0x0046
+#define PCI_CHIP_IGDNG_M_G_BRIDGE 0x0044
+#endif
+
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
#define VENDOR_ID(p) (p)->vendor_id
#define DEVICE_ID(p) (p)->device_id
@@ -339,7 +349,10 @@ extern int I810_DEBUG;
#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || IS_GM45(pI810))
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810))
+#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G)
+#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G)
+#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810))
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810) || IS_IGDNG(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \
@@ -347,20 +360,20 @@ extern int I810_DEBUG;
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* mark chipsets without overlay hw */
-#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810))
+#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* chipsets require graphics mem for hardware status page */
#define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \
(IS_G33CLASS(pI810) ||\
- IS_G4X(pI810)))
+ IS_G4X(pI810) || IS_IGDNG(pI810)))
/* chipsets require status page in non stolen memory */
-#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810))
-#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810))
+#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
+#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* dsparb controlled by hw only */
-#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810))
+#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
#define SUPPORTS_YTILING(pI810) (IS_I965G(pI830))
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 21c35da..4b8c459 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -138,6 +138,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_D_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_M_G, 0 ),
{ 0, 0, 0 },
};
@@ -189,6 +191,8 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
{PCI_CHIP_G41_G, "G41"},
+ {PCI_CHIP_IGDNG_D_G, "IGDNG_D"},
+ {PCI_CHIP_IGDNG_M_G, "IGDNG_M"},
{-1, NULL}
};
@@ -225,6 +229,8 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
{PCI_CHIP_G41_G, PCI_CHIP_G41_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGDNG_D_G, PCI_CHIP_IGDNG_D_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGDNG_M_G, PCI_CHIP_IGDNG_M_G, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 73d350f..8400872 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -118,6 +118,8 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
{PCI_CHIP_G41_G, "G41"},
+ {PCI_CHIP_IGDNG_D_G, "IGDNG_D"},
+ {PCI_CHIP_IGDNG_M_G, "IGDNG_M"},
{-1, NULL}
};
@@ -148,6 +150,8 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
{PCI_CHIP_G41_G, PCI_CHIP_G41_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGDNG_D_G, PCI_CHIP_IGDNG_D_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGDNG_M_G, PCI_CHIP_IGDNG_M_G, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED}
};
@@ -324,7 +328,7 @@ I830DetectMemory(ScrnInfoPtr pScrn)
range = gtt_size + 4;
/* new 4 series hardware has seperate GTT stolen with GFX stolen */
- if (IS_G4X(pI830) || IS_IGD(pI830))
+ if (IS_G4X(pI830) || IS_IGD(pI830) || IS_IGDNG(pI830))
range = 4;
if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
@@ -440,7 +444,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- if (IS_G4X(pI830)) {
+ if (IS_G4X(pI830) || IS_IGDNG(pI830)) {
gttaddr = pI830->MMIOAddr + MB(2);
pI830->GTTMapSize = MB(2);
} else {
@@ -1135,6 +1139,12 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
case PCI_CHIP_G41_G:
chipname = "G41";
break;
+ case PCI_CHIP_IGDNG_D_G:
+ chipname = "IGDNG_D";
+ break;
+ case PCI_CHIP_IGDNG_M_G:
+ chipname = "IGDNG_M";
+ break;
default:
chipname = "unknown chipset";
break;
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