xf86-video-ati: Branch 'master'

[Alex Deucher]

 src/r600_shader.c |   16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

New commits:
commit ec1a3ccdf61c2226617b571cc4a209a542e9d7e3
Author: Alex Deucher <alexdeucher at gmail.com>
Date:   Mon Jun 8 15:31:57 2009 -0400

    R6xx/r7xx: don't clamp tex coords in composite VS
    
    Fixes broken repeat modes.  see fdo bugs 21818, 22139

diff --git a/src/r600_shader.c b/src/r600_shader.c
index ceabad8..584deb4 100644
--- a/src/r600_shader.c
+++ b/src/r600_shader.c
@@ -546,7 +546,7 @@ int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_GPR(0),
                                  DST_REL(ABSOLUTE),
                                  DST_ELEM(ELEM_X),
-                                 CLAMP(1));
+                                 CLAMP(0));
 
     /* 5 texY / h */
     shader[i++] = ALU_DWORD0(SRC0_SEL(0),
@@ -573,7 +573,7 @@ int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_GPR(0),
                                  DST_REL(ABSOLUTE),
                                  DST_ELEM(ELEM_Y),
-                                 CLAMP(1));
+                                 CLAMP(0));
 
     /* 6/7 */
     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
@@ -1715,7 +1715,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_GPR(1),
                                  DST_REL(ABSOLUTE),
                                  DST_ELEM(ELEM_X),
-                                 CLAMP(1));
+                                 CLAMP(0));
 
     /* 18 srcY / h */
     shader[i++] = ALU_DWORD0(SRC0_SEL(1),
@@ -1742,7 +1742,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_GPR(1),
                                  DST_REL(ABSOLUTE),
                                  DST_ELEM(ELEM_Y),
-                                 CLAMP(1));
+                                 CLAMP(0));
 
     /* 19 maskX / w */
     shader[i++] = ALU_DWORD0(SRC0_SEL(0),
@@ -1769,7 +1769,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_GPR(0),
                                  DST_REL(ABSOLUTE),
                                  DST_ELEM(ELEM_X),
-                                 CLAMP(1));
+                                 CLAMP(0));
 
     /* 20 maskY / h */
     shader[i++] = ALU_DWORD0(SRC0_SEL(0),
@@ -1796,7 +1796,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_GPR(0),
                                  DST_REL(ABSOLUTE),
                                  DST_ELEM(ELEM_Y),
-                                 CLAMP(1));
+                                 CLAMP(0));
     /* 21 */
     shader[i++] = 0x00000000;
     shader[i++] = 0x00000000;
@@ -2068,7 +2068,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_GPR(0),
                                  DST_REL(ABSOLUTE),
                                  DST_ELEM(ELEM_X),
-                                 CLAMP(1));
+                                 CLAMP(0));
 
     /* 38 srcY / h */
     shader[i++] = ALU_DWORD0(SRC0_SEL(0),
@@ -2095,7 +2095,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
                                  DST_GPR(0),
                                  DST_REL(ABSOLUTE),
                                  DST_ELEM(ELEM_Y),
-                                 CLAMP(1));
+                                 CLAMP(0));
 
     /* 39 */
     shader[i++] = 0x00000000;