xf86-video-intel: Branch '2.8' - 7 commits - configure.ac NEWS src/bios_reader/bios_reader.c src/drmmode_display.c src/i830_accel.c src/i830_bios.c src/i830_uxa.c src/render_program/exa_wm_src_sample_planar.g4a src/render_program/exa_wm_src_sample_planar.g4b src/render_program/exa_wm_src_sample_planar.g4b.gen5
Carl Worth
cworth at kemper.freedesktop.org
Tue Aug 25 22:58:01 PDT 2009
NEWS | 29 +++++++++++++++----
configure.ac | 2 -
src/bios_reader/bios_reader.c | 20 +++++++++++--
src/drmmode_display.c | 3 -
src/i830_accel.c | 3 -
src/i830_bios.c | 6 ++-
src/i830_uxa.c | 23 ++++++++++-----
src/render_program/exa_wm_src_sample_planar.g4a | 4 +-
src/render_program/exa_wm_src_sample_planar.g4b | 4 +-
src/render_program/exa_wm_src_sample_planar.g4b.gen5 | 4 +-
10 files changed, 69 insertions(+), 29 deletions(-)
New commits:
commit e6105d978a0217219cb2d60a672ae200c70bc68d
Author: Carl Worth <cworth at cworth.org>
Date: Tue Aug 25 16:56:44 2009 -0700
Increment version number to 2.8.1 for release.
diff --git a/configure.ac b/configure.ac
index c19922b..e4737d5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-intel],
- 2.8.0.901,
+ 2.8.1,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-intel)
commit 584cdcb10ce73838e9a96b8f8a390cd0affe2f0e
Author: Carl Worth <cworth at cworth.org>
Date: Tue Aug 25 16:56:09 2009 -0700
NEWS: Add notes for 2.8.1
An additional 5 patches were proposed at:
http://wiki.x.org/wiki/Intel28Branch
diff --git a/NEWS b/NEWS
index 1bd218f..db58868 100644
--- a/NEWS
+++ b/NEWS
@@ -1,17 +1,36 @@
-Release 2.8.0.901 (2.8.1 rc1 2009-08-13)
-========================================
-We are pleased to announce this release candidate working toward the
-2.8.1 maintenance release of the xf86-video-intel driver. This
-snapshot contains a few, hand-picked fixes since the 2.8.0 release.
+Release 2.8.0 (2009-08-25)
+============================
+We are pleased to announce this 2.8.1 maintenance release of the
+xf86-video-intel driver. This snapshot contains a few, hand-picked
+fixes since the 2.8.0 release. Several of the bugs fixed can manifest
+themselves as "random" crashing or hanging of the GPU, (so effectively
+the interactive session). We recommend that all users/distributors of
+2.8.0 upgrade to 2.8.1.
New fixes in 2.8.1 compared to 2.8.0
------------------------------------
+Bug numbers are relative to bugs.freedesktop.org unless otherwise
+mentioned.
+
* Allow DRM mode setting to include transformations (also requires a
fix in the X server---available in xserver 1.6.3)
* Align tiled pixmap height so we don't address beyond the end of our
buffers.
+* Align the height of untiled pixmaps to 2 lines as well.
+
+* Replace existing EDID property blob with new one
+
+* Only align DRI2 tiled pixmaps to the DRI2 tiled pixmap alignment
+ requirement (fixes bug #21387).
+
+* Calculate the DVO relative offset in LVDS data entry to get the DVO
+ timing (fixes bug #22787 and Debian bug #538148).
+
+* Fix sampler indexes on i965 planar video, (fixes bugs #22895 and
+ #19856).
+
Release 2.8.0 (2009-07-20)
==========================
We are pleased to present this major release of the xf86-video-intel
commit 215ee68a5aa1d0f24884cd8bc226959c30c20bd3
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 12 19:29:31 2009 -0700
Align the height of untiled pixmaps to 2 lines as well.
The 965 docs note, and it's probably the case on 915 as well, that the
2x2 subspans are read as a unit, even if the bottom row isn't used. If
the address in that bottom row extended beyond the end of the GTT, a
fault could occur.
Thanks to Chris Wilson for pointing out the problem.
(cherry picked from commit 465a4ab416b2e5ad53b96702720331a44fffa2fe)
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index c05d4d6..28a19cb 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -613,14 +613,17 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
pitch_align);
if (tiling == I915_TILING_NONE) {
- size = stride * h;
+ /* Round the height up so that the GPU's access to a 2x2 aligned
+ * subspan doesn't address an invalid page offset beyond the
+ * end of the GTT.
+ */
+ size = stride * ALIGN(h, 2);
} else {
int aligned_h = h;
if (tiling == I915_TILING_X)
aligned_h = ALIGN(h, 8);
else
aligned_h = ALIGN(h, 32);
- assert(aligned_h >= h);
stride = i830_get_fence_pitch(i830, stride, tiling);
/* Round the object up to the size of the fence it will live in
commit 180a9d160f28087db20e34c838f19ff0a26fabcc
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 5 12:45:16 2009 -0700
Fix sampler indexes on i965 planar video.
We only set up one sampler, because all of our sampling is the same. By
using a non-zero index for the other two samplers, we'd dereference (likely)
zeroed data, resulting in using NEAREST filtering. This was a regression in
40671132cb3732728703c6444f4577467fa9223f which incidentally switched from
having 6 samplers to 1.
Bug #22895, #19856
(cherry picked from commit 79b6851148574419389ac8055b0c31b8bdac3ab3)
diff --git a/src/render_program/exa_wm_src_sample_planar.g4a b/src/render_program/exa_wm_src_sample_planar.g4a
index ca77b48..ad33350 100644
--- a/src/render_program/exa_wm_src_sample_planar.g4a
+++ b/src/render_program/exa_wm_src_sample_planar.g4a
@@ -52,7 +52,7 @@ send (16) src_msg_ind /* msg reg index */
send (16) src_msg_ind /* msg reg index */
src_sample_r<1>UW /* readback */
g0<8,8,1>UW /* copy to msg start reg*/
- sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ sampler (3,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
/* here(src->dst) we should use src_sampler and src_surface */
mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
@@ -60,6 +60,6 @@ send (16) src_msg_ind /* msg reg index */
send (16) src_msg_ind /* msg reg index */
src_sample_b<1>UW /* readback */
g0<8,8,1>UW /* copy to msg start reg*/
- sampler (5,4,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ sampler (5,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
/* here(src->dst) we should use src_sampler and src_surface */
mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
diff --git a/src/render_program/exa_wm_src_sample_planar.g4b b/src/render_program/exa_wm_src_sample_planar.g4b
index 77a5c23..23e5e0d 100644
--- a/src/render_program/exa_wm_src_sample_planar.g4b
+++ b/src/render_program/exa_wm_src_sample_planar.g4b
@@ -1,4 +1,4 @@
{ 0x00000201, 0x20080061, 0x00000000, 0x0000e000 },
{ 0x01800031, 0x22001d29, 0x008d0000, 0x02520001 },
- { 0x01800031, 0x21c01d29, 0x008d0000, 0x02520203 },
- { 0x01800031, 0x22401d29, 0x008d0000, 0x02520405 },
+ { 0x01800031, 0x21c01d29, 0x008d0000, 0x02520003 },
+ { 0x01800031, 0x22401d29, 0x008d0000, 0x02520005 },
diff --git a/src/render_program/exa_wm_src_sample_planar.g4b.gen5 b/src/render_program/exa_wm_src_sample_planar.g4b.gen5
index a381e68..71068d9 100644
--- a/src/render_program/exa_wm_src_sample_planar.g4b.gen5
+++ b/src/render_program/exa_wm_src_sample_planar.g4b.gen5
@@ -1,4 +1,4 @@
{ 0x00000201, 0x20080061, 0x00000000, 0x0000e000 },
{ 0x01800031, 0x22001d29, 0x208d0000, 0x0a2a0001 },
- { 0x01800031, 0x21c01d29, 0x208d0000, 0x0a2a0203 },
- { 0x01800031, 0x22401d29, 0x208d0000, 0x0a2a0405 },
+ { 0x01800031, 0x21c01d29, 0x208d0000, 0x0a2a0003 },
+ { 0x01800031, 0x22401d29, 0x208d0000, 0x0a2a0005 },
commit aa1d3f0bfd323126bcb4e11e4e5090fc2850237a
Author: Zhao Yakui <yakui.zhao at intel.com>
Date: Fri Jul 24 10:44:20 2009 +0800
Calculate the DVO relative offset in LVDS data entry to get the DVO timing
Now the DVO timing in LVDS data entry is obtained by using the
following step:
a. get the entry size for every LVDS panel data
b. Get the LVDS fp entry for the preferred panel type
c. get the DVO timing by using entry->dvo_timing
In our driver the entry->dvo_timing is related with the size of
lvds_fp_timing. For example: the size is 46.
But it seems that the size of lvds_fp_timing varies on the differnt
platform. In such case we will get the incorrect DVO timing because of
the incorrect DVO offset in LVDS panel data entry.
Calculate the DVO timing offset in LVDS data entry to get the DVO timing
a. get the DVO timing offset in the LVDS fp data entry by using the
pointer definition in LVDS data ptr
b. get the LVDS data entry
c. get the DVO timing by adding the DVO timing offset to data entry
https://bugs.freedesktop.org/show_bug.cgi?id=22787
Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
(cherry picked from commit af45482a52999b52bf41468c458808e30c100e35)
diff --git a/src/bios_reader/bios_reader.c b/src/bios_reader/bios_reader.c
index cdc2045..35b144c 100644
--- a/src/bios_reader/bios_reader.c
+++ b/src/bios_reader/bios_reader.c
@@ -313,11 +313,23 @@ static void dump_lvds_data(void)
{
struct bdb_block *block;
struct bdb_lvds_lfp_data *lvds_data;
+ struct bdb_lvds_lfp_data_ptrs *ptrs;
int num_entries;
int i;
int hdisplay, hsyncstart, hsyncend, htotal;
int vdisplay, vsyncstart, vsyncend, vtotal;
float clock;
+ int lfp_data_size, dvo_offset;
+
+ block = find_section(BDB_LVDS_LFP_DATA_PTRS);
+ if (!block) {
+ printf("No LVDS ptr block\n");
+ return;
+ }
+ ptrs = block->data;
+ lfp_data_size = ptrs->ptr[1].fp_timing_offset - ptrs->ptr[0].fp_timing_offset;
+ dvo_offset = ptrs->ptr[0].dvo_timing_offset - ptrs->ptr[0].fp_timing_offset;
+ free(block);
block = find_section(BDB_LVDS_LFP_DATA);
if (!block) {
@@ -326,14 +338,16 @@ static void dump_lvds_data(void)
}
lvds_data = block->data;
- num_entries = block->size / sizeof(struct bdb_lvds_lfp_data_entry);
+ num_entries = block->size / lfp_data_size;
printf("LVDS panel data block (preferred block marked with '*'):\n");
printf(" Number of entries: %d\n", num_entries);
for (i = 0; i < num_entries; i++) {
- struct bdb_lvds_lfp_data_entry *lfp_data = &lvds_data->data[i];
- uint8_t *timing_data = (uint8_t *)&lfp_data->dvo_timing;
+ uint8_t *lfp_data_ptr = (uint8_t *)lvds_data->data + lfp_data_size * i;
+ uint8_t *timing_data = lfp_data_ptr + dvo_offset;
+ struct bdb_lvds_lfp_data_entry *lfp_data =
+ (struct bdb_lvds_flp_data_entry *)lfp_data_ptr;
char marker;
if (i == panel_type)
diff --git a/src/i830_bios.c b/src/i830_bios.c
index 60c307c..f4a2005 100644
--- a/src/i830_bios.c
+++ b/src/i830_bios.c
@@ -123,6 +123,7 @@ parse_integrated_panel_data(I830Ptr pI830, struct bdb_header *bdb)
DisplayModePtr fixed_mode;
unsigned char *timing_ptr;
int lfp_data_size;
+ int dvo_offset;
/* Defaults if we can't find VBT info */
pI830->lvds_dither = 0;
@@ -146,10 +147,11 @@ parse_integrated_panel_data(I830Ptr pI830, struct bdb_header *bdb)
lfp_data_size = lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
+ dvo_offset = lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
+ lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
entry = (struct bdb_lvds_lfp_data_entry *)((uint8_t *)lvds_data->data +
(lfp_data_size * lvds_options->panel_type));
- timing_ptr = (unsigned char *)&entry->dvo_timing;
-
+ timing_ptr = (unsigned char *)entry + dvo_offset;
if (pI830->skip_panel_detect)
return;
commit 959bf6df0f8d2defae1f7b3084c9e6ed473db9d9
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 15 16:38:07 2009 -0700
Only align DRI2 tiled pixmaps to the DRI2 tiled pixmap alignment requirement.
This should save significant amounts of memory for glyph and other small
pixmap storage.
Bug #21387
(cherry picked from commit 6b7728491c3b771bcba2c7ffd75330c0a0b37f44)
diff --git a/src/i830_accel.c b/src/i830_accel.c
index 96a7bde..abefa55 100644
--- a/src/i830_accel.c
+++ b/src/i830_accel.c
@@ -232,9 +232,6 @@ I830AccelInit(ScreenPtr pScreen)
pI830->accel_max_x = 2048;
pI830->accel_max_y = 2048;
}
- /* Bump the pitch so that we can tile any pixmap we create. */
- if (pI830->directRenderingType >= DRI_DRI2)
- pI830->accel_pixmap_pitch_alignment = 512;
return i830_uxa_init(pScreen);
}
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index fe0fb49..c05d4d6 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -597,14 +597,20 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
{
unsigned int size;
uint32_t tiling = I915_TILING_NONE;
+ int pitch_align;
- stride = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
- i830->accel_pixmap_pitch_alignment);
-
- if (usage == INTEL_CREATE_PIXMAP_TILING_X)
+ if (usage == INTEL_CREATE_PIXMAP_TILING_X) {
tiling = I915_TILING_X;
- else if (usage == INTEL_CREATE_PIXMAP_TILING_Y)
+ pitch_align = 512;
+ } else if (usage == INTEL_CREATE_PIXMAP_TILING_Y) {
tiling = I915_TILING_Y;
+ pitch_align = 512;
+ } else {
+ pitch_align = i830->accel_pixmap_pitch_alignment;
+ }
+
+ stride = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
+ pitch_align);
if (tiling == I915_TILING_NONE) {
size = stride * h;
commit 154592a855e07889be5ffc8d63ef39ed424c61f6
Author: Keith Packard <keithp at keithp.com>
Date: Tue Jul 21 12:32:10 2009 -0700
drmmode_output_get_modes: Replace existing EDID property blob with new one
This synchronizes the X EDID data with the kernel EDID data each time the
kernel data may have changed. Otherwise, X ends up stuck with the first EDID
data it sees, failing to accomodate to different monitors.
Signed-off-by: Keith Packard <keithp at keithp.com>
(cherry picked from commit 6f3fc6b20f3daedab02e31f49678d4d2ff0fa7a3)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 8c919f9..814743b 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -638,8 +638,7 @@ drmmode_output_get_modes(xf86OutputPtr output)
if (!props || !(props->flags & DRM_MODE_PROP_BLOB))
continue;
- if (!strcmp(props->name, "EDID") &&
- drmmode_output->edid_blob == NULL) {
+ if (!strcmp(props->name, "EDID")) {
drmModeFreePropertyBlob(drmmode_output->edid_blob);
drmmode_output->edid_blob =
drmModeGetPropertyBlob(drmmode->fd,
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