xf86-video-intel: 3 commits - src/i810_reg.h src/i830_crt.c src/i830_driver.c

[Zhenyu Wang]

 src/i810_reg.h    |    3 +++
 src/i830_crt.c    |   11 +++++++++++
 src/i830_driver.c |   20 ++++++++++++++++----
 3 files changed, 30 insertions(+), 4 deletions(-)

New commits:
commit 1cc15ba454fdf54a7dea9da066e0a023a4742fab
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date:   Fri Sep 26 10:01:52 2008 +0800

    Render register clock gating disable fix on 4 series chipset

diff --git a/src/i810_reg.h b/src/i810_reg.h
index 5b90e12..6458008 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -1167,6 +1167,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
 
 #define RENCLK_GATE_D2		0x6208
+#define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
+#define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
+#define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
 #define RAMCLK_GATE_D		0x6210		/* CRL only */
 #define DEUC			0x6214          /* CRL only */
 
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 1317c1d..389775f 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -965,12 +965,18 @@ i830_init_clock_gating(ScrnInfoPtr pScrn)
     /* Disable clock gating reported to work incorrectly according to the specs.
      */
     if (IS_GM45(pI830) || IS_G4X(pI830)) {
+	uint32_t dspclk_gate;
 	OUTREG(RENCLK_GATE_D1, 0);
-	OUTREG(RENCLK_GATE_D2, 0);
+	OUTREG(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
+		GS_UNIT_CLOCK_GATE_DISABLE |
+		CL_UNIT_CLOCK_GATE_DISABLE);
 	OUTREG(RAMCLK_GATE_D, 0);
-	OUTREG(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE |
-	       OVRUNIT_CLOCK_GATE_DISABLE |
-	       OVCUNIT_CLOCK_GATE_DISABLE);
+	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
+	    OVRUNIT_CLOCK_GATE_DISABLE |
+	    OVCUNIT_CLOCK_GATE_DISABLE;
+	if (IS_GM45(pI830))
+	    dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
+	OUTREG(DSPCLK_GATE_D, dspclk_gate);
     } else if (IS_I965GM(pI830)) {
 	OUTREG(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
 	OUTREG(RENCLK_GATE_D2, 0);
commit d6b2696f9ac14a81598e0147698209ad428fd45d
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date:   Fri Sep 26 09:53:03 2008 +0800

    Do force CRT detect sequence twice on 4 series chipset

diff --git a/src/i830_crt.c b/src/i830_crt.c
index 5812e2b..2e70eb8 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -161,6 +161,14 @@ i830_crt_detect_hotplug(xf86OutputPtr output)
     uint32_t	temp;
     const int	timeout_ms = 1000;
     int		starttime, curtime;
+    int		tries = 1;
+
+    /* On 4 series, CRT detect sequence need to be done twice for safe. */
+    if (IS_G4X(pI830))
+	tries = 2;
+
+retry:
+    tries--;
 
     temp = INREG(PORT_HOTPLUG_EN);
 
@@ -173,6 +181,9 @@ i830_crt_detect_hotplug(xf86OutputPtr output)
 	    break;
     }
 
+    if (tries > 0)
+	goto retry;
+
     if ((INREG(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) ==
 	CRT_HOTPLUG_MONITOR_COLOR)
     {
commit d8a007b056e3d6c3e132ecac06368b21d2ac4123
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date:   Fri Sep 26 09:44:59 2008 +0800

    Bug #16515: Fix VT switch with DVI on G45
    
    On DVI, centered VGA mode is used instead of native mode VGA, and
    PLL on pipe is used instead of VGA PLL setting. So make sure PLL
    settled down in restore time.

diff --git a/src/i830_driver.c b/src/i830_driver.c
index 9bf0a64..1317c1d 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2359,12 +2359,15 @@ RestoreHWState(ScrnInfoPtr pScrn)
    /* If the pipe A PLL is active, we can restore the pipe & plane config */
    if (pI830->saveDPLL_A & DPLL_VCO_ENABLE)
    {
+      OUTREG(FPA0, pI830->saveFPA0);
       OUTREG(DPLL_A, pI830->saveDPLL_A & ~DPLL_VCO_ENABLE);
+      POSTING_READ(DPLL_A);
       usleep(150);
    }
    OUTREG(FPA0, pI830->saveFPA0);
    OUTREG(FPA1, pI830->saveFPA1);
    OUTREG(DPLL_A, pI830->saveDPLL_A);
+   POSTING_READ(DPLL_A);
    i830_dpll_settle();
    if (IS_I965G(pI830))
       OUTREG(DPLL_A_MD, pI830->saveDPLL_A_MD);
@@ -2420,12 +2423,15 @@ RestoreHWState(ScrnInfoPtr pScrn)
       /* If the pipe B PLL is active, we can restore the pipe & plane config */
       if (pI830->saveDPLL_B & DPLL_VCO_ENABLE)
       {
+	 OUTREG(FPB0, pI830->saveFPB0);
 	 OUTREG(DPLL_B, pI830->saveDPLL_B & ~DPLL_VCO_ENABLE);
+	 POSTING_READ(DPLL_B);
 	 usleep(150);
       }
       OUTREG(FPB0, pI830->saveFPB0);
       OUTREG(FPB1, pI830->saveFPB1);
       OUTREG(DPLL_B, pI830->saveDPLL_B);
+      POSTING_READ(DPLL_B);
       i830_dpll_settle();
       if (IS_I965G(pI830))
 	 OUTREG(DPLL_B_MD, pI830->saveDPLL_B_MD);