xf86-video-nv: src/g80_driver.c src/nv_driver.c

[Aaron Plattner]

 src/g80_driver.c |    7 ++-----
 src/nv_driver.c  |   19 +++++++++++++++----
 2 files changed, 17 insertions(+), 9 deletions(-)

New commits:
commit e387bf31aae78d4447b4af555a8d09f79f72e6e7
Author: Aaron Plattner <aplattner at nvidia.com>
Date:   Fri Oct 17 20:45:18 2008 -0700

    Only match PCI display devices in our display driver.
    
    Apparently the server needs the driver to tell it that no, we really don't want
    screen sections on our NIC, USB hubs, bridge devices, etc.
    
    Stop whining about PROBE_DETECT in G80 PreInit and just bail out instead.
    
    Bug #18099: Xorg -configure tries to create a screen for every nvidia device.

diff --git a/src/g80_driver.c b/src/g80_driver.c
index 50d55a0..ad8a424 100644
--- a/src/g80_driver.c
+++ b/src/g80_driver.c
@@ -206,11 +206,8 @@ G80PreInit(ScrnInfoPtr pScrn, int flags)
     CARD32 tmp;
     memType BAR1sizeKB;
 
-    if(flags & PROBE_DETECT) {
-        xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-                "G80 PROBE_DETECT unimplemented\n");
-        return FALSE;
-    }
+    if(flags & PROBE_DETECT)
+        return TRUE;
 
     /* Check the number of entities, and fail if it isn't one. */
     if(pScrn->numEntities != 1)
diff --git a/src/nv_driver.c b/src/nv_driver.c
index 831e90b..faf73a9 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -77,11 +77,22 @@ static Bool	NVModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
 static Bool	NVSetModeVBE(ScrnInfoPtr pScrn, DisplayModePtr pMode);
 
 #if XSERVER_LIBPCIACCESS
-/* For now, just match any NVIDIA PCI device and sort through them in the probe
- * routine */
+/* For now, just match any NVIDIA display device and sort through them in the
+ * probe routine */
+
+/*
+ * libpciaccess's masks are shifted by 8 bits compared to the ones in xf86Pci.h.
+ */
+#define LIBPCIACCESS_CLASS_SHIFT (PCI_CLASS_SHIFT - 8)
+#define LIBPCIACCESS_CLASS_MASK (PCI_CLASS_MASK >> 8)
+
 static const struct pci_id_match NVPciIdMatchList[] = {
-    { PCI_VENDOR_NVIDIA, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, 0 },
-    { PCI_VENDOR_NVIDIA_SGS, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, 0},
+    { PCI_VENDOR_NVIDIA, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY,
+      PCI_CLASS_DISPLAY << LIBPCIACCESS_CLASS_SHIFT, LIBPCIACCESS_CLASS_MASK, 0 },
+
+    { PCI_VENDOR_NVIDIA_SGS, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY,
+      PCI_CLASS_DISPLAY << LIBPCIACCESS_CLASS_SHIFT, LIBPCIACCESS_CLASS_MASK, 0 },
+
     { 0, 0, 0 }
 };
 #endif