xf86-video-intel: Branch 'xf86-video-intel-2.5-branch' - 20 commits - configure.ac man/intel.man src/common.h src/i810_reg.h src/i830_crt.c src/i830_display.c src/i830_driver.c src/i830_exa.c src/i830.h src/i830_hdmi.c src/i830_quirks.c src/i830_render.c src/i830_sdvo.c src/i830_sdvo_regs.h src/i830_tv.c src/i830_video.c src/i915_render.c src/i965_render.c src/i965_video.c src/reg_dumper/.gitignore src/reg_dumper/gtt.c
Jesse Barnes
jbarnes at kemper.freedesktop.org
Tue Nov 11 12:52:39 PST 2008
configure.ac | 23 +++--
man/intel.man | 15 +++
src/common.h | 14 +--
src/i810_reg.h | 17 ++++
src/i830.h | 12 +++
src/i830_crt.c | 58 +++++++++-----
src/i830_display.c | 2
src/i830_driver.c | 18 +++-
src/i830_exa.c | 17 ----
src/i830_hdmi.c | 4 -
src/i830_quirks.c | 5 +
src/i830_render.c | 21 +----
src/i830_sdvo.c | 5 +
src/i830_sdvo_regs.h | 137 ++++++++++++++++++++++++++++++++--
src/i830_tv.c | 182 +++++++++++++++++++++++-----------------------
src/i830_video.c | 12 ++-
src/i915_render.c | 21 +----
src/i965_render.c | 23 +----
src/i965_video.c | 2
src/reg_dumper/.gitignore | 1
src/reg_dumper/gtt.c | 2
21 files changed, 373 insertions(+), 218 deletions(-)
New commits:
commit 76e71ddfd4f4b9fb240458ea4c9183b139d50b88
Author: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Tue Nov 11 11:50:50 2008 -0800
Update version to 2.5.1 in preparation for release
diff --git a/configure.ac b/configure.ac
index a53b225..2c956ff 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-intel],
- 2.5.0,
+ 2.5.1,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-intel)
commit a580641cb3fa04c7bbd15f5bc0011cec314375e9
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Fri Nov 7 16:06:26 2008 +0800
quirk LVDS on Asus Eee box
Reported by Yang Sheng <sheng.yang at intel.com>
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 8dae235..155cb44 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -335,6 +335,9 @@ static i830_quirk i830_quirk_list[] = {
{ PCI_CHIP_I855_GM, SUBSYS_ANY, SUBSYS_ANY, quirk_pipea_force },
{ PCI_CHIP_845_G, SUBSYS_ANY, SUBSYS_ANY, quirk_pipea_force },
+ /* Asus Eee Box has no LVDS */
+ { PCI_CHIP_I945_GME, 0x1043, 0x1252, quirk_ignore_lvds },
+
{ 0, 0, 0, NULL },
};
commit 98c9a08257386fa97720f51bc82822b764d5f6bc
Author: Keith Packard <keithp at keithp.com>
Date: Thu Nov 6 15:04:27 2008 -0800
Use long crt hotplug activation time on GM45.
The GM45 b-spec requires the use of the longer hotplug activation period,
but does not require looping twice over the detection logic. With this
patch, CRT detection appears solid on my GM45.
Signed-off-by: Keith Packard <keithp at keithp.com>
diff --git a/src/i810_reg.h b/src/i810_reg.h
index e9c03e5..b391d55 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -1242,7 +1242,22 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define SDVOC_HOTPLUG_INT_EN (1 << 25)
# define TV_HOTPLUG_INT_EN (1 << 18)
# define CRT_HOTPLUG_INT_EN (1 << 9)
+# define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
+/* must use period 64 on GM45 according to docs */
+# define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
+# define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
+# define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
+# define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
+# define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
+# define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
+# define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
+# define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
+# define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
+# define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
# define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
+# define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
+# define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
+# define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
#define PORT_HOTPLUG_STAT 0x61114
# define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
diff --git a/src/i830_crt.c b/src/i830_crt.c
index 479fbe5..ad81fbb 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -158,39 +158,55 @@ i830_crt_detect_hotplug(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- uint32_t temp;
+ uint32_t hotplug_en, temp;
const int timeout_ms = 1000;
int starttime, curtime;
int tries = 1;
+ int try;
- /* On 4 series, CRT detect sequence need to be done twice for safe. */
- if (IS_G4X(pI830))
+ /* On 4 series desktop, CRT detect sequence need to be done twice
+ * to get a reliable result. */
+ if (IS_G4X(pI830) && !IS_GM45(pI830))
tries = 2;
+ else
+ tries = 1;
-retry:
- tries--;
+ hotplug_en = INREG(PORT_HOTPLUG_EN);
- temp = INREG(PORT_HOTPLUG_EN);
+ hotplug_en &= ~CRT_HOTPLUG_MASK;
- OUTREG(PORT_HOTPLUG_EN, temp | CRT_HOTPLUG_FORCE_DETECT | (1 << 5));
+ /* This starts the detection sequence */
+ hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
- for (curtime = starttime = GetTimeInMillis();
- (curtime - starttime) < timeout_ms; curtime = GetTimeInMillis())
- {
- if ((INREG(PORT_HOTPLUG_EN) & CRT_HOTPLUG_FORCE_DETECT) == 0)
- break;
- }
+ /* GM45 requires a longer activation period to reliably
+ * detect CRT
+ */
+ if (IS_GM45(pI830))
+ hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
- if (tries > 0)
- goto retry;
+ /* Use the default voltage value */
+ hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
- if ((INREG(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) ==
- CRT_HOTPLUG_MONITOR_COLOR)
- {
- return TRUE;
- } else {
- return FALSE;
+ for (try = 0; try < tries; try++) {
+ /* turn FORCE_DETECT on */
+ OUTREG(PORT_HOTPLUG_EN, hotplug_en);
+
+ /* wait for FORCE_DETECT to go off */
+ for (curtime = starttime = GetTimeInMillis();
+ (curtime - starttime) < timeout_ms;
+ curtime = GetTimeInMillis())
+ {
+ temp = INREG(PORT_HOTPLUG_EN);
+
+ if ((temp & CRT_HOTPLUG_FORCE_DETECT) == 0)
+ break;
+ }
}
+
+ /* Check the status to see if both blue and green are on now */
+ temp = INREG(PORT_HOTPLUG_STAT);
+ return ((temp & CRT_HOTPLUG_MONITOR_MASK) ==
+ CRT_HOTPLUG_MONITOR_COLOR);
}
/**
commit d8e59840201f7c869a5c267dad22f3babc414926
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Oct 29 20:41:46 2008 +0800
TV: fix timing parameters for PAL, 480p, 1080i
diff --git a/src/i830_tv.c b/src/i830_tv.c
index d02bc11..112c588 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -487,7 +487,7 @@ const static tv_mode_t tv_modes[] = {
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
- .hsync_end = 64, .hblank_end = 128,
+ .hsync_end = 64, .hblank_end = 142,
.hblank_start = 844, .htotal = 863,
.progressive = FALSE, .trilevel_sync = FALSE,
@@ -548,7 +548,7 @@ const static tv_mode_t tv_modes[] = {
.veq_ena = FALSE,
.vi_end_f1 = 44, .vi_end_f2 = 44,
- .nbr_end = 496,
+ .nbr_end = 479,
.burst_ena = FALSE,
@@ -572,7 +572,7 @@ const static tv_mode_t tv_modes[] = {
.veq_ena = FALSE,
.vi_end_f1 = 44, .vi_end_f2 = 44,
- .nbr_end = 496,
+ .nbr_end = 479,
.burst_ena = FALSE,
@@ -733,7 +733,7 @@ const static tv_mode_t tv_modes[] = {
.component_only = 1,
.hsync_end = 88, .hblank_end = 235,
- .hblank_start = 2155, .htotal = 2200,
+ .hblank_start = 2155, .htotal = 2201,
.progressive = FALSE, .trilevel_sync = TRUE,
commit 5a42dd3bda2a4620be7192cab0f1e68d22267f0f
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Oct 29 20:32:18 2008 +0800
TV: save serveral TV_CTL register fields in mode set
Driver should keep those fields according with spec.
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 6458008..e9c03e5 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -1577,7 +1577,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
# define TV_ENC_C0_FIX (1 << 10)
/** Bits that must be preserved by software */
-# define TV_CTL_SAVE ((3 << 8) | (3 << 6))
+# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
# define TV_FUSE_STATE_MASK (3 << 4)
/** Read-only state that reports all features enabled */
# define TV_FUSE_STATE_ENABLED (0 << 4)
diff --git a/src/i830_tv.c b/src/i830_tv.c
index 4063588..d02bc11 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -1042,7 +1042,8 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
if (!tv_mode)
return; /* can't happen (mode_prepare prevents this) */
- tv_ctl = 0;
+ tv_ctl = INREG(TV_CTL);
+ tv_ctl &= TV_CTL_SAVE;
switch (dev_priv->type) {
default:
commit 558eaa44fbe3b1301757bcdb13137d38d06832b4
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Oct 29 20:26:44 2008 +0800
TV: fix default contrast and saturation modifier
Color knobs was set with higher modifier which caused strong color
on TV screen. Setting fixed point modifier to default 1.0 makes picture
on TV look nicer.
diff --git a/src/i830_tv.c b/src/i830_tv.c
index de0e15d..4063588 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -1179,7 +1179,9 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
(i830_float_to_csc(color_conversion->bv) << 16) |
(i830_float_to_luma(color_conversion->av)));
- OUTREG(TV_CLR_KNOBS, 0x00606000);
+ /* 2.6 fixed point value for contrast and saturation modifier,
+ use 1 as default */
+ OUTREG(TV_CLR_KNOBS, 0x00404000);
OUTREG(TV_CLR_LEVEL, ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
(video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
{
commit feeef621d1e3eec7012238d4db47c00c19abbaac
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Oct 29 20:26:03 2008 +0800
TV: white space cleanup
diff --git a/src/i830_tv.c b/src/i830_tv.c
index 0a33357..de0e15d 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -144,7 +144,7 @@ static const uint32_t filter_table[] = {
0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
- 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
+ 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
0x2D002CC0, 0x30003640, 0x2D0036C0,
0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
@@ -215,7 +215,7 @@ typedef struct {
*
* The constants below were all computed using a 107.520MHz clock
*/
-
+
/**
* Register programming values for TV modes.
*
@@ -225,7 +225,7 @@ typedef struct {
const static tv_mode_t tv_modes[] = {
{
.name = "NTSC-M",
- .clock = 107520,
+ .clock = 107520,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -239,7 +239,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
- .veq_ena = TRUE, .veq_start_f1 = 0,
+ .veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
@@ -249,7 +249,7 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
- .vburst_start_f3 = 9, .vburst_end_f3 = 240,
+ .vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f4 = 10, .vburst_end_f4 = 240,
/* desired 3.5800000 actual 3.5800000 clock 107.52 */
@@ -276,7 +276,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "NTSC-443",
- .clock = 107520,
+ .clock = 107520,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -289,7 +289,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
- .veq_ena = TRUE, .veq_start_f1 = 0,
+ .veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
@@ -299,7 +299,7 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
- .vburst_start_f3 = 9, .vburst_end_f3 = 240,
+ .vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f4 = 10, .vburst_end_f4 = 240,
/* desired 4.4336180 actual 4.4336180 clock 107.52 */
@@ -326,7 +326,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "NTSC-J",
- .clock = 107520,
+ .clock = 107520,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -340,7 +340,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
- .veq_ena = TRUE, .veq_start_f1 = 0,
+ .veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
@@ -350,7 +350,7 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
- .vburst_start_f3 = 9, .vburst_end_f3 = 240,
+ .vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f4 = 10, .vburst_end_f4 = 240,
/* desired 3.5800000 actual 3.5800000 clock 107.52 */
@@ -377,7 +377,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "PAL-M",
- .clock = 107520,
+ .clock = 107520,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -391,7 +391,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
- .veq_ena = TRUE, .veq_start_f1 = 0,
+ .veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
@@ -401,7 +401,7 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
- .vburst_start_f3 = 9, .vburst_end_f3 = 240,
+ .vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f4 = 10, .vburst_end_f4 = 240,
/* desired 3.5800000 actual 3.5800000 clock 107.52 */
@@ -429,7 +429,7 @@ const static tv_mode_t tv_modes[] = {
{
/* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
.name = "PAL-N",
- .clock = 107520,
+ .clock = 107520,
.refresh = 25.0,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -443,17 +443,17 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
- .veq_ena = TRUE, .veq_start_f1 = 0,
+ .veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 24, .vi_end_f2 = 25,
.nbr_end = 286,
.burst_ena = TRUE,
- .hburst_start = 73, .hburst_len = 34,
+ .hburst_start = 73, .hburst_len = 34,
.vburst_start_f1 = 8, .vburst_end_f1 = 285,
.vburst_start_f2 = 8, .vburst_end_f2 = 286,
- .vburst_start_f3 = 9, .vburst_end_f3 = 286,
+ .vburst_start_f3 = 9, .vburst_end_f3 = 286,
.vburst_start_f4 = 9, .vburst_end_f4 = 285,
@@ -482,7 +482,7 @@ const static tv_mode_t tv_modes[] = {
{
/* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
.name = "PAL",
- .clock = 107520,
+ .clock = 107520,
.refresh = 25.0,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@@ -495,7 +495,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 5, .vsync_start_f2 = 6,
.vsync_len = 5,
- .veq_ena = TRUE, .veq_start_f1 = 0,
+ .veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 15,
.vi_end_f1 = 24, .vi_end_f2 = 25,
@@ -505,7 +505,7 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 73, .hburst_len = 32,
.vburst_start_f1 = 8, .vburst_end_f1 = 285,
.vburst_start_f2 = 8, .vburst_end_f2 = 286,
- .vburst_start_f3 = 9, .vburst_end_f3 = 286,
+ .vburst_start_f3 = 9, .vburst_end_f3 = 286,
.vburst_start_f4 = 9, .vburst_end_f4 = 285,
/* desired 4.4336180 actual 4.4336180 clock 107.52 */
@@ -532,7 +532,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "480p at 59.94Hz",
- .clock = 107520,
+ .clock = 107520,
.refresh = 59.94,
.oversample = TV_OVERSAMPLE_4X,
.component_only = 1,
@@ -540,7 +540,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 64, .hblank_end = 122,
.hblank_start = 842, .htotal = 857,
- .progressive = TRUE,.trilevel_sync = FALSE,
+ .progressive = TRUE, .trilevel_sync = FALSE,
.vsync_start_f1 = 12, .vsync_start_f2 = 12,
.vsync_len = 12,
@@ -556,7 +556,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "480p at 60Hz",
- .clock = 107520,
+ .clock = 107520,
.refresh = 60.0,
.oversample = TV_OVERSAMPLE_4X,
.component_only = 1,
@@ -564,7 +564,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 64, .hblank_end = 122,
.hblank_start = 842, .htotal = 856,
- .progressive = TRUE,.trilevel_sync = FALSE,
+ .progressive = TRUE, .trilevel_sync = FALSE,
.vsync_start_f1 = 12, .vsync_start_f2 = 12,
.vsync_len = 12,
@@ -580,7 +580,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "576p",
- .clock = 107520,
+ .clock = 107520,
.refresh = 50.0,
.oversample = TV_OVERSAMPLE_4X,
.component_only = 1,
@@ -588,7 +588,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 64, .hblank_end = 139,
.hblank_start = 859, .htotal = 863,
- .progressive = TRUE, .trilevel_sync = FALSE,
+ .progressive = TRUE, .trilevel_sync = FALSE,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
@@ -604,7 +604,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "720p at 60Hz",
- .clock = 148800,
+ .clock = 148800,
.refresh = 60.0,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@@ -612,7 +612,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 80, .hblank_end = 300,
.hblank_start = 1580, .htotal = 1649,
- .progressive = TRUE, .trilevel_sync = TRUE,
+ .progressive = TRUE, .trilevel_sync = TRUE,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
@@ -628,7 +628,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "720p at 59.94Hz",
- .clock = 148800,
+ .clock = 148800,
.refresh = 59.94,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@@ -636,7 +636,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 80, .hblank_end = 300,
.hblank_start = 1580, .htotal = 1651,
- .progressive = TRUE, .trilevel_sync = TRUE,
+ .progressive = TRUE, .trilevel_sync = TRUE,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
@@ -652,7 +652,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "720p at 50Hz",
- .clock = 148800,
+ .clock = 148800,
.refresh = 50.0,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@@ -660,7 +660,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 80, .hblank_end = 300,
.hblank_start = 1580, .htotal = 1979,
- .progressive = TRUE, .trilevel_sync = TRUE,
+ .progressive = TRUE, .trilevel_sync = TRUE,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
@@ -677,7 +677,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "1080i at 50Hz",
- .clock = 148800,
+ .clock = 148800,
.refresh = 25.0,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@@ -685,14 +685,13 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 88, .hblank_end = 235,
.hblank_start = 2155, .htotal = 2639,
- .progressive = FALSE, .trilevel_sync = TRUE,
+ .progressive = FALSE, .trilevel_sync = TRUE,
- .vsync_start_f1 = 4, .vsync_start_f2 = 5,
+ .vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_len = 10,
- .veq_ena = TRUE, .veq_start_f1 = 4,
- .veq_start_f2 = 4, .veq_len = 10,
-
+ .veq_ena = TRUE, .veq_start_f1 = 4,
+ .veq_start_f2 = 4, .veq_len = 10,
.vi_end_f1 = 21, .vi_end_f2 = 22,
.nbr_end = 539,
@@ -703,7 +702,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "1080i at 60Hz",
- .clock = 148800,
+ .clock = 148800,
.refresh = 30.0,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@@ -711,15 +710,14 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 88, .hblank_end = 235,
.hblank_start = 2155, .htotal = 2199,
- .progressive = FALSE, .trilevel_sync = TRUE,
+ .progressive = FALSE, .trilevel_sync = TRUE,
- .vsync_start_f1 = 4, .vsync_start_f2 = 5,
+ .vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_len = 10,
- .veq_ena = TRUE, .veq_start_f1 = 4,
+ .veq_ena = TRUE, .veq_start_f1 = 4,
.veq_start_f2 = 4, .veq_len = 10,
-
.vi_end_f1 = 21, .vi_end_f2 = 22,
.nbr_end = 539,
@@ -729,7 +727,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "1080i at 59.94Hz",
- .clock = 148800,
+ .clock = 148800,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@@ -737,16 +735,16 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 88, .hblank_end = 235,
.hblank_start = 2155, .htotal = 2200,
- .progressive = FALSE, .trilevel_sync = TRUE,
+ .progressive = FALSE, .trilevel_sync = TRUE,
- .vsync_start_f1 = 4, .vsync_start_f2 = 5,
+ .vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_len = 10,
.veq_ena = TRUE, .veq_start_f1 = 4,
- .veq_start_f2 = 4, .veq_len = 10,
+ .veq_start_f2 = 4, .veq_len = 10,
- .vi_end_f1 = 21, .vi_end_f2 = 22,
+ .vi_end_f1 = 21, .vi_end_f2 = 22,
.nbr_end = 539,
.burst_ena = FALSE,
@@ -758,7 +756,7 @@ const static tv_mode_t tv_modes[] = {
#define NUM_TV_MODES sizeof(tv_modes) / sizeof (tv_modes[0])
static const video_levels_t component_level = {
- .blank = 279, .black = 279
+ .blank = 279, .black = 279, .burst = 0,
};
static const color_conversion_t sdtv_component_color = {
@@ -929,8 +927,8 @@ static const tv_mode_t *
i830_tv_mode_lookup (char *tv_format)
{
int i;
-
- for (i = 0; i < sizeof(tv_modes) / sizeof (tv_modes[0]); i++)
+
+ for (i = 0; i < sizeof(tv_modes) / sizeof (tv_modes[0]); i++)
{
const tv_mode_t *tv_mode = &tv_modes[i];
@@ -953,7 +951,7 @@ static int
i830_tv_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
{
const tv_mode_t *tv_mode = i830_tv_mode_find (output);
-
+
if (tv_mode && fabs (tv_mode->refresh - xf86ModeVRefresh (mode)) < 1.0)
return MODE_OK;
return MODE_CLOCK_RANGE;
@@ -971,8 +969,8 @@ i830_tv_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
if (!tv_mode)
return FALSE;
-
- for (i = 0; i < xf86_config->num_output; i++)
+
+ for (i = 0; i < xf86_config->num_output; i++)
{
xf86OutputPtr other_output = xf86_config->output[i];
@@ -1040,10 +1038,10 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
const video_levels_t *video_levels;
const color_conversion_t *color_conversion;
Bool burst_ena;
-
+
if (!tv_mode)
return; /* can't happen (mode_prepare prevents this) */
-
+
tv_ctl = 0;
switch (dev_priv->type) {
@@ -1207,7 +1205,7 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
i830WaitForVblank(pScrn);
/* Filter ctl must be set before TV_WIN_SIZE */
- OUTREG(TV_FILTER_CTL_1, TV_AUTO_SCALE);
+ OUTREG(TV_FILTER_CTL_1, TV_AUTO_SCALE);
xsize = tv_mode->hblank_start - tv_mode->hblank_end;
if (tv_mode->progressive)
ysize = tv_mode->nbr_end + 1;
@@ -1216,9 +1214,9 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
xpos += dev_priv->margin[TV_MARGIN_LEFT];
ypos += dev_priv->margin[TV_MARGIN_TOP];
- xsize -= (dev_priv->margin[TV_MARGIN_LEFT] +
+ xsize -= (dev_priv->margin[TV_MARGIN_LEFT] +
dev_priv->margin[TV_MARGIN_RIGHT]);
- ysize -= (dev_priv->margin[TV_MARGIN_TOP] +
+ ysize -= (dev_priv->margin[TV_MARGIN_TOP] +
dev_priv->margin[TV_MARGIN_BOTTOM]);
OUTREG(TV_WIN_POS, (xpos<<16)|ypos);
OUTREG(TV_WIN_SIZE, (xsize<<16)|ysize);
@@ -1227,7 +1225,7 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
OUTREG(dspcntr_reg, dspcntr);
/* Flush the plane changes */
OUTREG(dspbase_reg, INREG(dspbase_reg));
- }
+ }
j = 0;
for (i = 0; i < 60; i++)
@@ -1381,7 +1379,7 @@ i830_tv_detect(xf86OutputPtr output)
i830_tv_format_configure_property (output);
#endif
}
-
+
switch (type) {
case TV_TYPE_NONE:
return XF86OutputStatusDisconnected;
@@ -1394,8 +1392,8 @@ i830_tv_detect(xf86OutputPtr output)
static struct input_res {
char *name;
- int w, h;
-} input_res_table[] =
+ int w, h;
+} input_res_table[] =
{
{"640x480", 640, 480},
{"800x600", 800, 600},
@@ -1425,16 +1423,16 @@ i830_tv_get_modes(xf86OutputPtr output)
struct input_res *input = &input_res_table[j];
unsigned int hactive_s = input->w;
unsigned int vactive_s = input->h;
-
+
if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
continue;
- if (input->w > 1024 && (!tv_mode->progressive
+ if (input->w > 1024 && (!tv_mode->progressive
&& !tv_mode->component_only))
continue;
mode_ptr = xnfcalloc(1, sizeof(DisplayModeRec));
- mode_ptr->name = xnfalloc(strlen(input->name) + 1);
+ mode_ptr->name = xnfalloc(strlen(input->name) + 1);
strcpy (mode_ptr->name, input->name);
mode_ptr->HDisplay = hactive_s;
@@ -1451,17 +1449,17 @@ i830_tv_get_modes(xf86OutputPtr output)
mode_ptr->VSyncEnd = mode_ptr->VSyncStart + 1;
mode_ptr->VTotal = vactive_s + 33;
- mode_ptr->Clock = (int) (tv_mode->refresh *
- mode_ptr->VTotal *
+ mode_ptr->Clock = (int) (tv_mode->refresh *
+ mode_ptr->VTotal *
mode_ptr->HTotal / 1000.0);
-
+
mode_ptr->type = M_T_DRIVER;
mode_ptr->next = ret;
mode_ptr->prev = NULL;
if (ret != NULL)
ret->prev = mode_ptr;
ret = mode_ptr;
- }
+ }
return ret;
}
@@ -1499,7 +1497,6 @@ i830_tv_format_set_property (xf86OutputPtr output)
return err == Success;
}
-
/**
* Configure the TV_FORMAT property to list only supported formats
*
@@ -1515,16 +1512,16 @@ i830_tv_format_configure_property (xf86OutputPtr output)
Atom current_atoms[NUM_TV_MODES];
int num_atoms = 0;
int i;
-
+
if (!output->randr_output)
return Success;
for (i = 0; i < NUM_TV_MODES; i++)
if (!tv_modes[i].component_only || dev_priv->type == TV_TYPE_COMPONENT)
current_atoms[num_atoms++] = tv_format_name_atoms[i];
-
+
return RRConfigureOutputProperty(output->randr_output, tv_format_atom,
- TRUE, FALSE, FALSE,
+ TRUE, FALSE, FALSE,
num_atoms, (INT32 *) current_atoms);
}
@@ -1573,7 +1570,7 @@ i830_tv_create_resources(xf86OutputPtr output)
range[1] = 100;
err = RRConfigureOutputProperty(output->randr_output, margin_atoms[i],
TRUE, TRUE, FALSE, 2, range);
-
+
if (err != 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RRConfigureOutputProperty error, %d\n", err);
@@ -1595,8 +1592,8 @@ i830_tv_set_property(xf86OutputPtr output, Atom property,
RRPropertyValuePtr value)
{
int i;
-
- if (property == tv_format_atom)
+
+ if (property == tv_format_atom)
{
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_tv_priv *dev_priv = intel_output->dev_priv;
@@ -1609,7 +1606,7 @@ i830_tv_set_property(xf86OutputPtr output, Atom property,
memcpy (&atom, value->data, 4);
name = NameForAtom (atom);
-
+
val = xalloc (strlen (name) + 1);
if (!val)
return FALSE;
@@ -1652,7 +1649,7 @@ i830_tv_get_crtc(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
int pipe = !!(INREG(TV_CTL) & TV_ENC_PIPEB_SELECT);
-
+
return i830_pipe_to_crtc(pScrn, pipe);
}
#endif
@@ -1712,7 +1709,7 @@ i830_tv_init(ScrnInfoPtr pScrn)
* bit, (either as a 0 or a 1), assume it doesn't really
* exist
*/
- if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
+ if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
(tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
return;
@@ -1739,24 +1736,24 @@ i830_tv_init(ScrnInfoPtr pScrn)
dev_priv->type = TV_TYPE_UNKNOWN;
dev_priv->tv_format = NULL;
-
+
/* BIOS margin values */
dev_priv->margin[TV_MARGIN_LEFT] = 54;
dev_priv->margin[TV_MARGIN_TOP] = 36;
dev_priv->margin[TV_MARGIN_RIGHT] = 46;
dev_priv->margin[TV_MARGIN_BOTTOM] = 37;
-
+
if (output->conf_monitor)
{
char *tv_format;
-
+
tv_format = xf86findOptionValue (output->conf_monitor->mon_option_lst, "TV Format");
if (tv_format)
dev_priv->tv_format = xstrdup (tv_format);
}
if (!dev_priv->tv_format)
dev_priv->tv_format = xstrdup (tv_modes[0].name);
-
+
output->driver_private = intel_output;
output->interlaceAllowed = FALSE;
output->doubleScanAllowed = FALSE;
commit d24fcca4e3251098119ca2a50dc73ab3ad2bd6b6
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Nov 6 10:14:00 2008 +0800
SDVO: fix more command definition errors
diff --git a/src/i830_sdvo_regs.h b/src/i830_sdvo_regs.h
index 11e49c8..5d5bf98 100644
--- a/src/i830_sdvo_regs.h
+++ b/src/i830_sdvo_regs.h
@@ -566,7 +566,7 @@ struct i830_sdvo_enhancements_reply {
#define SDVO_CMD_GET_MAX_2D_FLICKER_FITER 0x52
#define SDVO_CMD_GET_MAX_SATURATION 0x55
#define SDVO_CMD_GET_MAX_HUE 0x58
-#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5c
+#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
#define SDVO_CMD_GET_MAX_CONTRAST 0x5e
#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
@@ -580,8 +580,8 @@ struct i830_sdvo_enhancement_limits_reply {
uint16_t default_value;
} __attribute__((packed));
-#define SDVO_CMD_GET_FLICKER_FITER 0x4d
-#define SDVO_CMD_SET_FLICKER_FITER 0x4e
+#define SDVO_CMD_GET_FLICKER_FILTER 0x4e
+#define SDVO_CMD_SET_FLICKER_FILTER 0x4f
#define SDVO_CMD_GET_ADAPTIVE_FLICKER_FITER 0x50
#define SDVO_CMD_SET_ADAPTIVE_FLICKER_FITER 0x51
#define SDVO_CMD_GET_2D_FLICKER_FITER 0x53
commit 7938adce1c848beb83db59eb5fa95bf77c41269c
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Mon Nov 3 16:05:28 2008 +0800
SDVO: add command for set monitor power state
SDVO encoder power state must be higher than monitor's state.
This only adds command and doesn't enable monitor power state
setting yet.
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 75a8d02..4a424de 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -231,8 +231,9 @@ const static struct _sdvo_cmd_name {
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
- SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODER_POWER_STATE),
+ SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
+ SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
diff --git a/src/i830_sdvo_regs.h b/src/i830_sdvo_regs.h
index 5ec22d4..11e49c8 100644
--- a/src/i830_sdvo_regs.h
+++ b/src/i830_sdvo_regs.h
@@ -513,13 +513,29 @@ struct i830_sdvo_hdtv_resolution_reply {
unsigned int pad5:7;
} __attribute__((packed));
+/* Get supported power state returns info for encoder and monitor, rely on
+ last SetTargetInput and SetTargetOutput calls */
#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
-#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
+/* Get power state returns info for encoder and monitor, rely on last
+ SetTargetInput and SetTargetOutput calls */
+#define SDVO_CMD_GET_POWER_STATE 0x2b
+/* Set encoder power state */
#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
# define SDVO_ENCODER_STATE_ON (1 << 0)
# define SDVO_ENCODER_STATE_STANDBY (1 << 1)
# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
# define SDVO_ENCODER_STATE_OFF (1 << 3)
+# define SDVO_MONITOR_STATE_ON (1 << 4)
+# define SDVO_MONITOR_STATE_STANDBY (1 << 5)
+# define SDVO_MONITOR_STATE_SUSPEND (1 << 6)
+# define SDVO_MONITOR_STATE_OFF (1 << 7)
+
+/* Set display power state */
+#define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d
+# define SDVO_DISPLAY_STATE_ON (1 << 0)
+# define SDVO_DISPLAY_STATE_STANDBY (1 << 1)
+# define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)
+# define SDVO_DISPLAY_STATE_OFF (1 << 3)
#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
struct i830_sdvo_enhancements_reply {
commit f649c198f93847747f3d740b422f340788a687c5
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Mon Nov 3 16:01:40 2008 +0800
SDVO: add GetScaledHDTVResolutionSupport command
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 35fccd5..75a8d02 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -235,6 +235,7 @@ const static struct _sdvo_cmd_name {
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
+ SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
/* HDMI op code */
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
@@ -1417,6 +1418,7 @@ i830_sdvo_dump_device(xf86OutputPtr output)
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SUPPORTED_TV_FORMATS);
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_TV_FORMAT);
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT);
+ i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT);
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS);
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SUPP_ENCODE);
diff --git a/src/i830_sdvo_regs.h b/src/i830_sdvo_regs.h
index 7ca85f3..5ec22d4 100644
--- a/src/i830_sdvo_regs.h
+++ b/src/i830_sdvo_regs.h
@@ -422,6 +422,97 @@ struct i830_sdvo_sdtv_resolution_reply {
unsigned int pad:5;
} __attribute__((packed));
+/* Get supported resolution with squire pixel aspect ratio that can be
+ scaled for the requested HDTV format */
+#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
+
+struct i830_sdvo_hdtv_resolution_request {
+ unsigned int hdtv_std_smpte_240m_1080i_59:1;
+ unsigned int hdtv_std_smpte_240m_1080i_60:1;
+ unsigned int hdtv_std_smpte_260m_1080i_59:1;
+ unsigned int hdtv_std_smpte_260m_1080i_60:1;
+ unsigned int hdtv_std_smpte_274m_1080i_50:1;
+ unsigned int hdtv_std_smpte_274m_1080i_59:1;
+ unsigned int hdtv_std_smpte_274m_1080i_60:1;
+ unsigned int hdtv_std_smpte_274m_1080p_23:1;
+
+ unsigned int hdtv_std_smpte_274m_1080p_24:1;
+ unsigned int hdtv_std_smpte_274m_1080p_25:1;
+ unsigned int hdtv_std_smpte_274m_1080p_29:1;
+ unsigned int hdtv_std_smpte_274m_1080p_30:1;
+ unsigned int hdtv_std_smpte_274m_1080p_50:1;
+ unsigned int hdtv_std_smpte_274m_1080p_59:1;
+ unsigned int hdtv_std_smpte_274m_1080p_60:1;
+ unsigned int hdtv_std_smpte_295m_1080i_50:1;
+
+ unsigned int hdtv_std_smpte_295m_1080p_50:1;
+ unsigned int hdtv_std_smpte_296m_720p_59:1;
+ unsigned int hdtv_std_smpte_296m_720p_60:1;
+ unsigned int hdtv_std_smpte_296m_720p_50:1;
+ unsigned int hdtv_std_smpte_293m_480p_59:1;
+ unsigned int hdtv_std_smpte_170m_480i_59:1;
+ unsigned int hdtv_std_iturbt601_576i_50:1;
+ unsigned int hdtv_std_iturbt601_576p_50:1;
+
+ unsigned int hdtv_std_eia_7702a_480i_60:1;
+ unsigned int hdtv_std_eia_7702a_480p_60:1;
+ unsigned int pad:6;
+} __attribute__((packed));
+
+struct i830_sdvo_hdtv_resolution_reply {
+ unsigned int res_640x480:1;
+ unsigned int res_800x600:1;
+ unsigned int res_1024x768:1;
+ unsigned int res_1280x960:1;
+ unsigned int res_1400x1050:1;
+ unsigned int res_1600x1200:1;
+ unsigned int res_1920x1440:1;
+ unsigned int res_2048x1536:1;
+
+ unsigned int res_2560x1920:1;
+ unsigned int res_3200x2400:1;
+ unsigned int res_3840x2880:1;
+ unsigned int pad1:5;
+
+ unsigned int res_848x480:1;
+ unsigned int res_1064x600:1;
+ unsigned int res_1280x720:1;
+ unsigned int res_1360x768:1;
+ unsigned int res_1704x960:1;
+ unsigned int res_1864x1050:1;
+ unsigned int res_1920x1080:1;
+ unsigned int res_2128x1200:1;
+
+ unsigned int res_2560x1400:1;
+ unsigned int res_2728x1536:1;
+ unsigned int res_3408x1920:1;
+ unsigned int res_4264x2400:1;
+ unsigned int res_5120x2880:1;
+ unsigned int pad2:3;
+
+ unsigned int res_768x480:1;
+ unsigned int res_960x600:1;
+ unsigned int res_1152x720:1;
+ unsigned int res_1124x768:1;
+ unsigned int res_1536x960:1;
+ unsigned int res_1680x1050:1;
+ unsigned int res_1728x1080:1;
+ unsigned int res_1920x1200:1;
+
+ unsigned int res_2304x1440:1;
+ unsigned int res_2456x1536:1;
+ unsigned int res_3072x1920:1;
+ unsigned int res_3840x2400:1;
+ unsigned int res_4608x2880:1;
+ unsigned int pad3:3;
+
+ unsigned int res_1280x1024:1;
+ unsigned int pad4:7;
+
+ unsigned int res_1280x768:1;
+ unsigned int pad5:7;
+} __attribute__((packed));
+
#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
commit 83855865ec0a7a220e9dfca7db41a703ab169eca
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Mon Nov 3 15:20:18 2008 +0800
SDVO: fix sdvo tv format and sdtv resolution request/reply definition
diff --git a/src/i830_sdvo_regs.h b/src/i830_sdvo_regs.h
index 53544ae..7ca85f3 100644
--- a/src/i830_sdvo_regs.h
+++ b/src/i830_sdvo_regs.h
@@ -337,15 +337,15 @@ struct i830_sdvo_tv_format {
unsigned int hdtv_std_smpte_240m_1080i_60:1;
unsigned int hdtv_std_smpte_260m_1080i_59:1;
unsigned int hdtv_std_smpte_260m_1080i_60:1;
- unsigned int hdtv_std_smpte_270m_1080i_50:1;
-
unsigned int hdtv_std_smpte_274m_1080i_50:1;
+
unsigned int hdtv_std_smpte_274m_1080i_59:1;
unsigned int hdtv_std_smpte_274m_1080i_60:1;
unsigned int hdtv_std_smpte_274m_1080p_23:1;
unsigned int hdtv_std_smpte_274m_1080p_24:1;
unsigned int hdtv_std_smpte_274m_1080p_25:1;
unsigned int hdtv_std_smpte_274m_1080p_29:1;
+ unsigned int hdtv_std_smpte_274m_1080p_30:1;
unsigned int hdtv_std_smpte_274m_1080p_50:1;
unsigned int hdtv_std_smpte_274m_1080p_59:1;
@@ -357,7 +357,7 @@ struct i830_sdvo_tv_format {
unsigned int hdtv_std_smpte_296m_720p_50:1;
unsigned int hdtv_std_smpte_293m_480p_59:1;
- unsigned int hdtv_std_smpte_270m_480i_59:1;
+ unsigned int hdtv_std_smpte_170m_480i_59:1;
unsigned int hdtv_std_iturbt601_576i_50:1;
unsigned int hdtv_std_iturbt601_576p_50:1;
unsigned int hdtv_std_eia_7702a_480i_60:1;
@@ -386,7 +386,17 @@ struct i830_sdvo_sdtv_resolution_request {
unsigned int pal_n:1;
unsigned int pal_nc:1;
unsigned int pal_60:1;
+ unsigned int secam_b:1;
+ unsigned int secam_d:1;
+ unsigned int secam_g:1;
+ unsigned int secam_k:1;
+
+ unsigned int secam_k1:1;
+ unsigned int secam_l:1;
+ unsigned int secam_60:1;
+ unsigned int pad:5;
} __attribute__((packed));
+
struct i830_sdvo_sdtv_resolution_reply {
unsigned int res_320x200:1;
unsigned int res_320x240:1;
@@ -402,6 +412,7 @@ struct i830_sdvo_sdtv_resolution_reply {
unsigned int res_720x480:1;
unsigned int res_720x540:1;
unsigned int res_720x576:1;
+ unsigned int res_768x576:1;
unsigned int res_800x600:1;
unsigned int res_832x624:1;
commit 6a3fe3c8492e6dca4b56d81fa1c0406696d085d8
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Mon Nov 3 14:59:53 2008 +0800
SDVO: add HDMI audio encrypt change bit for GetInterruptEventSource command
diff --git a/src/i830_sdvo_regs.h b/src/i830_sdvo_regs.h
index be35b8d..53544ae 100644
--- a/src/i830_sdvo_regs.h
+++ b/src/i830_sdvo_regs.h
@@ -210,7 +210,8 @@ struct i830_sdvo_in_out_map {
struct i830_sdvo_get_interrupt_event_source_response {
uint16_t interrupt_status;
unsigned int ambient_light_interrupt:1;
- unsigned int pad:7;
+ unsigned int hdmi_audio_encrypt_change:1;
+ unsigned int pad:6;
} __attribute__((packed));
/**
commit 97498f7e6233f574d537405ab097c9edc36e4290
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Mon Nov 3 14:51:14 2008 +0800
SDVO: fix wrong order of sdvo version's major/minor
diff --git a/src/i830_sdvo_regs.h b/src/i830_sdvo_regs.h
index 4d55555..be35b8d 100644
--- a/src/i830_sdvo_regs.h
+++ b/src/i830_sdvo_regs.h
@@ -50,8 +50,8 @@ struct i830_sdvo_caps {
uint8_t vendor_id;
uint8_t device_id;
uint8_t device_rev_id;
- uint8_t sdvo_version_major;
uint8_t sdvo_version_minor;
+ uint8_t sdvo_version_major;
unsigned int sdvo_input_count:2;
unsigned int smooth_scaling:1;
unsigned int sharp_scaling:1;
commit 179e99463d981487e60ee98f09b5083cf267bea8
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Nov 6 09:46:54 2008 +0800
Make IS_GM45 into IS_G4X define
Those are identical that using one define is much clear.
And it can also apply fixes for GM45 too, which is missing with
origin define.
diff --git a/src/common.h b/src/common.h
index acd5f4a..214932a 100644
--- a/src/common.h
+++ b/src/common.h
@@ -343,9 +343,9 @@ extern int I810_DEBUG;
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
-#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G)
+#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || IS_GM45(pI810))
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_GM45(pI810) || IS_G4X(pI810))
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
@@ -356,16 +356,16 @@ extern int I810_DEBUG;
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* mark chipsets without overlay hw */
-#define OVERLAY_NOEXIST(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
+#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810))
/* chipsets require graphics mem for hardware status page */
#define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \
- (IS_G33CLASS(pI810) || IS_GM45(pI810) || \
+ (IS_G33CLASS(pI810) ||\
IS_G4X(pI810)))
/* chipsets require status page in non stolen memory */
-#define HWS_NEED_NONSTOLEN(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
-#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
+#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810))
+#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810))
/* dsparb controlled by hw only */
-#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_GM45(pI810))
+#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
diff --git a/src/i830_display.c b/src/i830_display.c
index 341def9..006b634 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1126,7 +1126,7 @@ i830_update_dsparb(ScrnInfoPtr pScrn)
/*
* FIFO entries will be split based on programmed modes
*/
- if (IS_I965GM(pI830) || IS_GM45(pI830))
+ if (IS_I965GM(pI830))
fifo_entries = 127;
else if (IS_I9XX(pI830))
fifo_entries = 95;
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 1b62ee8..d882396 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -504,7 +504,7 @@ I830DetectMemory(ScrnInfoPtr pScrn)
range = gtt_size + 4;
/* new 4 series hardware has seperate GTT stolen with GFX stolen */
- if (IS_G4X(pI830) || IS_GM45(pI830))
+ if (IS_G4X(pI830))
range = 4;
if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
@@ -639,7 +639,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- if (IS_GM45(pI830) || IS_G4X(pI830)) {
+ if (IS_G4X(pI830)) {
gttaddr = pI830->MMIOAddr + MB(2);
pI830->GTTMapSize = MB(2);
} else {
@@ -964,7 +964,7 @@ i830_init_clock_gating(ScrnInfoPtr pScrn)
/* Disable clock gating reported to work incorrectly according to the specs.
*/
- if (IS_GM45(pI830) || IS_G4X(pI830)) {
+ if (IS_G4X(pI830)) {
uint32_t dspclk_gate;
OUTREG(RENCLK_GATE_D1, 0);
OUTREG(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
diff --git a/src/i830_hdmi.c b/src/i830_hdmi.c
index 44e5c05..806ca7d 100644
--- a/src/i830_hdmi.c
+++ b/src/i830_hdmi.c
@@ -142,11 +142,11 @@ i830_hdmi_detect(xf86OutputPtr output)
xf86OutputStatus status;
xf86MonPtr edid_mon;
- /* For G4X, PEG_BAND_GAP_DATA 3:0 must first be written 0xd.
+ /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 0xd.
* Failure to do so will result in spurious interrupts being
* generated on the port when a cable is not attached.
*/
- if (IS_G4X(pI830)) {
+ if (IS_G4X(pI830) && !IS_GM45(pI830)) {
temp = INREG(PEG_BAND_GAP_DATA);
OUTREG(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
}
diff --git a/src/i965_render.c b/src/i965_render.c
index e1b37da..6c1d2cb 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1047,7 +1047,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_GM45(pI830) || IS_G4X(pI830))
+ if (IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
diff --git a/src/i965_video.c b/src/i965_video.c
index 78f69ee..37eebb3 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -584,7 +584,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_GM45(pI830) || IS_G4X(pI830))
+ if (IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
diff --git a/src/reg_dumper/gtt.c b/src/reg_dumper/gtt.c
index eca4bc6..ead5935 100644
--- a/src/reg_dumper/gtt.c
+++ b/src/reg_dumper/gtt.c
@@ -52,7 +52,7 @@ int main(int argc, char **argv)
exit(1);
}
- if (IS_G4X(pI830) || IS_GM45(pI830))
+ if (IS_G4X(pI830))
gtt = (unsigned char *)(pI830->mmio + MB(2));
else if (IS_I965G(pI830))
gtt = (unsigned char *)(pI830->mmio + KB(512));
commit da24f26ced9b74fc5dae33c9d329b81be06e5995
Author: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Tue Nov 11 11:31:46 2008 -0800
Make I830FALLBACK debugging a runtime instead of compile-time option.
Conflicts:
src/i965_render.c
diff --git a/man/intel.man b/man/intel.man
index 1d30d1c..ef0337c 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -179,6 +179,12 @@ Default: "EXA".
.BI "Option \*qModeDebug\*q \*q" boolean \*q
Enable printing of additional debugging information about modesetting to
the server log.
+Default: Disabled
+.TP
+.BI "Option \*qFallbackDebug\*q \*q" boolean \*q
+Enable printing of debugging information on acceleration fallbacks to the
+server log.
+Default: Disabled
.TP
.BI "Option \*qForceEnablePipeA\*q \*q" boolean \*q
Force the driver to leave pipe A enabled. May be necessary in configurations
diff --git a/src/i830.h b/src/i830.h
index 711e43c..127ed10 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -717,6 +717,8 @@ typedef struct _I830Rec {
/* User option to ignore SDVO detect bit status, in case some outputs
not detected on SDVO, so let driver try its best. */
Bool force_sdvo_detect;
+ /** User option to print acceleration fallback info to the server log. */
+ Bool fallback_debug;
} I830Rec;
#define I830PTR(p) ((I830Ptr)((p)->driverPrivate))
@@ -961,6 +963,15 @@ static inline int i830_fb_compression_supported(I830Ptr pI830)
return TRUE;
}
+#define I830FALLBACK(s, arg...) \
+do { \
+ if (I830PTR(pScrn)->fallback_debug) { \
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
+ "EXA fallback: " s "\n", ##arg); \
+ } \
+ return FALSE; \
+} while(0)
+
Bool i830_pixmap_tiled(PixmapPtr p);
#define i830_exa_check_pitch_2d(p) do {\
diff --git a/src/i830_driver.c b/src/i830_driver.c
index a2eaf15..1b62ee8 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -303,6 +303,7 @@ typedef enum {
OPTION_COLOR_KEY,
OPTION_CHECKDEVICES,
OPTION_MODEDEBUG,
+ OPTION_FALLBACKDEBUG,
OPTION_LVDS24BITMODE,
OPTION_FBC,
OPTION_TILING,
@@ -329,6 +330,7 @@ static OptionInfoRec I830Options[] = {
{OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE},
{OPTION_CHECKDEVICES, "CheckDevices",OPTV_BOOLEAN, {0}, FALSE},
{OPTION_MODEDEBUG, "ModeDebug", OPTV_BOOLEAN, {0}, FALSE},
+ {OPTION_FALLBACKDEBUG, "FallbackDebug", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_LVDS24BITMODE, "LVDS24Bit", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_FBC, "FramebufferCompression", OPTV_BOOLEAN, {0}, TRUE},
{OPTION_TILING, "Tiling", OPTV_BOOLEAN, {0}, TRUE},
@@ -1436,6 +1438,9 @@ I830GetEarlyOptions(ScrnInfoPtr pScrn)
memcpy(pI830->Options, I830Options, sizeof(I830Options));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, pI830->Options);
+ pI830->fallback_debug = xf86ReturnOptValBool(pI830->Options,
+ OPTION_FALLBACKDEBUG, FALSE);
+
if (xf86ReturnOptValBool(pI830->Options, OPTION_MODEDEBUG, FALSE)) {
pI830->debug_modes = TRUE;
} else {
diff --git a/src/i830_exa.c b/src/i830_exa.c
index e1cf24e..9fcda51 100644
--- a/src/i830_exa.c
+++ b/src/i830_exa.c
@@ -37,26 +37,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "i810_reg.h"
#include <string.h>
-#ifdef I830DEBUG
-#define DEBUG_I830FALLBACK 1
-#endif
-
#define ALWAYS_SYNC 0
#define ALWAYS_FLUSH 0
-#ifdef DEBUG_I830FALLBACK
-#define I830FALLBACK(s, arg...) \
-do { \
- DPRINTF(PFX, "EXA fallback: " s "\n", ##arg); \
- return FALSE; \
-} while(0)
-#else
-#define I830FALLBACK(s, arg...) \
-do { \
- return FALSE; \
-} while(0)
-#endif
-
const int I830CopyROP[16] =
{
ROP_0, /* GXclear */
diff --git a/src/i830_render.c b/src/i830_render.c
index 7b05daa..d3b0f7c 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -34,23 +34,6 @@
#include "i830.h"
#include "i830_reg.h"
-#ifdef I830DEBUG
-#define DEBUG_I830FALLBACK 1
-#endif
-
-#ifdef DEBUG_I830FALLBACK
-#define I830FALLBACK(s, arg...) \
-do { \
- DPRINTF(PFX, "EXA fallback: " s "\n", ##arg); \
- return FALSE; \
-} while(0)
-#else
-#define I830FALLBACK(s, arg...) \
-do { \
- return FALSE; \
-} while(0)
-#endif
-
struct blendinfo {
Bool dst_alpha;
Bool src_alpha;
@@ -160,6 +143,8 @@ static struct formatinfo i830_tex_formats[] = {
static Bool i830_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
{
+ ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
+
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
case PICT_x8r8g8b8:
@@ -227,6 +212,7 @@ static uint32_t i830_get_blend_cntl(int op, PicturePtr pMask,
static Bool i830_check_composite_texture(PicturePtr pPict, int unit)
{
+ ScrnInfoPtr pScrn = xf86Screens[pPict->pDrawable->pScreen->myNum];
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i;
@@ -371,6 +357,7 @@ Bool
i830_check_composite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
PicturePtr pDstPicture)
{
+ ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
uint32_t tmp1;
/* Check for unsupported compositing operations. */
diff --git a/src/i915_render.c b/src/i915_render.c
index 039db3b..ab288e1 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -35,23 +35,6 @@
#include "i915_reg.h"
#include "i915_3d.h"
-#ifdef I830DEBUG
-#define DEBUG_I830FALLBACK 1
-#endif
-
-#ifdef DEBUG_I830FALLBACK
-#define I830FALLBACK(s, arg...) \
-do { \
- DPRINTF(PFX, "EXA fallback: " s "\n", ##arg); \
- return FALSE; \
-} while(0)
-#else
-#define I830FALLBACK(s, arg...) \
-do { \
- return FALSE; \
-} while(0)
-#endif
-
struct formatinfo {
int fmt;
uint32_t card_fmt;
@@ -155,6 +138,8 @@ static uint32_t i915_get_blend_cntl(int op, PicturePtr pMask,
static Bool i915_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
{
+ ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
+
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
case PICT_x8r8g8b8:
@@ -184,6 +169,7 @@ static Bool i915_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
static Bool i915_check_composite_texture(PicturePtr pPict, int unit)
{
+ ScrnInfoPtr pScrn = xf86Screens[pPict->pDrawable->pScreen->myNum];
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i;
@@ -215,6 +201,7 @@ Bool
i915_check_composite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
PicturePtr pDstPicture)
{
+ ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
uint32_t tmp1;
/* Check for unsupported compositing operations. */
diff --git a/src/i965_render.c b/src/i965_render.c
index 9ee273c..e1b37da 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -42,23 +42,6 @@
#include "brw_defines.h"
#include "brw_structs.h"
-#ifdef I830DEBUG
-#define DEBUG_I830FALLBACK 1
-#endif
-
-#ifdef DEBUG_I830FALLBACK
-#define I830FALLBACK(s, arg...) \
-do { \
- DPRINTF(PFX, "EXA fallback: " s "\n", ##arg); \
- return FALSE; \
-} while(0)
-#else
-#define I830FALLBACK(s, arg...) \
-do { \
- return FALSE; \
-} while(0)
-#endif
-
#define MAX_VERTEX_PER_COMPOSITE 24
#define MAX_VERTEX_BUFFERS 256
@@ -161,6 +144,8 @@ static void i965_get_blend_cntl(int op, PicturePtr pMask, uint32_t dst_format,
static Bool i965_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
{
+ ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
+
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
case PICT_x8r8g8b8:
@@ -192,6 +177,7 @@ static Bool i965_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
static Bool i965_check_composite_texture(PicturePtr pPict, int unit)
{
+ ScrnInfoPtr pScrn = xf86Screens[pPict->pDrawable->pScreen->myNum];
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i;
@@ -226,6 +212,7 @@ Bool
i965_check_composite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
PicturePtr pDstPicture)
{
+ ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
uint32_t tmp1;
/* Check for unsupported compositing operations. */
commit 24c34f020a3b23e0236aaac77b271d4390ab7619
Author: Maxim Levitsky <maximlevitsky at gmail.com>
Date: Wed Nov 5 13:47:09 2008 -0800
Add an option to make the overlay be the first XV adaptor.
diff --git a/man/intel.man b/man/intel.man
index 15ab234..1d30d1c 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -134,6 +134,15 @@ other drivers.
Disable or enable XVideo support.
Default: XVideo is enabled for configurations where it is supported.
.TP
+.BI "Option \*qXvPreferOverlay\*q \*q" boolean \*q
+Make hardware overlay be the first XV adaptor.
+The overlay behaves incorrectly in the presence of compositing, but some prefer
+it due to it syncing to vblank in the absence of compositing. While most
+XV-using applications have options to select which XV adaptor to use, this
+option can be used to place the overlay first for applications which don't
+have options for selecting adaptors.
+Default: Textured video adaptor is preferred.
+.TP
.BI "Option \*qLegacy3D\*q \*q" boolean \*q
Enable support for the non-GEM mode of the 3D driver on i830 and newer.
This will allocate a large static area for older Mesa to use for its texture
diff --git a/src/i830.h b/src/i830.h
index 5da4181..711e43c 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -554,6 +554,7 @@ typedef struct _I830Rec {
Bool XvDisabled; /* Xv disabled in PreInit. */
Bool XvEnabled; /* Xv enabled for this generation. */
+ Bool XvPreferOverlay;
#ifdef I830_XV
int colorKey;
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 4ffcd5f..a2eaf15 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -314,6 +314,7 @@ typedef enum {
OPTION_XVMC,
#endif
OPTION_FORCE_SDVO_DETECT,
+ OPTION_PREFER_OVERLAY,
} I830Opts;
static OptionInfoRec I830Options[] = {
@@ -341,6 +342,7 @@ static OptionInfoRec I830Options[] = {
{OPTION_XVMC, "XvMC", OPTV_BOOLEAN, {0}, TRUE},
#endif
{OPTION_FORCE_SDVO_DETECT, "ForceSDVODetect", OPTV_BOOLEAN, {0}, FALSE},
+ {OPTION_PREFER_OVERLAY, "XvPreferOverlay", OPTV_BOOLEAN, {0}, FALSE},
{-1, NULL, OPTV_NONE, {0}, FALSE}
};
/* *INDENT-ON* */
@@ -1689,6 +1691,8 @@ I830XvInit(ScrnInfoPtr pScrn)
pI830->XvDisabled =
!xf86ReturnOptValBool(pI830->Options, OPTION_XVIDEO, TRUE);
+ pI830->XvPreferOverlay = xf86ReturnOptValBool(pI830->Options, OPTION_PREFER_OVERLAY, FALSE);
+
#ifdef I830_XV
if (xf86GetOptValInteger(pI830->Options, OPTION_VIDEO_KEY,
&(pI830->colorKey))) {
diff --git a/src/i830_video.c b/src/i830_video.c
index 316bc61..216ed47 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -611,7 +611,6 @@ I830InitVideo(ScreenPtr pScreen)
{
texturedAdaptor = I830SetupImageVideoTextured(pScreen);
if (texturedAdaptor != NULL) {
- adaptors[num_adaptors++] = texturedAdaptor;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -625,7 +624,6 @@ I830InitVideo(ScreenPtr pScreen)
{
overlayAdaptor = I830SetupImageVideoOverlay(pScreen);
if (overlayAdaptor != NULL) {
- adaptors[num_adaptors++] = overlayAdaptor;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up overlay video\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -633,6 +631,16 @@ I830InitVideo(ScreenPtr pScreen)
}
I830InitOffscreenImages(pScreen);
}
+
+ if (overlayAdaptor && pI830->XvPreferOverlay)
+ adaptors[num_adaptors++] = overlayAdaptor;
+
+ if (texturedAdaptor)
+ adaptors[num_adaptors++] = texturedAdaptor;
+
+ if (overlayAdaptor && !pI830->XvPreferOverlay)
+ adaptors[num_adaptors++] = overlayAdaptor;
+
#ifdef INTEL_XVMC
if (intel_xvmc_probe(pScrn)) {
if (texturedAdaptor)
commit 8e017206f8ed8b3986f5f2c04580ad99a2745a91
Author: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Thu Oct 30 13:40:23 2008 -0700
Don't modify render standby if kernel mode setting is active
Since we can't bang on registers directly in that case.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 25bcb47..4ffcd5f 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -3313,7 +3313,8 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
return FALSE;
}
- i830_disable_render_standby(pScrn);
+ if (!pI830->use_drm_mode)
+ i830_disable_render_standby(pScrn);
DPRINTF(PFX, "assert( if(!I830EnterVT(scrnIndex, 0)) )\n");
commit 631cfb0a5721334537e693a8b97f07ab26fbb857
Author: Adam Jackson <ajax at redhat.com>
Date: Fri Oct 24 14:47:27 2008 -0400
Quirk: No LVDS on Dell Studio Hybrid
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 12cab86..8dae235 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -255,6 +255,8 @@ static i830_quirk i830_quirk_list[] = {
{ PCI_CHIP_I965_GM, 0x1028, 0x0286, quirk_ignore_tv },
/* Dell Vostro A840 (LP: #235155) */
{ PCI_CHIP_I965_GM, 0x1028, 0x0298, quirk_ignore_tv },
+ /* Dell Studio Hybrid */
+ { PCI_CHIP_I965_GM, 0x1028, 0x0279, quirk_ignore_lvds },
/* Lenovo Napa TV (use dmi)*/
{ PCI_CHIP_I945_GM, 0x17aa, SUBSYS_ANY, quirk_lenovo_tv_dmi },
commit 378778aa8eb6a26e33c5051aa20d4e0e52249004
Author: Carl Worth <cworth at cworth.org>
Date: Wed Oct 22 14:51:42 2008 -0700
Ignore intel_gtt binary
We simply forgot to add this to .gitignore when it was created.
diff --git a/src/reg_dumper/.gitignore b/src/reg_dumper/.gitignore
index 0adc8b2..5aac542 100644
--- a/src/reg_dumper/.gitignore
+++ b/src/reg_dumper/.gitignore
@@ -1,3 +1,4 @@
+intel_gtt
intel_hotplug
intel_idle
intel_reg_dumper
commit 3b4965416052273da2bbf1166492c8e4b54966b4
Author: Dave Airlie <airlied at linux.ie>
Date: Mon Oct 20 18:46:49 2008 -0700
Default kernel mode setting to off, add configure flag to enable
Should help avoid unpleasantness.
diff --git a/configure.ac b/configure.ac
index 67ccbdf..a53b225 100644
--- a/configure.ac
+++ b/configure.ac
@@ -75,6 +75,11 @@ AC_ARG_ENABLE(xvmc, AC_HELP_STRING([--disable-xvmc],
[XVMC="$enableval"],
[XVMC=auto])
+AC_ARG_ENABLE(kms, AC_HELP_STRING([--enable-kms],
+ [Enable kernel mode setting support [[default=no]]]),
+ [KMS="$enableval"],
+ [KMS=no])
+
# Checks for extensions
XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto)
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
@@ -107,13 +112,15 @@ if test x$DRI != xno; then
[have_dristruct_h="yes"], [have_dristruct_h="no"])
AC_CHECK_FILE([${sdkdir}/damage.h],
[have_damage_h="yes"], [have_damage_h="no"])
- AC_CHECK_HEADER(xf86drmMode.h,
- [DRM_MODE=yes],[DRM_MODE=no]
- [#include "stdint.h"])
- dnl exaGetPixmapDriverPrivate required for DRM_MODE.
- PKG_CHECK_MODULES(DRM_MODE, [xorg-server >= 1.5], [], [DRM_MODE=no])
- if test "x$DRM_MODE" = xyes; then
- AC_DEFINE(XF86DRM_MODE,1,[DRM kernel modesetting])
+ if test x$KMS != xno; then
+ AC_CHECK_HEADER(xf86drmMode.h,
+ [DRM_MODE=yes],[DRM_MODE=no]
+ [#include "stdint.h"])
+ dnl exaGetPixmapDriverPrivate required for DRM_MODE.
+ PKG_CHECK_MODULES(DRM_MODE, [xorg-server >= 1.5], [], [DRM_MODE=no])
+ if test "x$DRM_MODE" = xyes; then
+ AC_DEFINE(XF86DRM_MODE,1,[DRM kernel modesetting])
+ fi
fi
fi
AC_MSG_CHECKING([whether to include DRI support])
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