xf86-video-ati: Branch 'master'
Alex Deucher
agd5f at kemper.freedesktop.org
Tue May 13 17:52:24 PDT 2008
src/legacy_crtc.c | 18 ++++++++++++------
src/legacy_output.c | 29 +++++++++++++++++++----------
src/pcidb/ati_pciids.csv | 12 ++++++------
src/radeon.h | 9 ++++++---
src/radeon_accel.c | 1 +
src/radeon_bios.c | 13 +++++++------
src/radeon_chipinfo_gen.h | 12 ++++++------
src/radeon_driver.c | 28 ++++++++++++++++------------
src/radeon_exa_funcs.c | 6 +++---
src/radeon_exa_render.c | 1 +
src/radeon_output.c | 14 +++++++++-----
src/radeon_video.c | 3 ++-
12 files changed, 88 insertions(+), 58 deletions(-)
New commits:
commit 582c1a1b2c7b1032e9f9f54ca36100c57f580c5c
Author: Alex Deucher <alex at cube.(none)>
Date: Tue May 13 20:50:25 2008 -0400
RS4xx: Split out RS400 and RS480 as separate families
RS400 (intel based IGP) and RS480 (AMD based IGP) have different
MC setups and need to be handled differently
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index c4e1650..489fecf 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -78,7 +78,8 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
OUTREG(RADEON_BUS_CNTL, restore->bus_cntl);
OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl);
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
OUTREG(RS400_DISP2_REQ_CNTL1, restore->disp2_req_cntl1);
OUTREG(RS400_DISP2_REQ_CNTL2, restore->disp2_req_cntl2);
OUTREG(RS400_DMIF_MEM_CNTL1, restore->dmif_mem_cntl1);
@@ -330,7 +331,8 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
if (IS_R300_VARIANT ||
(info->ChipFamily == CHIP_FAMILY_RS300) ||
- (info->ChipFamily == CHIP_FAMILY_RS400)) {
+ (info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
/* When restoring console mode, use saved PPLL_REF_DIV
* setting.
@@ -491,7 +493,8 @@ RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL);
save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL);
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1);
save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2);
save->dmif_mem_cntl1 = INREG(RS400_DMIF_MEM_CNTL1);
@@ -679,7 +682,8 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
save->cap1_trig_cntl = 0;
save->bus_cntl = info->BusCntl;
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1;
save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2;
save->dmif_mem_cntl1 = info->SavedReg->dmif_mem_cntl1;
@@ -1557,7 +1561,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
#if 0
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
/* attempt to program RS400 disp regs correctly ??? */
temp = info->SavedReg->disp1_req_cntl1;
temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
@@ -1624,7 +1629,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
#if 0
/* attempt to program RS400 disp2 regs correctly ??? */
temp = info->SavedReg->disp2_req_cntl1;
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 962887a..337370b 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -71,7 +71,7 @@ RADEONRestoreDACRegisters(ScrnInfoPtr pScrn,
OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
if ((info->ChipFamily != CHIP_FAMILY_RADEON) &&
- (info->ChipFamily != CHIP_FAMILY_R200))
+ (info->ChipFamily != CHIP_FAMILY_R200))
OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
@@ -103,7 +103,8 @@ RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl);
OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl);
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
OUTREG(RS400_FP_2ND_GEN_CNTL, restore->fp_2nd_gen_cntl);
/*OUTREG(RS400_TMDS2_CNTL, restore->tmds2_cntl);*/
OUTREG(RS400_TMDS2_TRANSMITTER_CNTL, restore->tmds2_transmitter_cntl);
@@ -127,7 +128,8 @@ RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl);
- if (info->ChipFamily == CHIP_FAMILY_RS400)
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480))
OUTREG(RS400_FP2_2_GEN_CNTL, restore->fp2_2_gen_cntl);
}
@@ -212,7 +214,8 @@ RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
save->tmds_pll_cntl ^= (1 << 22);
}
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
save->fp_2nd_gen_cntl = INREG(RS400_FP_2ND_GEN_CNTL);
save->fp2_2_gen_cntl = INREG(RS400_FP2_2_GEN_CNTL);
save->tmds2_cntl = INREG(RS400_TMDS2_CNTL);
@@ -732,7 +735,8 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
OUTREG(RADEON_FP_GEN_CNTL, tmp);
save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
tmp = INREG(RS400_FP_2ND_GEN_CNTL);
tmp |= (RS400_FP_2ND_ON | RS400_TMDS_2ND_EN);
OUTREG(RS400_FP_2ND_GEN_CNTL, tmp);
@@ -747,7 +751,8 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
OUTREG(RADEON_FP2_GEN_CNTL, tmp);
save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
tmp = INREG(RS400_FP2_2_GEN_CNTL);
tmp &= ~RS400_FP2_2_BLANK_EN;
tmp |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
@@ -811,7 +816,8 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
OUTREG(RADEON_FP_GEN_CNTL, tmp);
save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
tmp = INREG(RS400_FP_2ND_GEN_CNTL);
tmp &= ~(RS400_FP_2ND_ON | RS400_TMDS_2ND_EN);
OUTREG(RS400_FP_2ND_GEN_CNTL, tmp);
@@ -828,7 +834,8 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
OUTREG(RADEON_FP2_GEN_CNTL, tmp);
save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
tmp = INREG(RS400_FP2_2_GEN_CNTL);
tmp |= RS400_FP2_2_BLANK_EN;
tmp &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
@@ -964,7 +971,8 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
}
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
save->tmds2_transmitter_cntl = info->SavedReg->tmds2_transmitter_cntl &
~(RS400_TMDS2_PLLRST);
save->tmds2_transmitter_cntl &= ~(RS400_TMDS2_PLLEN);
@@ -1037,7 +1045,8 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
}
}
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
if (pScrn->rgbBits == 8)
save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl |
RS400_FP2_2_PANEL_FORMAT; /* 24 bit format, */
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index fc340e7..7308ce9 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -179,20 +179,20 @@
"0x5656","MACH64VV","MACH64",,,,,,
"0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5) 5834"
"0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3) 5835"
-"0x5954","RS480_5954","RS400",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)"
-"0x5955","RS480_5955","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)"
+"0x5954","RS480_5954","RS480",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)"
+"0x5955","RS480_5955","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)"
"0x5960","RV280_5960","RV280",,,,,,"ATI Radeon 9250 5960 (AGP)"
"0x5961","RV280_5961","RV280",,,,,,"ATI Radeon 9200 5961 (AGP)"
"0x5962","RV280_5962","RV280",,,,,,"ATI Radeon 9200 5962 (AGP)"
"0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE 5964 (AGP)"
"0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200 (PCI)"
"0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000 5969 (PCI)"
-"0x5974","RS482_5974","RS400",1,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)"
-"0x5975","RS485_5975","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)"
+"0x5974","RS482_5974","RS480",1,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)"
+"0x5975","RS485_5975","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)"
"0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)"
"0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)"
-"0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)"
-"0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)"
+"0x5A61","RC410_5A61","RS480",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)"
+"0x5A62","RC410_5A62","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)"
"0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)"
"0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)"
"0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)"
diff --git a/src/radeon.h b/src/radeon.h
index 93b1aa7..a7bf5e4 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -262,7 +262,8 @@ typedef enum {
CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
CHIP_FAMILY_R420, /* R420/R423/M18 */
CHIP_FAMILY_RV410, /* RV410, M26 */
- CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */
+ CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */
+ CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */
CHIP_FAMILY_RV515, /* rv515 */
CHIP_FAMILY_R520, /* r520 */
CHIP_FAMILY_RV530, /* rv530 */
@@ -297,7 +298,8 @@ typedef enum {
(info->ChipFamily == CHIP_FAMILY_RV380) || \
(info->ChipFamily == CHIP_FAMILY_R420) || \
(info->ChipFamily == CHIP_FAMILY_RV410) || \
- (info->ChipFamily == CHIP_FAMILY_RS400))
+ (info->ChipFamily == CHIP_FAMILY_RS400) || \
+ (info->ChipFamily == CHIP_FAMILY_RS480))
#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515))
@@ -318,7 +320,8 @@ typedef enum {
(info->ChipFamily == CHIP_FAMILY_RV410) || \
(info->ChipFamily == CHIP_FAMILY_RS690) || \
(info->ChipFamily == CHIP_FAMILY_RS740) || \
- (info->ChipFamily == CHIP_FAMILY_RS400))
+ (info->ChipFamily == CHIP_FAMILY_RS400) || \
+ (info->ChipFamily == CHIP_FAMILY_RS480))
/*
* Errata workarounds
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index d2851a7..2351213 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -375,6 +375,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
(info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740) ||
(info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480) ||
IS_R500_3D) {
uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
if (info->num_gb_pipes == 0) {
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index a3efe29..fa09aae 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -221,17 +221,18 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
- /* most XPRESS chips seem to specify DDC_CRT2 for their
- * VGA DDC port, however DDC never seems to work on that
- * port. Some have reported success on DDC_MONID, so
- * lets see what happens with that.
+ /* on XPRESS chips, CRT2_DDC and MONID_DCC both use the
+ * MONID gpio, but use different pins.
+ * CRT2_DDC uses the standard pinout, MONID_DDC uses
+ * something else.
*/
- if (info->ChipFamily == CHIP_FAMILY_RS400 &&
+ if ((info->ChipFamily == CHIP_FAMILY_RS400 ||
+ info->ChipFamily == CHIP_FAMILY_RS480) &&
info->BiosConnector[index].ConnectorType == CONNECTOR_VGA &&
info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
}
-
+
/* XPRESS desktop chips seem to have a proprietary connector listed for
* DVI-D, try and do the right thing here.
*/
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index de1d109..a3540ca 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -98,20 +98,20 @@ RADEONCardInfo RADEONCards[] = {
{ 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
{ 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 },
{ 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 },
- { 0x5954, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
- { 0x5955, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
+ { 0x5954, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 },
+ { 0x5955, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
{ 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
- { 0x5974, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
- { 0x5975, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
+ { 0x5974, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
+ { 0x5975, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
{ 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
{ 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
- { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
- { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
+ { 0x5A61, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 },
+ { 0x5A62, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
{ 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 36994c8..215886e 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -928,12 +928,12 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
xtal = 2700;
} else {
if (prev_xtal == 0) {
- prev_xtal = xtal;
- tries = 0;
- goto again;
+ prev_xtal = xtal;
+ tries = 0;
+ goto again;
} else if (prev_xtal != xtal) {
- prev_xtal = 0;
- goto again;
+ prev_xtal = 0;
+ goto again;
}
}
@@ -944,14 +944,16 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
if (ref_div < 2) {
uint32_t tmp;
tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV);
- if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS300)
- || (info->ChipFamily == CHIP_FAMILY_RS400))
- ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >>
- R300_PPLL_REF_DIV_ACC_SHIFT;
+ if (IS_R300_VARIANT
+ || (info->ChipFamily == CHIP_FAMILY_RS300)
+ || (info->ChipFamily == CHIP_FAMILY_RS400)
+ || (info->ChipFamily == CHIP_FAMILY_RS480))
+ ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >>
+ R300_PPLL_REF_DIV_ACC_SHIFT;
else
- ref_div = tmp & RADEON_PPLL_REF_DIV_MASK;
+ ref_div = tmp & RADEON_PPLL_REF_DIV_MASK;
if (ref_div < 2)
- ref_div = 12;
+ ref_div = 12;
}
/* Calculate "base" xclk straight from MPLL, though that isn't
@@ -1025,7 +1027,8 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV);
if (IS_R300_VARIANT ||
(info->ChipFamily == CHIP_FAMILY_RS300) ||
- (info->ChipFamily == CHIP_FAMILY_RS400)) {
+ (info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
} else {
pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
@@ -1812,6 +1815,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
(info->ChipFamily == CHIP_FAMILY_RS200) ||
(info->ChipFamily == CHIP_FAMILY_RS300) ||
(info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480) ||
(info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740))
info->has_tcl = FALSE;
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 80f3be9..13a7de5 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -551,9 +551,9 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
} else
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA Composite requires CP on R5xx/IGP\n");
- } else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_RV280) ||
- (info->ChipFamily == CHIP_FAMILY_RS300) ||
+ } else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
+ (info->ChipFamily == CHIP_FAMILY_RV280) ||
+ (info->ChipFamily == CHIP_FAMILY_RS300) ||
(info->ChipFamily == CHIP_FAMILY_R200)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
"enabled for R200 type cards.\n");
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index f519a3e..38959e6 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -2109,6 +2109,7 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst)
ENTER_DRAW(0);
if (IS_R500_3D || ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480) ||
(info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740))) {
/* r500 shows corruption on small things like glyphs without a 3D idle
diff --git a/src/radeon_output.c b/src/radeon_output.c
index f5d82cb..59bc990 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -1113,11 +1113,13 @@ radeon_detect(xf86OutputPtr output)
*/
if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) &&
(radeon_output->DACType == DAC_TVDAC) &&
- (info->ChipFamily == CHIP_FAMILY_RS400)) {
+ ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480))) {
radeon_output->MonType = MT_CRT;
return XF86OutputStatusUnknown;
- } else if ((info->ChipFamily == CHIP_FAMILY_RS400) &&
- radeon_output->type == OUTPUT_DVI_D) {
+ } else if (((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) &&
+ radeon_output->type == OUTPUT_DVI_D) {
radeon_output->MonType = MT_DFP; /* MT_LCD ??? */
return XF86OutputStatusUnknown;
}
@@ -2474,7 +2476,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].valid = TRUE;
/* IGP only has TVDAC */
- if (info->ChipFamily == CHIP_FAMILY_RS400)
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480))
info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
else
info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
@@ -2502,7 +2505,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
} else {
/* Below is the most common setting, but may not be true */
if (info->IsIGP) {
- if (info->ChipFamily == CHIP_FAMILY_RS400)
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480))
info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
else
info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
diff --git a/src/radeon_video.c b/src/radeon_video.c
index d4b9ac4..ab1ed8d 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -2987,7 +2987,8 @@ RADEONPutImage(
case FOURCC_I420:
/* it seems rs4xx chips (all of them???) either can't handle planar
yuv at all or would need some unknown different setup. */
- if (info->ChipFamily != CHIP_FAMILY_RS400) {
+ if ((info->ChipFamily != CHIP_FAMILY_RS400) &&
+ (info->ChipFamily != CHIP_FAMILY_RS480)) {
/* need 16bytes alignment for u,v plane, so 2 times that for width
but blitter needs 64bytes alignment. 128byte is a waste but dstpitch
for uv planes needs to be dstpitch yplane >> 1 for now. */
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