xf86-video-ati: Branch 'master' - 2 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Mar 24 11:26:14 PDT 2008
src/radeon_commonfuncs.c | 29 ++-
src/radeon_exa_render.c | 315 ++++++---------------------------------
src/radeon_textured_videofuncs.c | 230 +++++-----------------------
3 files changed, 117 insertions(+), 457 deletions(-)
New commits:
commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 24 14:25:03 2008 -0400
R3xx/R5xx: move more VAP, etc. state setup into common init3d() function
Also some minor code cleanups
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 45dc14b..a370e5b 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -60,9 +60,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_RS690) ||
- (info->ChipFamily == CHIP_FAMILY_RS740)) {
+ if (IS_R300_3D || IS_R500_3D) {
BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
@@ -151,7 +149,19 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0);
FINISH_ACCEL();
- BEGIN_ACCEL(5);
+ /* setup the VAP */
+ BEGIN_ACCEL(4);
+ /* disable TCL/PVS */
+ OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
+ OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (4 << R300_PVS_NUM_FPUS_SHIFT) |
+ (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
+ OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
+ FINISH_ACCEL();
+
+ BEGIN_ACCEL(4);
OUT_ACCEL_REG(R300_US_W_FMT, 0);
OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
R300_OUT_FMT_C0_SEL_BLUE |
@@ -168,11 +178,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
R300_OUT_FMT_C1_SEL_GREEN |
R300_OUT_FMT_C2_SEL_RED |
R300_OUT_FMT_C3_SEL_ALPHA));
- OUT_ACCEL_REG(R300_US_OUT_FMT_0, (R300_OUT_FMT_C4_10 |
- R300_OUT_FMT_C0_SEL_BLUE |
- R300_OUT_FMT_C1_SEL_GREEN |
- R300_OUT_FMT_C2_SEL_RED |
- R300_OUT_FMT_C3_SEL_ALPHA));
FINISH_ACCEL();
@@ -182,7 +187,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0);
FINISH_ACCEL();
- BEGIN_ACCEL(12);
+ BEGIN_ACCEL(13);
+ OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0);
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0);
@@ -208,8 +214,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
(8191 << R300_SCISSOR_Y_SHIFT)));
- if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690) ||
- (info->ChipFamily == CHIP_FAMILY_RS740)) {
+ if (IS_R300_3D) {
/* clip has offset 1440 */
OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
(1088 << R300_CLIP_Y_SHIFT)));
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index d968dc8..9496bb6 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1036,10 +1036,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
CARD32 txenable, colorpitch;
CARD32 blendcntl;
int pixel_shift;
- int has_tcl = 0; /*((info->ChipFamily != CHIP_FAMILY_RS690) &&
- (info->ChipFamily != CHIP_FAMILY_RS740) &&
- (info->ChipFamily != CHIP_FAMILY_RS400) &&
- (info->ChipFamily != CHIP_FAMILY_RV515)); */
ACCEL_PREAMBLE();
TRACE;
@@ -1080,234 +1076,49 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
RADEON_SWITCH_TO_3D();
- /* setup the VAP */
- if (has_tcl) {
- BEGIN_ACCEL(9);
- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (4 << R300_PVS_NUM_FPUS_SHIFT) |
- (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
- } else {
- BEGIN_ACCEL(8);
- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
- OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (4 << R300_PVS_NUM_FPUS_SHIFT) |
- (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
- }
-
- OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
- OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
-
- if (has_tcl) {
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (1 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_SIGNED_1));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
- (0 << R300_SKIP_DWORDS_2_SHIFT) |
- (2 << R300_DST_VEC_LOC_2_SHIFT) |
- R300_LAST_VEC_2 |
- R300_SIGNED_2));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_1_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_2_SHIFT)));
- } else {
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (6 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_SIGNED_1));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
- (0 << R300_SKIP_DWORDS_2_SHIFT) |
- (7 << R300_DST_VEC_LOC_2_SHIFT) |
- R300_LAST_VEC_2 |
- R300_SIGNED_2));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_1_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_2_SHIFT)));
- }
- FINISH_ACCEL();
-
- /* setup the vertex shader */
- if (has_tcl) {
- if (pMask) {
- BEGIN_ACCEL(22);
- /* flush the PVS before updating??? */
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
-
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
- ((0 << R300_PVS_FIRST_INST_SHIFT) |
- (2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (2 << R300_PVS_LAST_INST_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
- (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
- } else {
- BEGIN_ACCEL(18);
- /* flush the PVS before updating??? */
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
-
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
- ((0 << R300_PVS_FIRST_INST_SHIFT) |
- (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (1 << R300_PVS_LAST_INST_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
- (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
- }
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
- /* PVS inst 0 */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(0) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- /* PVS inst 1 */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(1) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(1) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(1) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(1) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- if (pMask) {
- /* PVS inst 2 */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(2) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(2) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(2) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(2) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- }
-
- OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
-
- OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
- FINISH_ACCEL();
- }
+ BEGIN_ACCEL(8);
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (6 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_SIGNED_1));
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
+ (0 << R300_SKIP_DWORDS_2_SHIFT) |
+ (7 << R300_DST_VEC_LOC_2_SHIFT) |
+ R300_LAST_VEC_2 |
+ R300_SIGNED_2));
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_1_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_2_SHIFT)));
- BEGIN_ACCEL(4);
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
((2 << R300_TEX_0_COMP_CNT_SHIFT) |
(2 << R300_TEX_1_COMP_CNT_SHIFT)));
- OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
+ OUT_ACCEL_REG(R300_TX_INVALTAGS, 0);
OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
FINISH_ACCEL();
@@ -1394,9 +1205,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_OUT_FMT_C2_SEL_BLUE |
R300_OUT_FMT_C3_SEL_ALPHA);
break;
- case PICT_r5g6b5:
case PICT_a1r5g5b5:
case PICT_x1r5g5b5:
+ /* fix me */
+ case PICT_r5g6b5:
output_fmt = (R300_OUT_FMT_C_5_6_5 |
R300_OUT_FMT_C0_SEL_BLUE |
R300_OUT_FMT_C1_SEL_GREEN |
@@ -1567,103 +1379,80 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
CARD32 mask_color, mask_alpha;
if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
- //src_color = R300_ALU_RGB_0_0;
src_color = (R500_ALU_RGB_R_SWIZ_A_0 |
R500_ALU_RGB_G_SWIZ_A_0 |
R500_ALU_RGB_B_SWIZ_A_0);
else
- //src_color = R300_ALU_RGB_SRC0_RGB;
src_color = (R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B);
if (PICT_FORMAT_A(pSrcPicture->format) == 0)
- //src_alpha = R300_ALU_ALPHA_1_0;
src_alpha = R500_ALPHA_SWIZ_A_1;
else
- //src_alpha = R300_ALU_ALPHA_SRC0_A;
src_alpha = R500_ALPHA_SWIZ_A_A;
if (pMask && pMaskPicture->componentAlpha) {
if (RadeonBlendOp[op].src_alpha) {
if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
- //src_color = R300_ALU_RGB_1_0;
- //src_alpha = R300_ALU_ALPHA_1_0;
src_color = (R500_ALU_RGB_R_SWIZ_A_1 |
R500_ALU_RGB_G_SWIZ_A_1 |
R500_ALU_RGB_B_SWIZ_A_1);
src_alpha = R500_ALPHA_SWIZ_A_1;
} else {
- //src_color = R300_ALU_RGB_SRC0_AAA;
- //src_alpha = R300_ALU_ALPHA_SRC0_A;
src_color = (R500_ALU_RGB_R_SWIZ_A_A |
R500_ALU_RGB_G_SWIZ_A_A |
R500_ALU_RGB_B_SWIZ_A_A);
src_alpha = R500_ALPHA_SWIZ_A_A;
}
- //mask_color = R300_ALU_RGB_SRC1_RGB;
mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B);
if (PICT_FORMAT_A(pMaskPicture->format) == 0)
- //mask_alpha = R300_ALU_ALPHA_1_0;
mask_alpha = R500_ALPHA_SWIZ_B_1;
else
- //mask_alpha = R300_ALU_ALPHA_SRC1_A;
mask_alpha = R500_ALPHA_SWIZ_B_A;
} else {
- //src_color = R300_ALU_RGB_SRC0_RGB;
src_color = (R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B);
if (PICT_FORMAT_A(pSrcPicture->format) == 0)
- //src_alpha = R300_ALU_ALPHA_1_0;
src_alpha = R500_ALPHA_SWIZ_A_1;
else
- //src_alpha = R300_ALU_ALPHA_SRC0_A;
src_alpha = R500_ALPHA_SWIZ_A_A;
- //mask_color = R300_ALU_RGB_SRC1_RGB;
mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B);
if (PICT_FORMAT_A(pMaskPicture->format) == 0)
- //mask_alpha = R300_ALU_ALPHA_1_0;
mask_alpha = R500_ALPHA_SWIZ_B_1;
else
- //mask_alpha = R300_ALU_ALPHA_SRC1_A;
mask_alpha = R500_ALPHA_SWIZ_B_A;
}
} else if (pMask) {
if (PICT_FORMAT_A(pMaskPicture->format) == 0)
- //mask_color = R300_ALU_RGB_1_0;
mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_G_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1);
else
- //mask_color = R300_ALU_RGB_SRC1_AAA;
mask_color = (R500_ALU_RGB_R_SWIZ_B_A |
R500_ALU_RGB_G_SWIZ_B_A |
R500_ALU_RGB_B_SWIZ_B_A);
if (PICT_FORMAT_A(pMaskPicture->format) == 0)
- //mask_alpha = R300_ALU_ALPHA_1_0;
mask_alpha = R500_ALPHA_SWIZ_B_1;
else
- //mask_alpha = R300_ALU_ALPHA_SRC1_A;
mask_alpha = R500_ALPHA_SWIZ_B_A;
} else {
- //mask_color = R300_ALU_RGB_1_0;
mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_G_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1);
- //mask_alpha = R300_ALU_ALPHA_1_0;
mask_alpha = R500_ALPHA_SWIZ_B_1;
}
@@ -1686,9 +1475,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_OUT_FMT_C2_SEL_BLUE |
R300_OUT_FMT_C3_SEL_ALPHA);
break;
- case PICT_r5g6b5:
case PICT_a1r5g5b5:
case PICT_x1r5g5b5:
+ /* fix me */
+ case PICT_r5g6b5:
output_fmt = (R300_OUT_FMT_C_5_6_5 |
R300_OUT_FMT_C0_SEL_BLUE |
R300_OUT_FMT_C1_SEL_GREEN |
@@ -1746,7 +1536,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
/* src tex */
OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
@@ -1798,9 +1588,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_DY_S_SWIZ_R |
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ R500_DY_Q_SWIZ_R));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
@@ -1833,9 +1623,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_DY_S_SWIZ_R |
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ R500_DY_Q_SWIZ_R));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
} else {
BEGIN_ACCEL(13);
OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
@@ -1870,9 +1660,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_DY_S_SWIZ_R |
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ R500_DY_Q_SWIZ_R));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
}
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
@@ -1916,14 +1706,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
FINISH_ACCEL();
}
- BEGIN_ACCEL(4);
+ BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
- OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
FINISH_ACCEL();
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 2681d3f..45dc0c9 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -106,15 +106,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
dstyoff = 0;
#endif
-#if 0
- ErrorF("dst_offset: 0x%x\n", dst_offset);
- ErrorF("dst_pitch: 0x%x\n", dst_pitch);
- ErrorF("dstxoff: 0x%x\n", dstxoff);
- ErrorF("dstyoff: 0x%x\n", dstyoff);
- ErrorF("src_offset: 0x%x\n", pPriv->src_offset);
- ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch);
-#endif
-
if (!info->XInited3D)
RADEONInit3DEngine(pScrn);
@@ -126,11 +117,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
FINISH_VIDEO();
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- int has_tcl = 0; /*((info->ChipFamily != CHIP_FAMILY_RS690) &&
- (info->ChipFamily != CHIP_FAMILY_RS740) &&
- (info->ChipFamily != CHIP_FAMILY_RS400) &&
- (info->ChipFamily != CHIP_FAMILY_RV515));*/
+ if (IS_R300_3D || IS_R500_3D) {
switch (pPixmap->drawable.bitsPerPixel) {
case 16:
@@ -194,154 +181,36 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txenable = R300_TEX_0_ENABLE;
- /* setup the VAP */
- if (has_tcl) {
- BEGIN_VIDEO(26);
- OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0);
- OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- OUT_VIDEO_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (4 << R300_PVS_NUM_FPUS_SHIFT) |
- (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
- } else {
- BEGIN_VIDEO(8);
- OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
- OUT_VIDEO_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (4 << R300_PVS_NUM_FPUS_SHIFT) |
- (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
- }
-
- OUT_VIDEO_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
- OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
-
- if (has_tcl) {
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (10 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_LAST_VEC_1 |
- R300_SIGNED_1));
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_1_SHIFT)));
- } else {
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (6 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_LAST_VEC_1 |
- R300_SIGNED_1));
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
- << R300_WRITE_ENA_1_SHIFT)));
- }
-
- /* setup vertex shader */
- if (has_tcl) {
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
- ((0 << R300_PVS_FIRST_INST_SHIFT) |
- (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (1 << R300_PVS_LAST_INST_SHIFT)));
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
- (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
-
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(0) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(0) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_DST_OPCODE(R300_VE_ADD) |
- R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
- R300_PVS_DST_OFFSET(1) |
- R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
- R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(10) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(10) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
- (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(10) |
- R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
- R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
- OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
-
- OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
- OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
- OUT_VIDEO_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
- OUT_VIDEO_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
- OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
- }
+ BEGIN_VIDEO(6);
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (6 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_LAST_VEC_1 |
+ R300_SIGNED_1));
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ << R300_WRITE_ENA_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ << R300_WRITE_ENA_1_SHIFT)));
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
+
+ OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
+ OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
FINISH_VIDEO();
/* setup pixel shader */
@@ -358,7 +227,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_RS_SEL_T(R300_RS_SEL_C1) |
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
+ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
OUT_VIDEO_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
OUT_VIDEO_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
@@ -445,8 +314,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
- OUT_VIDEO_REG(R300_RS_INST_COUNT, 0);
- OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
+ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+
+ OUT_VIDEO_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
+ R500_RS_INST_TEX_CN_WRITE |
+ (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
OUT_VIDEO_REG(R500_US_FC_CTRL, 0);
@@ -456,7 +328,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_US_CODE_RANGE_SIZE(1)));
OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
- // 7807
+
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -488,11 +360,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_DY_S_SWIZ_R |
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ R500_DY_Q_SWIZ_R));
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- // 0x78105
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
@@ -508,13 +379,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_RGB_ADDR1_CONST |
R500_RGB_ADDR2(0) |
R500_RGB_ADDR2_CONST |
- R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000
+ R500_RGB_SRCP_OP_1_MINUS_2RGB0));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR1_CONST |
R500_ALPHA_ADDR2(0) |
R500_ALPHA_ADDR2_CONST |
- R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000
+ R500_ALPHA_SRCP_OP_1_MINUS_2A0));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
@@ -523,33 +394,28 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC0 |
R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1 |
- R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220
+ R500_ALU_RGB_G_SWIZ_B_1));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SWIZ_B_1));//0x00c0c000)
+ R500_ALPHA_SWIZ_B_1));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));//0x20490000
+ R500_ALU_RGBA_A_SWIZ_0));
FINISH_VIDEO();
}
- BEGIN_VIDEO(6);
- OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
- OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
+ BEGIN_VIDEO(4);
OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset);
OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch);
blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
- OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl);
- OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0);
- FINISH_VIDEO();
+ OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
- BEGIN_VIDEO(1);
OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT);
FINISH_VIDEO();
@@ -722,7 +588,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
} else {
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
+ if (IS_R300_3D || IS_R500_3D)
BEGIN_RING(4 * VTX_DWORD_COUNT + 6);
else
BEGIN_RING(4 * VTX_DWORD_COUNT + 2);
@@ -733,7 +599,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
}
#else /* ACCEL_CP */
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
+ if (IS_R300_3D || IS_R500_3D)
BEGIN_VIDEO(3 + VTX_DWORD_COUNT * 4);
else
BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4);
@@ -759,7 +625,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
VTX_OUT((float)(dstX + dstw), (float)dstY,
xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]);
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
+ if (IS_R300_3D || IS_R500_3D) {
OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
}
commit 399b1d405e602c62d6deebea6d7e1f38886cd8e2
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 24 13:04:57 2008 -0400
R3xx/R5xx: use non VAP/TCP for textured video
Just extra state to emit.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index d4a3343..2681d3f 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -127,10 +127,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_VIDEO();
if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) &&
+ int has_tcl = 0; /*((info->ChipFamily != CHIP_FAMILY_RS690) &&
(info->ChipFamily != CHIP_FAMILY_RS740) &&
(info->ChipFamily != CHIP_FAMILY_RS400) &&
- (info->ChipFamily != CHIP_FAMILY_RV515));
+ (info->ChipFamily != CHIP_FAMILY_RV515));*/
switch (pPixmap->drawable.bitsPerPixel) {
case 16:
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