xf86-video-ati: Branch 'master' - 33 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Wed Mar 19 13:15:17 PDT 2008
src/radeon.h | 19
src/radeon_exa_funcs.c | 4
src/radeon_exa_render.c | 1097 +++++++++++++++++++++++++++------------
src/radeon_reg.h | 187 +++++-
src/radeon_textured_video.c | 23
src/radeon_textured_videofuncs.c | 97 ++-
6 files changed, 1067 insertions(+), 360 deletions(-)
New commits:
commit bed9754ad21d6c0a7f61067b04ba31c430a7cecb
Merge: 55e446b... f71ac0e...
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 16:06:41 2008 -0400
Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into r3xx-render
commit 55e446b5bc091e6c7b3c2e9ae20b45130555c246
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 13:15:32 2008 -0400
R3xx/R5xx: Make sure to clamp the output of the FS
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index c881a28..707e9fc 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1540,7 +1540,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
- R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
+ R300_ALU_RGB_CLAMP));
OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
(R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(1) |
@@ -1557,7 +1558,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
- R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE)));
+ R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
+ R300_ALU_ALPHA_CLAMP));
FINISH_ACCEL();
} else {
CARD32 output_fmt;
@@ -1771,7 +1773,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
@@ -1803,7 +1807,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
R500_TEX_INST_LD |
@@ -1838,7 +1844,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
@@ -1873,7 +1881,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_INST_RGB_OMASK_R |
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
- R500_INST_ALPHA_OMASK));
+ R500_INST_ALPHA_OMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR1(1) |
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 6a2b8e1..7702591 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -414,7 +414,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
- R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
+ R300_ALU_RGB_CLAMP));
OUT_VIDEO_REG(R300_US_ALU_ALPHA_ADDR_0,
(R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(0) |
@@ -432,7 +433,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
- R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE)));
+ R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
+ R300_ALU_ALPHA_CLAMP));
FINISH_VIDEO();
} else {
BEGIN_VIDEO(23);
@@ -461,7 +463,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
@@ -496,7 +500,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_OMASK_R |
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
- R500_INST_ALPHA_OMASK));
+ R500_INST_ALPHA_OMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR1(0) |
commit b6aa4279cbe68cc8e4523795e9714fb798b62d98
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 12:45:01 2008 -0400
R5xx: bump textured video limits to 4096
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index f2f38c3..c881a28 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -345,7 +345,7 @@ RADEONGetDrawablePixmap(DrawablePtr pDrawable)
return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable);
else
return (PixmapPtr)pDrawable;
-}
+}
static Bool R100CheckComposite(int op, PicturePtr pSrcPicture,
PicturePtr pMaskPicture, PicturePtr pDstPicture)
@@ -435,7 +435,7 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
RADEONInit3DEngine(pScrn);
if (!RADEONGetDestFormat(pDstPicture, &dst_format))
- return FALSE;
+ return FALSE;
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 05dd20e..0a6598d 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -46,6 +46,9 @@
#define IMAGE_MAX_WIDTH 2048
#define IMAGE_MAX_HEIGHT 2048
+#define IMAGE_MAX_WIDTH_R500 4096
+#define IMAGE_MAX_HEIGHT_R500 4096
+
static Bool
RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
{
@@ -300,6 +303,16 @@ static XF86VideoEncodingRec DummyEncoding[1] =
}
};
+static XF86VideoEncodingRec DummyEncodingR500[1] =
+{
+ {
+ 0,
+ "XV_IMAGE",
+ IMAGE_MAX_WIDTH_R500, IMAGE_MAX_HEIGHT_R500,
+ {1, 1}
+ }
+};
+
#define NUM_FORMATS 3
static XF86VideoFormatRec Formats[NUM_FORMATS] =
@@ -326,6 +339,8 @@ static XF86ImageRec Images[NUM_IMAGES] =
XF86VideoAdaptorPtr
RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
{
+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONPortPrivPtr pPortPriv;
XF86VideoAdaptorPtr adapt;
int i;
@@ -340,7 +355,10 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
adapt->flags = 0;
adapt->name = "Radeon Textured Video";
adapt->nEncodings = 1;
- adapt->pEncodings = DummyEncoding;
+ if (IS_R500_3D)
+ adapt->pEncodings = DummyEncodingR500;
+ else
+ adapt->pEncodings = DummyEncoding;
adapt->nFormats = NUM_FORMATS;
adapt->pFormats = Formats;
adapt->nPorts = num_texture_ports;
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 8302509..6a2b8e1 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -160,8 +160,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP;
- txformat0 = (((pPriv->w - 1) << R300_TXWIDTH_SHIFT) |
- ((pPriv->h - 1) << R300_TXHEIGHT_SHIFT));
+ txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
+ (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
txformat0 |= R300_TXPITCH_EN;
@@ -176,6 +176,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txpitch = pPriv->src_pitch / 2;
txpitch -= 1;
+ if (IS_R500_3D && ((pPriv->w - 1) & 0x800))
+ txpitch |= R500_TXWIDTH_11;
+
+ if (IS_R500_3D && ((pPriv->h - 1) & 0x800))
+ txpitch |= R500_TXHEIGHT_11;
+
txoffset = pPriv->src_offset;
BEGIN_VIDEO(6);
commit 4a445a3e8c4c5ecd9d4ef8daa26906c3ceaa94a1
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 12:31:51 2008 -0400
RADEON: add new macros to distinguish between R3xx and R5xx 3D
diff --git a/src/radeon.h b/src/radeon.h
index a67f375..8ebb3b3 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -271,7 +271,7 @@ typedef enum {
CHIP_FAMILY_RV570, /* rv570 */
CHIP_FAMILY_RS690,
CHIP_FAMILY_RS740,
- CHIP_FAMILY_R600, /* r60 */
+ CHIP_FAMILY_R600, /* r600 */
CHIP_FAMILY_R630,
CHIP_FAMILY_RV610,
CHIP_FAMILY_RV630,
@@ -303,6 +303,23 @@ typedef enum {
#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620))
+#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \
+ (info->ChipFamily == CHIP_FAMILY_R520) || \
+ (info->ChipFamily == CHIP_FAMILY_RV530) || \
+ (info->ChipFamily == CHIP_FAMILY_R580) || \
+ (info->ChipFamily == CHIP_FAMILY_RV560) || \
+ (info->ChipFamily == CHIP_FAMILY_RV570))
+
+#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \
+ (info->ChipFamily == CHIP_FAMILY_RV350) || \
+ (info->ChipFamily == CHIP_FAMILY_R350) || \
+ (info->ChipFamily == CHIP_FAMILY_RV380) || \
+ (info->ChipFamily == CHIP_FAMILY_R420) || \
+ (info->ChipFamily == CHIP_FAMILY_RV410) || \
+ (info->ChipFamily == CHIP_FAMILY_RS690) || \
+ (info->ChipFamily == CHIP_FAMILY_RS740) || \
+ (info->ChipFamily == CHIP_FAMILY_RS400))
+
/*
* Errata workarounds
*/
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 84beec3..d5ee5a6 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -536,9 +536,9 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
if (info->ChipFamily >= CHIP_FAMILY_R600)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
"unsupported on R600 and newer cards.\n");
- else if (IS_R300_VARIANT || (IS_AVIVO_VARIANT && info->ChipFamily <= CHIP_FAMILY_RS740)) {
+ else if (IS_R300_3D || IS_R500_3D) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
- "enabled for R300 type cards.\n");
+ "enabled for R300/R400/R500 type cards.\n");
info->exa->CheckComposite = R300CheckComposite;
info->exa->PrepareComposite =
FUNC_NAME(R300PrepareComposite);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index c3ad7a5..f2f38c3 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -888,10 +888,10 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
(((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
- if (IS_AVIVO_VARIANT && ((w - 1) & 0x800))
+ if (IS_R500_3D && ((w - 1) & 0x800))
txpitch |= R500_TXWIDTH_11;
- if (IS_AVIVO_VARIANT && ((h - 1) & 0x800))
+ if (IS_R500_3D && ((h - 1) & 0x800))
txpitch |= R500_TXHEIGHT_11;
if (pPict->repeat) {
@@ -952,7 +952,6 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
int max_tex_w, max_tex_h, max_dst_w, max_dst_h;
- Bool is_r500;
TRACE;
@@ -962,10 +961,7 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable);
- is_r500 = ((info->ChipFamily >= CHIP_FAMILY_RV515) &&
- (info->ChipFamily <= CHIP_FAMILY_RV570));
-
- if (is_r500) {
+ if (IS_R500_3D) {
max_tex_w = 4096;
max_tex_h = 4096;
max_dst_w = 4096;
@@ -1016,11 +1012,11 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
}
}
- if (!R300CheckCompositeTexture(pMaskPicture, 1, is_r500))
+ if (!R300CheckCompositeTexture(pMaskPicture, 1, IS_R500_3D))
return FALSE;
}
- if (!R300CheckCompositeTexture(pSrcPicture, 0, is_r500))
+ if (!R300CheckCompositeTexture(pSrcPicture, 0, IS_R500_3D))
return FALSE;
if (!R300GetDestFormat(pDstPicture, &tmp1))
@@ -1316,9 +1312,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
FINISH_ACCEL();
/* setup pixel shader */
- if (IS_R300_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_RS690) ||
- (info->ChipFamily == CHIP_FAMILY_RS740)) {
+ if (IS_R300_3D) {
CARD32 output_fmt;
int src_color, src_alpha;
int mask_color, mask_alpha;
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 647fa80..8302509 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -340,9 +340,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_VIDEO();
/* setup pixel shader */
- if (IS_R300_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_RS690) ||
- (info->ChipFamily == CHIP_FAMILY_RS740)) {
+ if (IS_R300_3D) {
BEGIN_VIDEO(16);
OUT_VIDEO_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
commit 85d0c9e8d22ccc72bec87b3fd44da5d7609293e0
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 12:07:33 2008 -0400
RADEON: fixed textured video with XAA and tiling
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 6072c0e..05dd20e 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -60,6 +60,9 @@ RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
} else
#endif
{
+ if (info->tilingEnabled && ((pPix->devPrivate.ptr - info->FB) == 0))
+ return TRUE;
+ else
return FALSE;
}
}
commit f5951db7b3522e0fe6af7f46a170c9c9a60a9bff
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 12:01:50 2008 -0400
RV515: fix textured video and EXA Composite
There seems to be an issue with the PVS setup on RV515, but
bypassing it seems to work fine.
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 66652ce..c3ad7a5 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1042,7 +1042,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
int pixel_shift;
int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) &&
(info->ChipFamily != CHIP_FAMILY_RS740) &&
- (info->ChipFamily != CHIP_FAMILY_RS400));
+ (info->ChipFamily != CHIP_FAMILY_RS400) &&
+ (info->ChipFamily != CHIP_FAMILY_RV515));
ACCEL_PREAMBLE();
TRACE;
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 2d5819a..647fa80 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -130,7 +130,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) &&
(info->ChipFamily != CHIP_FAMILY_RS740) &&
- (info->ChipFamily != CHIP_FAMILY_RS400));
+ (info->ChipFamily != CHIP_FAMILY_RS400) &&
+ (info->ChipFamily != CHIP_FAMILY_RV515));
switch (pPixmap->drawable.bitsPerPixel) {
case 16:
commit 13573879fe56368ad06234712b677c23fabc56c6
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Mar 19 15:06:47 2008 +1000
r500: make it work from startup.
I'm not sure why this worked or what is going wrong here, really the
VAP internal architecture escapes me :)
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 5f28fef..66652ce 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1125,20 +1125,20 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_0_SHIFT) |
(R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_1_SHIFT)));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_2_SHIFT)));
} else {
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
@@ -1161,20 +1161,20 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_0_SHIFT) |
(R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_1_SHIFT)));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_2_SHIFT)));
}
FINISH_ACCEL();
commit d331dd64d644a18ec99a2136cd0943b5edca1f03
Author: Alex Deucher <alex at samba.(none)>
Date: Tue Mar 18 19:44:26 2008 -0400
R3xx/R5xx: remove extra return after last commit
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 6592438..5f28fef 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -179,7 +179,6 @@ static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format)
default:
RADEON_FALLBACK(("Unsupported dest format 0x%x\n",
(int)pDstPicture->format));
- return FALSE;
}
return TRUE;
}
commit bc34df7a9c35cdd38c49d5c22471f3f487a33d6e
Author: Alex Deucher <alex at samba.(none)>
Date: Tue Mar 18 19:39:47 2008 -0400
R3xx/R5xx: switch an ErrorF() to RADEONFALLBACK()
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 0c94a23..6592438 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -177,8 +177,8 @@ static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format)
*dst_format = R300_COLORFORMAT_I8;
break;
default:
- ErrorF("Unsupported dest format 0x%x\n",
- (int)pDstPicture->format);
+ RADEON_FALLBACK(("Unsupported dest format 0x%x\n",
+ (int)pDstPicture->format));
return FALSE;
}
return TRUE;
commit 6f03f8fe0ecf4181dcf125049cf63bece0451fb2
Author: Alex Deucher <alex at samba.(none)>
Date: Tue Mar 18 19:36:05 2008 -0400
R3xx: we only use 2 temps, not 3
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 34f26de..0c94a23 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1448,7 +1448,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_INST_TEX_ADDR(1)));
OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* max num of temps used */
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* max num of temps used */
OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(0) |
R300_TEX_CODE_OFFSET(0) |
commit 8bb71ab4a3eb4fb6ef7f709e87c8df387cb70ee3
Author: Tilman Sauerbeck <tilman at code-monkey.de>
Date: Tue Mar 18 14:36:08 2008 -0400
R3xx/R5xx: fix up a8-src-something_with_colors
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 9718359..34f26de 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1324,7 +1324,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
int mask_color, mask_alpha;
if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
- src_color = R300_ALU_RGB_1_0;
+ src_color = R300_ALU_RGB_0_0;
else
src_color = R300_ALU_RGB_SRC0_RGB;
@@ -1571,10 +1571,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
CARD32 mask_color, mask_alpha;
if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
- //src_color = R300_ALU_RGB_1_0;
- src_color = (R500_ALU_RGB_R_SWIZ_A_1 |
- R500_ALU_RGB_G_SWIZ_A_1 |
- R500_ALU_RGB_B_SWIZ_A_1);
+ //src_color = R300_ALU_RGB_0_0;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_0 |
+ R500_ALU_RGB_G_SWIZ_A_0 |
+ R500_ALU_RGB_B_SWIZ_A_0);
else
//src_color = R300_ALU_RGB_SRC0_RGB;
src_color = (R500_ALU_RGB_R_SWIZ_A_R |
commit c362591d9b496df30668543158e4de44de742dc3
Author: Alex Deucher <alex at samba.(none)>
Date: Tue Mar 18 11:15:17 2008 -0400
R3xx/R5xx: remove some cruft
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index dd07084..9718359 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -952,8 +952,6 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
PixmapPtr pSrcPixmap, pDstPixmap;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int i;
int max_tex_w, max_tex_h, max_dst_w, max_dst_h;
Bool is_r500;
@@ -963,33 +961,6 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
-#if 0
- /* Throw out cases that aren't going to be our rotation first */
- if (pMaskPicture != NULL || op != PictOpSrc || pSrcPicture->pDrawable == NULL)
- RADEON_FALLBACK(("Junk driver\n"));
-
- if (pSrcPicture->pDrawable->type != DRAWABLE_WINDOW ||
- pDstPicture->pDrawable->type != DRAWABLE_PIXMAP) {
- RADEON_FALLBACK(("bad drawable\n"));
- }
-
- pSrcPixmap = (*pScreen->GetWindowPixmap) ((WindowPtr) pSrcPicture->pDrawable);
- pDstPixmap = (PixmapPtr)pDstPicture->pDrawable;
-
- /* Check if the dest is one of our shadow pixmaps */
- for (i = 0; i < xf86_config->num_crtc; i++) {
- xf86CrtcPtr crtc = xf86_config->crtc[i];
-
- if (crtc->rotatedPixmap == pDstPixmap)
- break;
- }
- if (i == xf86_config->num_crtc)
- RADEON_FALLBACK(("no rotated pixmap\n"));
-
- if (pSrcPixmap != pScreen->GetScreenPixmap(pScreen))
- RADEON_FALLBACK(("src not screen\n"));
-#endif
-
pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable);
is_r500 = ((info->ChipFamily >= CHIP_FAMILY_RV515) &&
commit 89fe6d2c7d7471e6088558130f6e49f46c31dd47
Author: Dave Airlie <airlied at linux.ie>
Date: Tue Mar 18 09:43:43 2008 -0400
R5xx: fix typ in r5xx render accel
This gets render working on r5xx
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index a1cab9a..dd07084 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1848,7 +1848,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_ADDR(1) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
commit 79b40ebcd8dedfc83e484c1024beeeaccc6124f3
Author: Alex Deucher <alex at samba.(none)>
Date: Tue Mar 18 02:46:49 2008 -0400
R5xx: first pass at render support (untested)
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 7d15264..a1cab9a 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1595,61 +1595,313 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE)));
FINISH_ACCEL();
} else {
- BEGIN_ACCEL(23);
- OUT_ACCEL_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
- (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
- (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
- (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
-
- OUT_ACCEL_REG(R300_RS_INST_COUNT, 0);
- OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
- OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
- OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
- OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(1)));
- OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(1)));
- OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
- // 7807
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
- R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
- R500_TEX_IGNORE_UNCOVERED));
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_DST_ADDR(0) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
- R500_DX_S_SWIZ_R |
- R500_DX_T_SWIZ_R |
- R500_DX_R_SWIZ_R |
- R500_DX_Q_SWIZ_R |
- R500_DY_ADDR(0) |
- R500_DY_S_SWIZ_R |
- R500_DY_T_SWIZ_R |
- R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
-
- // 0x78105
+ CARD32 output_fmt;
+ CARD32 src_color, src_alpha;
+ CARD32 mask_color, mask_alpha;
+
+ if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
+ //src_color = R300_ALU_RGB_1_0;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1);
+ else
+ //src_color = R300_ALU_RGB_SRC0_RGB;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B);
+
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ //src_alpha = R300_ALU_ALPHA_1_0;
+ src_alpha = R500_ALPHA_SWIZ_A_1;
+ else
+ //src_alpha = R300_ALU_ALPHA_SRC0_A;
+ src_alpha = R500_ALPHA_SWIZ_A_A;
+
+ if (pMask && pMaskPicture->componentAlpha) {
+ if (RadeonBlendOp[op].src_alpha) {
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
+ //src_color = R300_ALU_RGB_1_0;
+ //src_alpha = R300_ALU_ALPHA_1_0;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1);
+ src_alpha = R500_ALPHA_SWIZ_A_1;
+ } else {
+ //src_color = R300_ALU_RGB_SRC0_AAA;
+ //src_alpha = R300_ALU_ALPHA_SRC0_A;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_A |
+ R500_ALU_RGB_G_SWIZ_A_A |
+ R500_ALU_RGB_B_SWIZ_A_A);
+ src_alpha = R500_ALPHA_SWIZ_A_A;
+ }
+
+ //mask_color = R300_ALU_RGB_SRC1_RGB;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B);
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_alpha = R300_ALU_ALPHA_1_0;
+ mask_alpha = R500_ALPHA_SWIZ_B_1;
+ else
+ //mask_alpha = R300_ALU_ALPHA_SRC1_A;
+ mask_alpha = R500_ALPHA_SWIZ_B_A;
+
+ } else {
+ //src_color = R300_ALU_RGB_SRC0_RGB;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B);
+
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ //src_alpha = R300_ALU_ALPHA_1_0;
+ src_alpha = R500_ALPHA_SWIZ_A_1;
+ else
+ //src_alpha = R300_ALU_ALPHA_SRC0_A;
+ src_alpha = R500_ALPHA_SWIZ_A_A;
+
+ //mask_color = R300_ALU_RGB_SRC1_RGB;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B);
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_alpha = R300_ALU_ALPHA_1_0;
+ mask_alpha = R500_ALPHA_SWIZ_B_1;
+ else
+ //mask_alpha = R300_ALU_ALPHA_SRC1_A;
+ mask_alpha = R500_ALPHA_SWIZ_B_A;
+
+ }
+ } else if (pMask) {
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_color = R300_ALU_RGB_1_0;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
+ R500_ALU_RGB_G_SWIZ_B_1 |
+ R500_ALU_RGB_B_SWIZ_B_1);
+ else
+ //mask_color = R300_ALU_RGB_SRC1_AAA;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_A |
+ R500_ALU_RGB_G_SWIZ_B_A |
+ R500_ALU_RGB_B_SWIZ_B_A);
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_alpha = R300_ALU_ALPHA_1_0;
+ mask_alpha = R500_ALPHA_SWIZ_B_1;
+ else
+ //mask_alpha = R300_ALU_ALPHA_SRC1_A;
+ mask_alpha = R500_ALPHA_SWIZ_B_A;
+ } else {
+ //mask_color = R300_ALU_RGB_1_0;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
+ R500_ALU_RGB_G_SWIZ_B_1 |
+ R500_ALU_RGB_B_SWIZ_B_1);
+ //mask_alpha = R300_ALU_ALPHA_1_0;
+ mask_alpha = R500_ALPHA_SWIZ_B_1;
+ }
+
+ /* shader output swizzling */
+ switch (pDstPicture->format) {
+ case PICT_a8r8g8b8:
+ case PICT_x8r8g8b8:
+ default:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_a8b8g8r8:
+ case PICT_x8b8g8r8:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_RED |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_BLUE |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_r5g6b5:
+ case PICT_a1r5g5b5:
+ case PICT_x1r5g5b5:
+ output_fmt = (R300_OUT_FMT_C_5_6_5 |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_a8:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_ALPHA);
+ break;
+ }
+
+ if (pMask) {
+ BEGIN_ACCEL(13);
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+ OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+
+ OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+
+ /* src tex */
+ OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
+ R500_RS_INST_TEX_CN_WRITE |
+ (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
+ /* mask tex */
+ OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
+ R500_RS_INST_TEX_CN_WRITE |
+ (1 << R500_RS_INST_TEX_ADDR_SHIFT)));
+
+ OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1);
+ OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
+ OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ R500_US_CODE_END_ADDR(2)));
+ OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ R500_US_CODE_RANGE_SIZE(2)));
+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
+ } else {
+ BEGIN_ACCEL(11);
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+
+ OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+
+ /* src tex */
+ OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
+ R500_RS_INST_TEX_CN_WRITE |
+ (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
+
+ OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1);
+ OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
+ OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ R500_US_CODE_END_ADDR(1)));
+ OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ R500_US_CODE_RANGE_SIZE(1)));
+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
+ }
+
+ OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
+ FINISH_ACCEL();
+
+ if (pMask) {
+ BEGIN_ACCEL(19);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ R500_TEX_INST_LD |
+ R500_TEX_IGNORE_UNCOVERED));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ R500_DX_S_SWIZ_R |
+ R500_DX_T_SWIZ_R |
+ R500_DX_R_SWIZ_R |
+ R500_DX_Q_SWIZ_R |
+ R500_DY_ADDR(0) |
+ R500_DY_S_SWIZ_R |
+ R500_DY_T_SWIZ_R |
+ R500_DY_R_SWIZ_R |
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(1) |
+ R500_DX_S_SWIZ_R |
+ R500_DX_T_SWIZ_R |
+ R500_DX_R_SWIZ_R |
+ R500_DX_Q_SWIZ_R |
+ R500_DY_ADDR(1) |
+ R500_DY_S_SWIZ_R |
+ R500_DY_T_SWIZ_R |
+ R500_DY_R_SWIZ_R |
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ } else {
+ BEGIN_ACCEL(13);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ R500_DX_S_SWIZ_R |
+ R500_DX_T_SWIZ_R |
+ R500_DX_R_SWIZ_R |
+ R500_DX_Q_SWIZ_R |
+ R500_DY_ADDR(0) |
+ R500_DY_S_SWIZ_R |
+ R500_DY_T_SWIZ_R |
+ R500_DY_R_SWIZ_R |
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ }
+
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
@@ -1659,36 +1911,33 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_INST_ALPHA_OMASK));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR1(0) |
- R500_RGB_ADDR1_CONST |
- R500_RGB_ADDR2(0) |
- R500_RGB_ADDR2_CONST |
- R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000
+ R500_RGB_ADDR1(1) |
+ R500_RGB_ADDR2(0)));
+
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR1(0) |
- R500_ALPHA_ADDR1_CONST |
- R500_ALPHA_ADDR2(0) |
- R500_ALPHA_ADDR2_CONST |
- R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000
+ R500_ALPHA_ADDR1(1) |
+ R500_ALPHA_ADDR2(0)));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC0 |
- R500_ALU_RGB_R_SWIZ_B_1 |
- R500_ALU_RGB_B_SWIZ_B_1 |
- R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220
+ src_color |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ mask_color |
+ R500_ALU_RGB_TARGET(0)));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SWIZ_B_1));//0x00c0c000)
+ R500_ALPHA_ADDRD(0) |
+ R500_ALPHA_SEL_A_SRC0 |
+ src_alpha |
+ R500_ALPHA_SEL_B_SRC1 |
+ mask_alpha |
+ R500_ALPHA_TARGET(0)));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));//0x20490000
+ R500_ALU_RGBA_A_SWIZ_0));
FINISH_ACCEL();
}
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index b19b5ca..6245403 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -5095,17 +5095,18 @@
#define R500_GA_US_VECTOR_DATA 0x4254
#define R500_RS_INST_0 0x4320
-#define R500_RS_INST_TEX_ID_SHIFT 0
-#define R500_RS_INST_TEX_CN_WRITE (1 << 4)
-#define R500_RS_INST_TEX_ADDR_SHIFT 5
-#define R500_RS_INST_COL_ID_SHIFT 12
-#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
-#define R500_RS_INST_COL_CN_WRITE (1 << 16)
-#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
-#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
-#define R500_RS_INST_COL_COL_ADDR_SHIFT 18
-#define R500_RS_INST_TEX_ADJ (1 << 25)
-#define R500_RS_INST_W_CN (1 << 26)
+#define R500_RS_INST_1 0x4324
+# define R500_RS_INST_TEX_ID_SHIFT 0
+# define R500_RS_INST_TEX_CN_WRITE (1 << 4)
+# define R500_RS_INST_TEX_ADDR_SHIFT 5
+# define R500_RS_INST_COL_ID_SHIFT 12
+# define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
+# define R500_RS_INST_COL_CN_WRITE (1 << 16)
+# define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
+# define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
+# define R500_RS_INST_COL_COL_ADDR_SHIFT 18
+# define R500_RS_INST_TEX_ADJ (1 << 25)
+# define R500_RS_INST_W_CN (1 << 26)
#define R500_US_FC_CTRL 0x4624
#define R500_US_CODE_ADDR 0x4630
@@ -5113,16 +5114,17 @@
#define R500_US_CODE_OFFSET 0x4638
#define R500_RS_IP_0 0x4074
-#define R500_RS_IP_PTR_K0 62
-#define R500_RS_IP_PTR_K1 63
-#define R500_RS_IP_TEX_PTR_S_SHIFT 0
-#define R500_RS_IP_TEX_PTR_T_SHIFT 6
-#define R500_RS_IP_TEX_PTR_R_SHIFT 12
-#define R500_RS_IP_TEX_PTR_Q_SHIFT 18
-#define R500_RS_IP_COL_PTR_SHIFT 24
-#define R500_RS_IP_COL_FMT_SHIFT 27
-#define R500_RS_IP_COL_FMT_RGBA (0<<27)
-#define R500_RS_IP_OFFSET_EN (1 << 31)
+#define R500_RS_IP_1 0x4078
+# define R500_RS_IP_PTR_K0 62
+# define R500_RS_IP_PTR_K1 63
+# define R500_RS_IP_TEX_PTR_S_SHIFT 0
+# define R500_RS_IP_TEX_PTR_T_SHIFT 6
+# define R500_RS_IP_TEX_PTR_R_SHIFT 12
+# define R500_RS_IP_TEX_PTR_Q_SHIFT 18
+# define R500_RS_IP_COL_PTR_SHIFT 24
+# define R500_RS_IP_COL_FMT_SHIFT 27
+# define R500_RS_IP_COL_FMT_RGBA (0 << 27)
+# define R500_RS_IP_OFFSET_EN (1 << 31)
#endif
commit 71292c8f193230255d1d980c2e996bb01d04fab6
Author: Alex Deucher <alex at samba.(none)>
Date: Tue Mar 18 00:45:37 2008 -0400
R5xx: bump tex/dst limits to 4096
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 624269d..7d15264 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -812,13 +812,22 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
#ifdef ONLY_ONCE
-static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit)
+static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit, Bool is_r500)
{
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i;
+ int max_tex_w, max_tex_h;
- if ((w > 0x7ff) || (h > 0x7ff))
+ if (is_r500) {
+ max_tex_w = 4096;
+ max_tex_h = 4096;
+ } else {
+ max_tex_w = 2048;
+ max_tex_h = 2048;
+ }
+
+ if ((w > max_tex_w) || (h > max_tex_h))
RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h));
for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++)
@@ -877,11 +886,16 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txformat1 = R300TexFormats[i].card_fmt;
- txformat0 = (((w - 1) << R300_TXWIDTH_SHIFT) |
- ((h - 1) << R300_TXHEIGHT_SHIFT));
+ txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
+ (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
+
+ if (IS_AVIVO_VARIANT && ((w - 1) & 0x800))
+ txpitch |= R500_TXWIDTH_11;
+
+ if (IS_AVIVO_VARIANT && ((h - 1) & 0x800))
+ txpitch |= R500_TXHEIGHT_11;
if (pPict->repeat) {
- ErrorF("repeat\n");
if ((h != 1) &&
(((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
@@ -937,8 +951,11 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
ScreenPtr pScreen = pDstPicture->pDrawable->pScreen;
PixmapPtr pSrcPixmap, pDstPixmap;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int i;
+ int max_tex_w, max_tex_h, max_dst_w, max_dst_h;
+ Bool is_r500;
TRACE;
@@ -975,10 +992,23 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable);
- /* XXX: R(V)5xx may have higher limits
- */
- if (pSrcPixmap->drawable.width >= 2048 ||
- pSrcPixmap->drawable.height >= 2048) {
+ is_r500 = ((info->ChipFamily >= CHIP_FAMILY_RV515) &&
+ (info->ChipFamily <= CHIP_FAMILY_RV570));
+
+ if (is_r500) {
+ max_tex_w = 4096;
+ max_tex_h = 4096;
+ max_dst_w = 4096;
+ max_dst_h = 4096;
+ } else {
+ max_tex_w = 2048;
+ max_tex_h = 2048;
+ max_dst_w = 2560;
+ max_dst_h = 2560;
+ }
+
+ if (pSrcPixmap->drawable.width >= max_tex_w ||
+ pSrcPixmap->drawable.height >= max_tex_h) {
RADEON_FALLBACK(("Source w/h too large (%d,%d).\n",
pSrcPixmap->drawable.width,
pSrcPixmap->drawable.height));
@@ -986,8 +1016,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable);
- if (pDstPixmap->drawable.width >= 2560 ||
- pDstPixmap->drawable.height >= 2560) {
+ if (pDstPixmap->drawable.width >= max_dst_w ||
+ pDstPixmap->drawable.height >= max_dst_h) {
RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n",
pDstPixmap->drawable.width,
pDstPixmap->drawable.height));
@@ -996,8 +1026,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
if (pMaskPicture) {
PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable);
- if (pMaskPixmap->drawable.width >= 2048 ||
- pMaskPixmap->drawable.height >= 2048) {
+ if (pMaskPixmap->drawable.width >= max_tex_w ||
+ pMaskPixmap->drawable.height >= max_tex_h) {
RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n",
pMaskPixmap->drawable.width,
pMaskPixmap->drawable.height));
@@ -1016,11 +1046,11 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
}
}
- if (!R300CheckCompositeTexture(pMaskPicture, 1))
+ if (!R300CheckCompositeTexture(pMaskPicture, 1, is_r500))
return FALSE;
}
- if (!R300CheckCompositeTexture(pSrcPicture, 0))
+ if (!R300CheckCompositeTexture(pSrcPicture, 0, is_r500))
return FALSE;
if (!R300GetDestFormat(pDstPicture, &tmp1))
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 837562b..b19b5ca 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4291,11 +4291,14 @@
# define R300_TX_FORMAT_SWAP_YUV (1 << 24)
#define R300_TX_FORMAT2_0 0x4500
+# define R500_TXWIDTH_11 (1 << 15)
+# define R500_TXHEIGHT_11 (1 << 16)
+
#define R300_TX_OFFSET_0 0x4540
# define R300_ENDIAN_SWAP_16_BIT (1 << 0)
# define R300_ENDIAN_SWAP_32_BIT (2 << 0)
# define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)
-# define R300_MACRO_TILE (1 << 2);
+# define R300_MACRO_TILE (1 << 2)
#define R300_TX_ENABLE 0x4104
# define R300_TEX_0_ENABLE (1 << 0)
commit 30b52f8aa6a471455284f59b5b27252743892b13
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 17 23:20:10 2008 -0400
R3xx/R5xx: whitespace cleanup and cruft removal
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index d54b5c6..624269d 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1416,44 +1416,44 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
/* setup the rasterizer */
- if (pMask) {
- BEGIN_ACCEL(20);
- /* 4 components: 2 for tex0, 2 for tex1 */
- OUT_ACCEL_REG(R300_RS_COUNT,
- ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- /* rasterizer source table */
- OUT_ACCEL_REG(R300_RS_IP_0,
- (R300_RS_TEX_PTR(0) |
- R300_RS_SEL_S(R300_RS_SEL_C0) |
- R300_RS_SEL_T(R300_RS_SEL_C1) |
- R300_RS_SEL_R(R300_RS_SEL_K0) |
- R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_ACCEL_REG(R300_RS_IP_1,
- (R300_RS_TEX_PTR(2) |
- R300_RS_SEL_S(R300_RS_SEL_C0) |
- R300_RS_SEL_T(R300_RS_SEL_C1) |
- R300_RS_SEL_R(R300_RS_SEL_K0) |
- R300_RS_SEL_Q(R300_RS_SEL_K1)));
-
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
- /* src tex */
- OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
- R300_RS_INST_TEX_CN_WRITE |
- R300_INST_TEX_ADDR(0)));
- /* mask tex */
- OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
- R300_RS_INST_TEX_CN_WRITE |
- R300_INST_TEX_ADDR(1)));
-
- OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* max num of temps used */
- OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
- R300_ALU_CODE_SIZE(0) |
- R300_TEX_CODE_OFFSET(0) |
- R300_TEX_CODE_SIZE(1)));
-
- } else {
+ if (pMask) {
+ BEGIN_ACCEL(20);
+ /* 4 components: 2 for tex0, 2 for tex1 */
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+ /* rasterizer source table */
+ OUT_ACCEL_REG(R300_RS_IP_0,
+ (R300_RS_TEX_PTR(0) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+ OUT_ACCEL_REG(R300_RS_IP_1,
+ (R300_RS_TEX_PTR(2) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+ /* src tex */
+ OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(0)));
+ /* mask tex */
+ OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(1)));
+
+ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* max num of temps used */
+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ R300_ALU_CODE_SIZE(0) |
+ R300_TEX_CODE_OFFSET(0) |
+ R300_TEX_CODE_SIZE(1)));
+
+ } else {
BEGIN_ACCEL(17);
/* 2 components: 2 for tex0 */
OUT_ACCEL_REG(R300_RS_COUNT,
@@ -1478,244 +1478,198 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_TEX_CODE_OFFSET(0) |
R300_TEX_CODE_SIZE(0)));
- }
-
- OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0)));
-
- if (pMask) {
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(1) |
- R300_RGBA_OUT));
- } else {
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0) |
- R300_RGBA_OUT));
- }
-
- OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
-
- OUT_ACCEL_REG(R300_US_TEX_INST_0,
- (R300_TEX_SRC_ADDR(0) |
- R300_TEX_DST_ADDR(0) |
- R300_TEX_ID(0) |
- R300_TEX_INST(R300_TEX_INST_LD)));
-
- if (pMask) {
- OUT_ACCEL_REG(R300_US_TEX_INST_1,
- (R300_TEX_SRC_ADDR(1) |
- R300_TEX_DST_ADDR(1) |
- R300_TEX_ID(1) |
- R300_TEX_INST(R300_TEX_INST_LD)));
- }
-
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
- (R300_ALU_RGB_ADDR0(0) |
- R300_ALU_RGB_ADDR1(1) |
- R300_ALU_RGB_ADDR2(0) |
- R300_ALU_RGB_ADDRD(0) |
- R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
- R300_ALU_RGB_MASK_G |
- R300_ALU_RGB_MASK_B)) |
- R300_ALU_RGB_TARGET_A));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
- (R300_ALU_RGB_SEL_A(src_color) |
- R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_SEL_B(mask_color) |
- R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
- R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
- R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
- (R300_ALU_ALPHA_ADDR0(0) |
- R300_ALU_ALPHA_ADDR1(1) |
- R300_ALU_ALPHA_ADDR2(0) |
- R300_ALU_ALPHA_ADDRD(0) |
- R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
- R300_ALU_ALPHA_TARGET_A |
- R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
- (R300_ALU_ALPHA_SEL_A(src_alpha) |
- R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_SEL_B(mask_alpha) |
- R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
- R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
- R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE)));
- FINISH_ACCEL();
- } else {
- BEGIN_ACCEL(23);
- OUT_ACCEL_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
- (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
- (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
- (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
-
- OUT_ACCEL_REG(R300_RS_INST_COUNT, 0);
- OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
- OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
- OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
- OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(1)));
- OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(1)));
- OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
- // 7807
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
- R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
- R500_TEX_IGNORE_UNCOVERED));
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_DST_ADDR(0) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
- R500_DX_S_SWIZ_R |
- R500_DX_T_SWIZ_R |
- R500_DX_R_SWIZ_R |
- R500_DX_Q_SWIZ_R |
- R500_DY_ADDR(0) |
- R500_DY_S_SWIZ_R |
- R500_DY_T_SWIZ_R |
- R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
-
- // 0x78105
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_LAST |
- R500_INST_RGB_OMASK_R |
- R500_INST_RGB_OMASK_G |
- R500_INST_RGB_OMASK_B |
- R500_INST_ALPHA_OMASK));
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR1(0) |
- R500_RGB_ADDR1_CONST |
- R500_RGB_ADDR2(0) |
- R500_RGB_ADDR2_CONST |
- R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR1(0) |
- R500_ALPHA_ADDR1_CONST |
- R500_ALPHA_ADDR2(0) |
- R500_ALPHA_ADDR2_CONST |
- R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC0 |
- R500_ALU_RGB_R_SWIZ_B_1 |
- R500_ALU_RGB_B_SWIZ_B_1 |
- R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SWIZ_B_1));//0x00c0c000)
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 |
- R500_ALU_RGBA_G_SWIZ_0 |
- R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));//0x20490000
- FINISH_ACCEL();
- }
+ }
- BEGIN_ACCEL(4);
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0)));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0)));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
- OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
+ if (pMask) {
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(1) |
+ R300_RGBA_OUT));
+ } else {
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0) |
+ R300_RGBA_OUT));
+ }
- blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
- OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
- OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
+ OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
-#if 0
- /* IN operator: Multiply src by mask components or mask alpha.
- * BLEND_CTL_ADD is A * B + C.
- * If a picture is a8, we have to explicitly zero its color values.
- * If the destination is a8, we have to route the alpha to red, I think.
- * If we're doing component alpha where the source for blending is going to
- * be the source alpha (and there's no source value used), we have to zero
- * the source's color values.
- */
- cblend = R200_TXC_OP_MADD | R200_TXC_ARG_C_ZERO;
- ablend = R200_TXA_OP_MADD | R200_TXA_ARG_C_ZERO;
+ OUT_ACCEL_REG(R300_US_TEX_INST_0,
+ (R300_TEX_SRC_ADDR(0) |
+ R300_TEX_DST_ADDR(0) |
+ R300_TEX_ID(0) |
+ R300_TEX_INST(R300_TEX_INST_LD)));
- if (pDstPicture->format == PICT_a8 ||
- (pMask && pMaskPicture->componentAlpha && RadeonBlendOp[op].src_alpha))
- {
- cblend |= R200_TXC_ARG_A_R0_ALPHA;
- } else if (pSrcPicture->format == PICT_a8)
- cblend |= R200_TXC_ARG_A_ZERO;
- else
- cblend |= R200_TXC_ARG_A_R0_COLOR;
- ablend |= R200_TXA_ARG_A_R0_ALPHA;
+ if (pMask) {
+ OUT_ACCEL_REG(R300_US_TEX_INST_1,
+ (R300_TEX_SRC_ADDR(1) |
+ R300_TEX_DST_ADDR(1) |
+ R300_TEX_ID(1) |
+ R300_TEX_INST(R300_TEX_INST_LD)));
+ }
- if (pMask) {
- if (pMaskPicture->componentAlpha &&
- pDstPicture->format != PICT_a8)
- cblend |= R200_TXC_ARG_B_R1_COLOR;
- else
- cblend |= R200_TXC_ARG_B_R1_ALPHA;
- ablend |= R200_TXA_ARG_B_R1_ALPHA;
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
+ (R300_ALU_RGB_ADDR0(0) |
+ R300_ALU_RGB_ADDR1(1) |
+ R300_ALU_RGB_ADDR2(0) |
+ R300_ALU_RGB_ADDRD(0) |
+ R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
+ R300_ALU_RGB_MASK_G |
+ R300_ALU_RGB_MASK_B)) |
+ R300_ALU_RGB_TARGET_A));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
+ (R300_ALU_RGB_SEL_A(src_color) |
+ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
+ R300_ALU_RGB_SEL_B(mask_color) |
+ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
+ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
+ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
+ (R300_ALU_ALPHA_ADDR0(0) |
+ R300_ALU_ALPHA_ADDR1(1) |
+ R300_ALU_ALPHA_ADDR2(0) |
+ R300_ALU_ALPHA_ADDRD(0) |
+ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
+ R300_ALU_ALPHA_TARGET_A |
+ R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
+ (R300_ALU_ALPHA_SEL_A(src_alpha) |
+ R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
+ R300_ALU_ALPHA_SEL_B(mask_alpha) |
+ R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
+ R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE)));
+ FINISH_ACCEL();
} else {
- cblend |= R200_TXC_ARG_B_ZERO | R200_TXC_COMP_ARG_B;
- ablend |= R200_TXA_ARG_B_ZERO | R200_TXA_COMP_ARG_B;
+ BEGIN_ACCEL(23);
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+ OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, 0);
+ OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
+ OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
+ OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
+ OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ R500_US_CODE_END_ADDR(1)));
+ OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ R500_US_CODE_RANGE_SIZE(1)));
+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
+ // 7807
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ R500_DX_S_SWIZ_R |
+ R500_DX_T_SWIZ_R |
+ R500_DX_R_SWIZ_R |
+ R500_DX_Q_SWIZ_R |
+ R500_DY_ADDR(0) |
+ R500_DY_S_SWIZ_R |
+ R500_DY_T_SWIZ_R |
+ R500_DY_R_SWIZ_R |
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+
+ // 0x78105
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_LAST |
+ R500_INST_RGB_OMASK_R |
+ R500_INST_RGB_OMASK_G |
+ R500_INST_RGB_OMASK_B |
+ R500_INST_ALPHA_OMASK));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ R500_RGB_ADDR1(0) |
+ R500_RGB_ADDR1_CONST |
+ R500_RGB_ADDR2(0) |
+ R500_RGB_ADDR2_CONST |
+ R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ R500_ALPHA_ADDR1(0) |
+ R500_ALPHA_ADDR1_CONST |
+ R500_ALPHA_ADDR2(0) |
+ R500_ALPHA_ADDR2_CONST |
+ R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC0 |
+ R500_ALU_RGB_R_SWIZ_B_1 |
+ R500_ALU_RGB_B_SWIZ_B_1 |
+ R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_1));//0x00c0c000)
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));//0x20490000
+ FINISH_ACCEL();
}
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, cblend);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_0, ablend);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_0,
- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
+ BEGIN_ACCEL(4);
+
+ OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
+ OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
- /* Op operator. */
blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blendcntl);
-#endif
+ OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
+ OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
FINISH_ACCEL();
commit 9c9f1b538ed710c3066775fba0a8e936b63087b1
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 17 23:01:37 2008 -0400
R3xx: get masks working and cleanup
RS offset was wrong for mask texture
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 8d9ce64..d54b5c6 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1047,12 +1047,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
TRACE;
- if (pMask && pMaskPicture->componentAlpha)
- //if (pMask)
- return FALSE;
-
- ErrorF("op: 0x%x, src: 0x%x, dst: 0x%x\n", op, pSrcPicture->format, pDstPicture->format);
-
if (!info->XInited3D)
RADEONInit3DEngine(pScrn);
@@ -1436,7 +1430,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1)));
OUT_ACCEL_REG(R300_RS_IP_1,
- (R300_RS_TEX_PTR(1) |
+ (R300_RS_TEX_PTR(2) |
R300_RS_SEL_S(R300_RS_SEL_C0) |
R300_RS_SEL_T(R300_RS_SEL_C1) |
R300_RS_SEL_R(R300_RS_SEL_K0) |
@@ -1539,9 +1533,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_RGB_ADDR1(1) |
R300_ALU_RGB_ADDR2(0) |
R300_ALU_RGB_ADDRD(0) |
- /*R300_ALU_RGB_WMASK((R300_ALU_RGB_MASK_R |
- R300_ALU_RGB_MASK_G |
- R300_ALU_RGB_MASK_B)) |*/
R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
R300_ALU_RGB_MASK_G |
R300_ALU_RGB_MASK_B)) |
@@ -1560,7 +1551,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_ALPHA_ADDR1(1) |
R300_ALU_ALPHA_ADDR2(0) |
R300_ALU_ALPHA_ADDRD(0) |
- /*R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A) |*/
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
R300_ALU_ALPHA_TARGET_A |
R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
commit ef94febd74f8ee63081b61e42f093a5a2b8fbf1e
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 17 22:27:19 2008 -0400
R3xx: minor adjustments
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 2123655..8d9ce64 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1129,22 +1129,22 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
<< R300_WRITE_ENA_0_SHIFT) |
(R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
<< R300_WRITE_ENA_1_SHIFT)));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
<< R300_WRITE_ENA_2_SHIFT)));
} else {
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
@@ -1478,7 +1478,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_INST_TEX_ADDR(0)));
OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* max num of temps used */
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* max num of temps used */
OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(0) |
R300_TEX_CODE_OFFSET(0) |
@@ -1538,7 +1538,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(1) |
R300_ALU_RGB_ADDR2(0) |
- R300_ALU_RGB_ADDRD(2) |
+ R300_ALU_RGB_ADDRD(0) |
/*R300_ALU_RGB_WMASK((R300_ALU_RGB_MASK_R |
R300_ALU_RGB_MASK_G |
R300_ALU_RGB_MASK_B)) |*/
@@ -1559,7 +1559,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(1) |
R300_ALU_ALPHA_ADDR2(0) |
- R300_ALU_ALPHA_ADDRD(2) |
+ R300_ALU_ALPHA_ADDRD(0) |
/*R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A) |*/
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
R300_ALU_ALPHA_TARGET_A |
commit bedbbf196dc97ee5142e7dfae16fb6f317fca5a7
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 17 20:16:25 2008 -0400
R3xx: some progress
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 3b7670b..2123655 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1436,13 +1436,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1)));
OUT_ACCEL_REG(R300_RS_IP_1,
- (R300_RS_TEX_PTR(2) |
+ (R300_RS_TEX_PTR(1) |
R300_RS_SEL_S(R300_RS_SEL_C0) |
R300_RS_SEL_T(R300_RS_SEL_C1) |
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(2) | R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
/* src tex */
OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
R300_RS_INST_TEX_CN_WRITE |
@@ -1471,7 +1471,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_RS_SEL_T(R300_RS_SEL_C1) |
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
/* src tex */
OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
R300_RS_INST_TEX_CN_WRITE |
commit af0e626c132de2dd9958fec657fcc85d4c0fe5e1
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 17 18:07:12 2008 -0400
R3xx: fix errant w
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index bfb7f38..3b7670b 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1190,7 +1190,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
if (pMask) {
BEGIN_ACCEL(22);
/* flush the PVS before updating??? */
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);w
+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
((0 << R300_PVS_FIRST_INST_SHIFT) |
commit 9bc7c2ec4048e1677547c1d60c51ccb954f7589a
Author: Alex Deucher <alex at samba.(none)>
Date: Fri Mar 14 20:12:22 2008 -0400
R3xx: odds and ends...
still not working.
- swizzle US output for BGR formats
- no need to write to temps in ALU ops,
write to output only
- flush the PVS before updating
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 5511200..bfb7f38 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -569,7 +569,7 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset));
if ((txpitch & 0x1f) != 0)
RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
-
+
for (i = 0; i < sizeof(R200TexFormats) / sizeof(R200TexFormats[0]); i++)
{
if (R200TexFormats[i].fmt == pPict->format)
@@ -720,7 +720,7 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
RADEONInit3DEngine(pScrn);
if (!RADEONGetDestFormat(pDstPicture, &dst_format))
- return FALSE;
+ return FALSE;
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
@@ -911,7 +911,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
BEGIN_ACCEL(6);
OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter);
- OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0x0);
+ OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0);
OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0);
OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1);
OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch);
@@ -1090,7 +1090,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
RADEON_SWITCH_TO_3D();
/* setup the VAP */
-
if (has_tcl) {
BEGIN_ACCEL(9);
OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
@@ -1189,7 +1188,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
/* setup the vertex shader */
if (has_tcl) {
if (pMask) {
- BEGIN_ACCEL(21);
+ BEGIN_ACCEL(22);
+ /* flush the PVS before updating??? */
+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);w
+
OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
((0 << R300_PVS_FIRST_INST_SHIFT) |
(2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
@@ -1197,7 +1199,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
(2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
} else {
- BEGIN_ACCEL(17);
+ BEGIN_ACCEL(18);
+ /* flush the PVS before updating??? */
+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+
OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
((0 << R300_PVS_FIRST_INST_SHIFT) |
(1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
@@ -1385,8 +1390,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
case PICT_x8r8g8b8:
- case PICT_a8b8g8r8:
- case PICT_x8b8g8r8:
default:
output_fmt = (R300_OUT_FMT_C4_8 |
R300_OUT_FMT_C0_SEL_BLUE |
@@ -1394,6 +1397,14 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_OUT_FMT_C2_SEL_RED |
R300_OUT_FMT_C3_SEL_ALPHA);
break;
+ case PICT_a8b8g8r8:
+ case PICT_x8b8g8r8:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_RED |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_BLUE |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
case PICT_r5g6b5:
case PICT_a1r5g5b5:
case PICT_x1r5g5b5:
@@ -1528,9 +1539,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_RGB_ADDR1(1) |
R300_ALU_RGB_ADDR2(0) |
R300_ALU_RGB_ADDRD(2) |
- R300_ALU_RGB_WMASK((R300_ALU_RGB_MASK_R |
+ /*R300_ALU_RGB_WMASK((R300_ALU_RGB_MASK_R |
R300_ALU_RGB_MASK_G |
- R300_ALU_RGB_MASK_B)) |
+ R300_ALU_RGB_MASK_B)) |*/
R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
R300_ALU_RGB_MASK_G |
R300_ALU_RGB_MASK_B)) |
@@ -1549,7 +1560,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_ALPHA_ADDR1(1) |
R300_ALU_ALPHA_ADDR2(0) |
R300_ALU_ALPHA_ADDRD(2) |
- R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A) |
+ /*R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A) |*/
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
R300_ALU_ALPHA_TARGET_A |
R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index cd8fce7..837562b 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4140,6 +4140,7 @@
# define R300_CLIP_DISABLE (1 << 16)
# define R300_UCP_CULL_ONLY_ENA (1 << 17)
# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18)
+#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
#define R300_SU_TEX_WRAP 0x42a0
#define R300_SU_POLY_OFFSET_ENABLE 0x42b4
commit 96bea7906c4706fcd57a9cd8f1ce3feab6ac676d
Author: Alex Deucher <alex at samba.(none)>
Date: Fri Mar 14 15:59:36 2008 -0400
R3xx: theoretical support for component alpha
masks are still broken so...
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index fc04463..5511200 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1333,7 +1333,40 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
else
src_alpha = R300_ALU_ALPHA_SRC0_A;
- if (pMask) {
+ if (pMask && pMaskPicture->componentAlpha) {
+ if (RadeonBlendOp[op].src_alpha) {
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
+ src_color = R300_ALU_RGB_1_0;
+ src_alpha = R300_ALU_ALPHA_1_0;
+ } else {
+ src_color = R300_ALU_RGB_SRC0_AAA;
+ src_alpha = R300_ALU_ALPHA_SRC0_A;
+ }
+
+ mask_color = R300_ALU_RGB_SRC1_RGB;
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ mask_alpha = R300_ALU_ALPHA_1_0;
+ else
+ mask_alpha = R300_ALU_ALPHA_SRC1_A;
+
+ } else {
+ src_color = R300_ALU_RGB_SRC0_RGB;
+
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ src_alpha = R300_ALU_ALPHA_1_0;
+ else
+ src_alpha = R300_ALU_ALPHA_SRC0_A;
+
+ mask_color = R300_ALU_RGB_SRC1_RGB;
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ mask_alpha = R300_ALU_ALPHA_1_0;
+ else
+ mask_alpha = R300_ALU_ALPHA_SRC1_A;
+
+ }
+ } else if (pMask) {
if (PICT_FORMAT_A(pMaskPicture->format) == 0)
mask_color = R300_ALU_RGB_1_0;
else
commit cffe3dcc8991cd7c457a9c1a9f41055aa9ea3436
Author: Alex Deucher <alex at samba.(none)>
Date: Fri Mar 14 14:37:43 2008 -0400
R3xx: VS WIP
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index dc717c2..fc04463 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1119,12 +1119,12 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_SIGNED_0 |
(R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
(0 << R300_SKIP_DWORDS_1_SHIFT) |
- (10 << R300_DST_VEC_LOC_1_SHIFT) |
+ (1 << R300_DST_VEC_LOC_1_SHIFT) |
R300_SIGNED_1));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
(0 << R300_SKIP_DWORDS_2_SHIFT) |
- (14 << R300_DST_VEC_LOC_2_SHIFT) |
+ (2 << R300_DST_VEC_LOC_2_SHIFT) |
R300_LAST_VEC_2 |
R300_SIGNED_2));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
@@ -1244,21 +1244,21 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_OFFSET(1) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_OFFSET(1) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_OFFSET(1) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
@@ -1266,10 +1266,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
if (pMask) {
/* PVS inst 2 */
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f04203);
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
@@ -1278,21 +1274,21 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(14) |
+ R300_PVS_SRC_OFFSET(2) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(14) |
+ R300_PVS_SRC_OFFSET(2) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
- R300_PVS_SRC_OFFSET(14) |
+ R300_PVS_SRC_OFFSET(2) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
commit b73f52a50dfd6ff8d92f04d6b510c39582c6ac67
Author: Alex Deucher <alex at samba.(none)>
Date: Fri Mar 14 14:20:49 2008 -0400
R3xx/R5xx: enable VS for mask texture
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 58be88c..dc717c2 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1124,7 +1124,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
(0 << R300_SKIP_DWORDS_2_SHIFT) |
- (11 << R300_DST_VEC_LOC_2_SHIFT) |
+ (14 << R300_DST_VEC_LOC_2_SHIFT) |
R300_LAST_VEC_2 |
R300_SIGNED_2));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
@@ -1188,7 +1188,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
/* setup the vertex shader */
if (has_tcl) {
- if (0/*pMask*/) {
+ if (pMask) {
BEGIN_ACCEL(21);
OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
((0 << R300_PVS_FIRST_INST_SHIFT) |
@@ -1207,14 +1207,12 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
}
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
/* PVS inst 0 */
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
R300_PVS_DST_OFFSET(0) |
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
@@ -1222,7 +1220,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
@@ -1230,7 +1227,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
@@ -1240,14 +1236,12 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
/* PVS inst 1 */
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
R300_PVS_DST_OFFSET(1) |
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(10) |
@@ -1255,7 +1249,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(10) |
@@ -1263,7 +1256,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(10) |
@@ -1272,12 +1264,39 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
- if (0/*pMask*/) {
+ if (pMask) {
/* PVS inst 2 */
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f04203);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f04203);
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(2) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(14) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(14) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(14) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
}
OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
commit 569a14ca9be1e18fe9921edc816ac3dc32d6cca7
Author: Alex Deucher <alex at samba.(none)>
Date: Fri Mar 14 13:32:12 2008 -0400
R3xx/R5xx: Fix magic numbers in vertex shaders
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 0644e3b..58be88c 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1206,16 +1206,74 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
}
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ /* PVS inst 0 */
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 1 */
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ //OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
if (0/*pMask*/) {
+ /* PVS inst 2 */
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f04203);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index a0aa486..cd8fce7 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3990,6 +3990,123 @@
# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0
#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204
+/* PVS instructions */
+/* Opcode and dst instruction */
+#define R300_PVS_DST_OPCODE(x) (x << 0)
+/* Vector ops */
+# define R300_VECTOR_NO_OP 0
+# define R300_VE_DOT_PRODUCT 1
+# define R300_VE_MULTIPLY 2
+# define R300_VE_ADD 3
+# define R300_VE_MULTIPLY_ADD 4
+# define R300_VE_DISTANCE_VECTOR 5
+# define R300_VE_FRACTION 6
+# define R300_VE_MAXIMUM 7
+# define R300_VE_MINIMUM 8
+# define R300_VE_SET_GREATER_THAN_EQUAL 9
+# define R300_VE_SET_LESS_THAN 10
+# define R300_VE_MULTIPLYX2_ADD 11
+# define R300_VE_MULTIPLY_CLAMP 12
+# define R300_VE_FLT2FIX_DX 13
+# define R300_VE_FLT2FIX_DX_RND 14
+/* R500 additions */
+# define R500_VE_PRED_SET_EQ_PUSH 15
+# define R500_VE_PRED_SET_GT_PUSH 16
+# define R500_VE_PRED_SET_GTE_PUSH 17
+# define R500_VE_PRED_SET_NEQ_PUSH 18
+# define R500_VE_COND_WRITE_EQ 19
+# define R500_VE_COND_WRITE_GT 20
+# define R500_VE_COND_WRITE_GTE 21
+# define R500_VE_COND_WRITE_NEQ 22
+# define R500_VE_COND_MUX_EQ 23
+# define R500_VE_COND_MUX_GT 24
+# define R500_VE_COND_MUX_GTE 25
+# define R500_VE_SET_GREATER_THAN 26
+# define R500_VE_SET_EQUAL 27
+# define R500_VE_SET_NOT_EQUAL 28
+/* Math ops */
+# define R300_MATH_NO_OP 0
+# define R300_ME_EXP_BASE2_DX 1
+# define R300_ME_LOG_BASE2_DX 2
+# define R300_ME_EXP_BASEE_FF 3
+# define R300_ME_LIGHT_COEFF_DX 4
+# define R300_ME_POWER_FUNC_FF 5
+# define R300_ME_RECIP_DX 6
+# define R300_ME_RECIP_FF 7
+# define R300_ME_RECIP_SQRT_DX 8
+# define R300_ME_RECIP_SQRT_FF 9
+# define R300_ME_MULTIPLY 10
+# define R300_ME_EXP_BASE2_FULL_DX 11
+# define R300_ME_LOG_BASE2_FULL_DX 12
+# define R300_ME_POWER_FUNC_FF_CLAMP_B 13
+# define R300_ME_POWER_FUNC_FF_CLAMP_B1 14
+# define R300_ME_POWER_FUNC_FF_CLAMP_01 15
+# define R300_ME_SIN 16
+# define R300_ME_COS 17
+/* R500 additions */
+# define R500_ME_LOG_BASE2_IEEE 18
+# define R500_ME_RECIP_IEEE 19
+# define R500_ME_RECIP_SQRT_IEEE 20
+# define R500_ME_PRED_SET_EQ 21
+# define R500_ME_PRED_SET_GT 22
+# define R500_ME_PRED_SET_GTE 23
+# define R500_ME_PRED_SET_NEQ 24
+# define R500_ME_PRED_SET_CLR 25
+# define R500_ME_PRED_SET_INV 26
+# define R500_ME_PRED_SET_POP 27
+# define R500_ME_PRED_SET_RESTORE 28
+/* macro */
+# define R300_PVS_MACRO_OP_2CLK_MADD 0
+# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1
+#define R300_PVS_DST_MATH_INST (1 << 6)
+#define R300_PVS_DST_MACRO_INST (1 << 7)
+#define R300_PVS_DST_REG_TYPE(x) (x << 8)
+# define R300_PVS_DST_REG_TEMPORARY 0
+# define R300_PVS_DST_REG_A0 1
+# define R300_PVS_DST_REG_OUT 2
+# define R500_PVS_DST_REG_OUT_REPL_X 3
+# define R300_PVS_DST_REG_ALT_TEMPORARY 4
+# define R300_PVS_DST_REG_INPUT 5
+#define R300_PVS_DST_ADDR_MODE_1 (1 << 12)
+#define R300_PVS_DST_OFFSET(x) (x << 13)
+#define R300_PVS_DST_WE_X (1 << 20)
+#define R300_PVS_DST_WE_Y (1 << 21)
+#define R300_PVS_DST_WE_Z (1 << 22)
+#define R300_PVS_DST_WE_W (1 << 23)
+#define R300_PVS_DST_VE_SAT (1 << 24)
+#define R300_PVS_DST_ME_SAT (1 << 25)
+#define R300_PVS_DST_PRED_ENABLE (1 << 26)
+#define R300_PVS_DST_PRED_SENSE (1 << 27)
+#define R300_PVS_DST_DUAL_MATH_OP (1 << 28)
+#define R300_PVS_DST_ADDR_SEL(x) (x << 29)
+#define R300_PVS_DST_ADDR_MODE_0 (1 << 31)
+/* src operand instruction */
+#define R300_PVS_SRC_REG_TYPE(x) (x << 0)
+# define R300_PVS_SRC_REG_TEMPORARY 0
+# define R300_PVS_SRC_REG_INPUT 1
+# define R300_PVS_SRC_REG_CONSTANT 2
+# define R300_PVS_SRC_REG_ALT_TEMPORARY 3
+#define R300_SPARE_0 (1 << 2)
+#define R300_PVS_SRC_ABS_XYZW (1 << 3)
+#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4)
+#define R300_PVS_SRC_OFFSET(x) (x << 5)
+#define R300_PVS_SRC_SWIZZLE_X(x) (x << 13)
+#define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16)
+#define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19)
+#define R300_PVS_SRC_SWIZZLE_W(x) (x << 22)
+# define R300_PVS_SRC_SELECT_X 0
+# define R300_PVS_SRC_SELECT_Y 1
+# define R300_PVS_SRC_SELECT_Z 2
+# define R300_PVS_SRC_SELECT_W 3
+# define R300_PVS_SRC_SELECT_FORCE_0 4
+# define R300_PVS_SRC_SELECT_FORCE_1 5
+#define R300_PVS_SRC_NEG_X (1 << 25)
+#define R300_PVS_SRC_NEG_Y (1 << 26)
+#define R300_PVS_SRC_NEG_Z (1 << 27)
+#define R300_PVS_SRC_NEG_W (1 << 28)
+#define R300_PVS_SRC_ADDR_SEL(x) (x << 29)
+#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31)
+
#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
#define R300_VAP_OUT_VTX_FMT_0 0x2090
# define R300_VTX_POS_PRESENT (1 << 0)
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 4ebb73b..2d5819a 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -268,16 +268,64 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
commit 4878997529601d62e257aa1c9112bd460561de73
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Mar 13 21:23:40 2008 -0400
R3xx: make sure to set the FS code size correctly
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index f367abd..0644e3b 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1334,6 +1334,14 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
R300_RS_INST_TEX_CN_WRITE |
R300_INST_TEX_ADDR(1)));
+
+ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* max num of temps used */
+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ R300_ALU_CODE_SIZE(0) |
+ R300_TEX_CODE_OFFSET(0) |
+ R300_TEX_CODE_SIZE(1)));
+
} else {
BEGIN_ACCEL(17);
/* 2 components: 2 for tex0 */
@@ -1351,15 +1359,16 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
R300_RS_INST_TEX_CN_WRITE |
R300_INST_TEX_ADDR(0)));
+
+ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* max num of temps used */
+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ R300_ALU_CODE_SIZE(0) |
+ R300_TEX_CODE_OFFSET(0) |
+ R300_TEX_CODE_SIZE(0)));
+
}
- OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* max num of temps used */
- OUT_ACCEL_REG(R300_US_CODE_OFFSET,
- (R300_ALU_CODE_OFFSET(0) |
- R300_ALU_CODE_SIZE(1) |
- R300_TEX_CODE_OFFSET(0) |
- R300_TEX_CODE_SIZE(1)));
OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
(R300_ALU_START(0) |
R300_ALU_SIZE(0) |
@@ -1375,12 +1384,22 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_SIZE(0) |
R300_TEX_START(0) |
R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0) |
- R300_RGBA_OUT));
+
+ if (pMask) {
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(1) |
+ R300_RGBA_OUT));
+ } else {
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0) |
+ R300_RGBA_OUT));
+ }
OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
commit 22f46b88ef05afb6a6b6d70007ac4980a446430e
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Mar 13 20:25:33 2008 -0400
R3xx: attempt to setup the rasterizer properly for mask texture
Not working yet
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index afc6360..f367abd 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1047,8 +1047,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
TRACE;
- //if (pMask && pMaskPicture->componentAlpha)
- if (pMask)
+ if (pMask && pMaskPicture->componentAlpha)
+ //if (pMask)
return FALSE;
ErrorF("op: 0x%x, src: 0x%x, dst: 0x%x\n", op, pSrcPicture->format, pDstPicture->format);
@@ -1092,7 +1092,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
/* setup the VAP */
if (has_tcl) {
- BEGIN_ACCEL(28);
+ BEGIN_ACCEL(9);
OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
@@ -1100,7 +1100,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(4 << R300_PVS_NUM_FPUS_SHIFT) |
(12 << R300_VF_MAX_VTX_NUM_SHIFT)));
} else {
- BEGIN_ACCEL(10);
+ BEGIN_ACCEL(8);
OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
@@ -1184,15 +1184,27 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
<< R300_WRITE_ENA_2_SHIFT)));
}
+ FINISH_ACCEL();
/* setup the vertex shader */
if (has_tcl) {
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
- ((0 << R300_PVS_FIRST_INST_SHIFT) |
- (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (1 << R300_PVS_LAST_INST_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
- (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ if (0/*pMask*/) {
+ BEGIN_ACCEL(21);
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (2 << R300_PVS_LAST_INST_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ } else {
+ BEGIN_ACCEL(17);
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (1 << R300_PVS_LAST_INST_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ }
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
@@ -1203,6 +1215,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ if (0/*pMask*/) {
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f04203);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ }
+
OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
@@ -1210,12 +1229,17 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
+ FINISH_ACCEL();
}
+
+ BEGIN_ACCEL(4);
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
((2 << R300_TEX_0_COMP_CNT_SHIFT) |
(2 << R300_TEX_1_COMP_CNT_SHIFT)));
+ OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
+ OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
FINISH_ACCEL();
/* setup pixel shader */
@@ -1279,27 +1303,58 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
break;
}
- if (pMask)
- BEGIN_ACCEL(18);
- else
+
+ /* setup the rasterizer */
+ if (pMask) {
+ BEGIN_ACCEL(20);
+ /* 4 components: 2 for tex0, 2 for tex1 */
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+ /* rasterizer source table */
+ OUT_ACCEL_REG(R300_RS_IP_0,
+ (R300_RS_TEX_PTR(0) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+ OUT_ACCEL_REG(R300_RS_IP_1,
+ (R300_RS_TEX_PTR(2) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(2) | R300_TX_OFFSET_RS(6));
+ /* src tex */
+ OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(0)));
+ /* mask tex */
+ OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(1)));
+ } else {
BEGIN_ACCEL(17);
- OUT_ACCEL_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R300_RS_IP_0,
- (R300_RS_TEX_PTR(0) |
- R300_RS_COL_PTR(0) |
- R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) |
- R300_RS_SEL_S(R300_RS_SEL_C0) |
- R300_RS_SEL_T(R300_RS_SEL_C1) |
- R300_RS_SEL_R(R300_RS_SEL_K0) |
- R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
- OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
- R300_RS_INST_TEX_CN_WRITE |
- R300_INST_TEX_ADDR(0)));
+ /* 2 components: 2 for tex0 */
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+ OUT_ACCEL_REG(R300_RS_IP_0,
+ (R300_RS_TEX_PTR(0) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+ /* src tex */
+ OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(0)));
+ }
+
OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* max num of temps used */
OUT_ACCEL_REG(R300_US_CODE_OFFSET,
(R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(1) |
@@ -1334,6 +1389,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_TEX_DST_ADDR(0) |
R300_TEX_ID(0) |
R300_TEX_INST(R300_TEX_INST_LD)));
+
if (pMask) {
OUT_ACCEL_REG(R300_US_TEX_INST_1,
(R300_TEX_SRC_ADDR(1) |
@@ -1346,7 +1402,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(1) |
R300_ALU_RGB_ADDR2(0) |
- R300_ALU_RGB_ADDRD(0) |
+ R300_ALU_RGB_ADDRD(2) |
R300_ALU_RGB_WMASK((R300_ALU_RGB_MASK_R |
R300_ALU_RGB_MASK_G |
R300_ALU_RGB_MASK_B)) |
@@ -1367,7 +1423,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(1) |
R300_ALU_ALPHA_ADDR2(0) |
- R300_ALU_ALPHA_ADDRD(0) |
+ R300_ALU_ALPHA_ADDRD(2) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A) |
R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
R300_ALU_ALPHA_TARGET_A |
@@ -1480,9 +1536,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
FINISH_ACCEL();
}
- BEGIN_ACCEL(6);
- OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
- OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
+ BEGIN_ACCEL(4);
OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
commit 081fc9e892fa3d2e07b7db65b2e2719646255463
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Mar 13 18:38:26 2008 -0400
R3xx: more mask work
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 6cbe0bb..afc6360 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1279,7 +1279,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
break;
}
- BEGIN_ACCEL(17);
+ if (pMask)
+ BEGIN_ACCEL(18);
+ else
+ BEGIN_ACCEL(17);
OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
@@ -1331,10 +1334,17 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_TEX_DST_ADDR(0) |
R300_TEX_ID(0) |
R300_TEX_INST(R300_TEX_INST_LD)));
+ if (pMask) {
+ OUT_ACCEL_REG(R300_US_TEX_INST_1,
+ (R300_TEX_SRC_ADDR(1) |
+ R300_TEX_DST_ADDR(1) |
+ R300_TEX_ID(1) |
+ R300_TEX_INST(R300_TEX_INST_LD)));
+ }
OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
(R300_ALU_RGB_ADDR0(0) |
- R300_ALU_RGB_ADDR1(0) |
+ R300_ALU_RGB_ADDR1(1) |
R300_ALU_RGB_ADDR2(0) |
R300_ALU_RGB_ADDRD(0) |
R300_ALU_RGB_WMASK((R300_ALU_RGB_MASK_R |
@@ -1355,7 +1365,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
(R300_ALU_ALPHA_ADDR0(0) |
- R300_ALU_ALPHA_ADDR1(0) |
+ R300_ALU_ALPHA_ADDR1(1) |
R300_ALU_ALPHA_ADDR2(0) |
R300_ALU_ALPHA_ADDRD(0) |
R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A) |
commit 2bf0236c03538ace3ce6d0e68f0829fc47d1385b
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Mar 13 18:32:00 2008 -0400
R3xx: enable composite for non-mask cases
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 9bdb403..6cbe0bb 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -946,7 +946,7 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
-#if 1
+#if 0
/* Throw out cases that aren't going to be our rotation first */
if (pMaskPicture != NULL || op != PictOpSrc || pSrcPicture->pDrawable == NULL)
RADEON_FALLBACK(("Junk driver\n"));
@@ -1047,9 +1047,12 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
TRACE;
- if (pMask && pMaskPicture->componentAlpha)
+ //if (pMask && pMaskPicture->componentAlpha)
+ if (pMask)
return FALSE;
+ ErrorF("op: 0x%x, src: 0x%x, dst: 0x%x\n", op, pSrcPicture->format, pDstPicture->format);
+
if (!info->XInited3D)
RADEONInit3DEngine(pScrn);
commit 74286ba41302107d2fc626fee2181f7c4bc18164
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Mar 13 18:25:32 2008 -0400
R3xx: add basic mask support
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index fd900cf..9bdb403 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1221,6 +1221,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(info->ChipFamily == CHIP_FAMILY_RS740)) {
CARD32 output_fmt;
int src_color, src_alpha;
+ int mask_color, mask_alpha;
if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
src_color = R300_ALU_RGB_1_0;
@@ -1232,6 +1233,20 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
else
src_alpha = R300_ALU_ALPHA_SRC0_A;
+ if (pMask) {
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ mask_color = R300_ALU_RGB_1_0;
+ else
+ mask_color = R300_ALU_RGB_SRC1_AAA;
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ mask_alpha = R300_ALU_ALPHA_1_0;
+ else
+ mask_alpha = R300_ALU_ALPHA_SRC1_A;
+ } else {
+ mask_color = R300_ALU_RGB_1_0;
+ mask_alpha = R300_ALU_ALPHA_1_0;
+ }
/* shader output swizzling */
switch (pDstPicture->format) {
@@ -1329,7 +1344,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
(R300_ALU_RGB_SEL_A(src_color) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+ R300_ALU_RGB_SEL_B(mask_color) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
@@ -1347,7 +1362,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
(R300_ALU_ALPHA_SEL_A(src_alpha) |
R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) |
+ R300_ALU_ALPHA_SEL_B(mask_alpha) |
R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
commit a2bbe10d866567911b68f222b4758624bfe9bf84
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Mar 13 18:16:53 2008 -0400
R300: setup source selects and output swizzling
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 682103b..fd900cf 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1047,11 +1047,14 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
TRACE;
+ if (pMask && pMaskPicture->componentAlpha)
+ return FALSE;
+
if (!info->XInited3D)
RADEONInit3DEngine(pScrn);
if (!R300GetDestFormat(pDstPicture, &dst_format))
- return FALSE;
+ return FALSE;
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
@@ -1216,7 +1219,49 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
if (IS_R300_VARIANT ||
(info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740)) {
- BEGIN_ACCEL(16);
+ CARD32 output_fmt;
+ int src_color, src_alpha;
+
+ if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
+ src_color = R300_ALU_RGB_1_0;
+ else
+ src_color = R300_ALU_RGB_SRC0_RGB;
+
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ src_alpha = R300_ALU_ALPHA_1_0;
+ else
+ src_alpha = R300_ALU_ALPHA_SRC0_A;
+
+
+ /* shader output swizzling */
+ switch (pDstPicture->format) {
+ case PICT_a8r8g8b8:
+ case PICT_x8r8g8b8:
+ case PICT_a8b8g8r8:
+ case PICT_x8b8g8r8:
+ default:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_r5g6b5:
+ case PICT_a1r5g5b5:
+ case PICT_x1r5g5b5:
+ output_fmt = (R300_OUT_FMT_C_5_6_5 |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_a8:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_ALPHA);
+ break;
+ }
+
+ BEGIN_ACCEL(17);
OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
@@ -1260,11 +1305,15 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_TEX_START(0) |
R300_TEX_SIZE(0) |
R300_RGBA_OUT));
+
+ OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
+
OUT_ACCEL_REG(R300_US_TEX_INST_0,
(R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(0) |
R300_TEX_ID(0) |
R300_TEX_INST(R300_TEX_INST_LD)));
+
OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
(R300_ALU_RGB_ADDR0(0) |
R300_ALU_RGB_ADDR1(0) |
@@ -1278,7 +1327,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_RGB_MASK_B)) |
R300_ALU_RGB_TARGET_A));
OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
- (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+ (R300_ALU_RGB_SEL_A(src_color) |
R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
@@ -1296,7 +1345,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_ALU_ALPHA_TARGET_A |
R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
- (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) |
+ (R300_ALU_ALPHA_SEL_A(src_alpha) |
R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) |
R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
commit b9974ecce7d1932595226004858b08a7a6b188dc
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Mar 13 17:35:38 2008 -0400
R3xx: set the texture id and add some register info
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 0423435..682103b 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -896,6 +896,8 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST));
+ txfilter |= (unit << R300_TX_ID_SHIFT);
+
switch (pPict->filter) {
case PictFilterNearest:
txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
@@ -1227,7 +1229,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1)));
OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
- OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
+ OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(0)));
OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
OUT_ACCEL_REG(R300_US_CODE_OFFSET,
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index a08654d..a0aa486 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4040,6 +4040,7 @@
# define R300_RS_COUNT_HIRES_EN (1 << 18)
#define R300_RS_IP_0 0x4310
+#define R300_RS_IP_1 0x4314
# define R300_RS_TEX_PTR(x) (x << 0)
# define R300_RS_COL_PTR(x) (x << 6)
# define R300_RS_COL_FMT(x) (x << 9)
@@ -4067,7 +4068,10 @@
# define R300_RS_W_EN (1 << 4)
# define R300_TX_OFFSET_RS(x) (x << 5)
#define R300_RS_INST_0 0x4330
+#define R300_RS_INST_1 0x4334
+# define R300_INST_TEX_ID(x) (x << 0)
# define R300_RS_INST_TEX_CN_WRITE (1 << 3)
+# define R300_INST_TEX_ADDR(x) (x << 6)
#define R300_TX_INVALTAGS 0x4100
#define R300_TX_FILTER0_0 0x4400
@@ -4086,6 +4090,7 @@
# define R300_TX_MIN_FILTER_NEAREST (1 << 11)
# define R300_TX_MAG_FILTER_LINEAR (2 << 9)
# define R300_TX_MIN_FILTER_LINEAR (2 << 11)
+# define R300_TX_ID_SHIFT 28
#define R300_TX_FILTER1_0 0x4440
#define R300_TX_FORMAT0_0 0x4480
# define R300_TXWIDTH_SHIFT 0
@@ -4193,7 +4198,7 @@
# define R300_OUT_FMT_C2_16_MPEG (7 << 0)
# define R300_OUT_FMT_C2_4 (8 << 0)
# define R300_OUT_FMT_C_3_3_2 (9 << 0)
-# define R300_OUT_FMT_C_6_5_6 (10 << 0)
+# define R300_OUT_FMT_C_5_6_5 (10 << 0)
# define R300_OUT_FMT_C_11_11_10 (11 << 0)
# define R300_OUT_FMT_C_10_11_11 (12 << 0)
# define R300_OUT_FMT_C_2_10_10_10 (13 << 0)
@@ -4241,6 +4246,8 @@
#define R300_US_CODE_ADDR_2 0x4618
#define R300_US_CODE_ADDR_3 0x461c
#define R300_US_TEX_INST_0 0x4620
+#define R300_US_TEX_INST_1 0x4624
+#define R300_US_TEX_INST_2 0x4628
# define R300_TEX_SRC_ADDR(x) (x << 0)
# define R300_TEX_DST_ADDR(x) (x << 6)
# define R300_TEX_ID(x) (x << 11)
@@ -4251,6 +4258,8 @@
# define R300_TEX_INST_PROJ 3
# define R300_TEX_INST_LODBIAS 4
#define R300_US_ALU_RGB_ADDR_0 0x46c0
+#define R300_US_ALU_RGB_ADDR_1 0x46c4
+#define R300_US_ALU_RGB_ADDR_2 0x46c8
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_RGB_ADDR0(x) (x << 0)
@@ -4270,6 +4279,8 @@
# define R300_ALU_RGB_TARGET_C (2 << 29)
# define R300_ALU_RGB_TARGET_D (3 << 29)
#define R300_US_ALU_RGB_INST_0 0x48c0
+#define R300_US_ALU_RGB_INST_1 0x48c4
+#define R300_US_ALU_RGB_INST_2 0x48c8
# define R300_ALU_RGB_SEL_A(x) (x << 0)
# define R300_ALU_RGB_SRC0_RGB 0
# define R300_ALU_RGB_SRC0_RRR 1
@@ -4339,6 +4350,8 @@
# define R300_ALU_RGB_CLAMP (1 << 30)
# define R300_ALU_RGB_INSERT_NOP (1 << 31)
#define R300_US_ALU_ALPHA_ADDR_0 0x47c0
+#define R300_US_ALU_ALPHA_ADDR_1 0x47c4
+#define R300_US_ALU_ALPHA_ADDR_2 0x47c8
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_ALPHA_ADDR0(x) (x << 0)
@@ -4357,6 +4370,8 @@
# define R300_ALU_ALPHA_TARGET_C (2 << 25)
# define R300_ALU_ALPHA_TARGET_D (3 << 25)
#define R300_US_ALU_ALPHA_INST_0 0x49c0
+#define R300_US_ALU_ALPHA_INST_1 0x49c4
+#define R300_US_ALU_ALPHA_INST_2 0x49c8
# define R300_ALU_ALPHA_SEL_A(x) (x << 0)
# define R300_ALU_ALPHA_SRC0_R 0
# define R300_ALU_ALPHA_SRC0_G 1
commit 0ef700b7da5e554a0d0d166f3fde85ff45c9eb1f
Author: Alex Deucher <alex at samba.(none)>
Date: Thu Mar 13 17:02:25 2008 -0400
R3xx/R5xx: enable blending
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 31e1206..0423435 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1407,7 +1407,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
- OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl);
+ OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
#if 0
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 94d5f31..a08654d 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4433,6 +4433,9 @@
#define R300_RB3D_ZTOP 0x4f14
#define R300_RB3D_ROPCNTL 0x4e18
#define R300_RB3D_BLENDCNTL 0x4e04
+# define R300_ALPHA_BLEND_ENABLE (1 << 0)
+# define R300_SEPARATE_ALPHA_ENABLE (1 << 1)
+# define R300_READ_ENABLE (1 << 2)
#define R300_RB3D_ABLENDCNTL 0x4e08
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
#define R300_RB3D_COLOROFFSET0 0x4e28
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