xf86-video-intel: Branch 'xvmc' - 74 commits - configure.ac man/intel.man man/Makefile.am src/bios_reader/Makefile.am src/brw_structs.h src/ch7017/ch7017.c src/ch7017/Makefile.am src/ch7xxx/ch7xxx.c src/ch7xxx/Makefile.am src/common.h src/i810_driver.c src/i810_reg.h src/i830_accel.c src/i830_crt.c src/i830_debug.c src/i830_display.c src/i830_dri.c src/i830_driver.c src/i830_dvo.c src/i830.h src/i830_i2c.c src/i830_lvds.c src/i830_memory.c src/i830_quirks.c src/i830_sdvo.c src/i830_tv.c src/i830_video.c src/i830_video.h src/i965_render.c src/i965_video.c src/ivch/ivch.c src/ivch/Makefile.am src/Makefile.am src/reg_dumper/.gitignore src/reg_dumper/idle.c src/reg_dumper/Makefile.am src/reg_dumper/stepping.c src/sil164/Makefile.am src/sil164/sil164.c src/tfp410/Makefile.am src/tfp410/tfp410.c
Zhenyu Wang
zhen at kemper.freedesktop.org
Mon Mar 10 23:45:13 PDT 2008
configure.ac | 16
man/Makefile.am | 1
man/intel.man | 7
src/Makefile.am | 4
src/bios_reader/Makefile.am | 3
src/brw_structs.h | 12
src/ch7017/Makefile.am | 3
src/ch7017/ch7017.c | 2
src/ch7xxx/Makefile.am | 3
src/ch7xxx/ch7xxx.c | 2
src/common.h | 30 +
src/i810_driver.c | 14
src/i810_reg.h | 91 ++++
src/i830.h | 9
src/i830_accel.c | 3
src/i830_crt.c | 1
src/i830_debug.c | 220 +++++++++--
src/i830_display.c | 181 +++++++--
src/i830_dri.c | 101 +----
src/i830_driver.c | 856 ++++++++++++++++++++++++--------------------
src/i830_dvo.c | 6
src/i830_i2c.c | 9
src/i830_lvds.c | 73 +++
src/i830_memory.c | 96 +++-
src/i830_quirks.c | 197 +++++++++-
src/i830_sdvo.c | 18
src/i830_tv.c | 2
src/i830_video.c | 68 ++-
src/i830_video.h | 1
src/i965_render.c | 6
src/i965_video.c | 5
src/ivch/Makefile.am | 3
src/ivch/ivch.c | 2
src/reg_dumper/.gitignore | 2
src/reg_dumper/Makefile.am | 16
src/reg_dumper/idle.c | 177 +++++++++
src/reg_dumper/stepping.c | 137 +++++++
src/sil164/Makefile.am | 3
src/sil164/sil164.c | 2
src/tfp410/Makefile.am | 3
src/tfp410/tfp410.c | 2
41 files changed, 1738 insertions(+), 649 deletions(-)
New commits:
commit 31654f52b084ebb32f69854dfb1c342c9da07928
Merge: a03aca1... 02c0ffb...
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Tue Mar 11 14:37:41 2008 +0800
Merge branch 'master' into xvmc
Conflicts:
man/intel.man
src/i830_driver.c
diff --cc man/intel.man
index c048f01,e5736e5..b9b64b9
--- a/man/intel.man
+++ b/man/intel.man
@@@ -176,10 -176,12 +176,17 @@@ Default: "EXA"
Enable printing of additional debugging information about modesetting to
the server log.
.TP
+ .BI "Option \*qForceEnablePipeA\*q \*q" boolean \*q
+ Force the driver to leave pipe A enabled. May be necessary in configurations
+ where the BIOS accesses pipe registers during display hotswitch or lid close,
+ causing a crash. If you find that your platform needs this option, please file
+ a bug against xf86-video-intel at http://bugs.freedesktop.org which includes
+ the output of 'lspci -v' and 'lspci -vn'.
++.TP
+.BI "Option \*qXvMC\*q \*q" boolean \*q
+Enable XvMC driver. Current support MPEG2 MC on 915/945 and G33 series.
+User should provide absolute path to libIntelXvMC.so in XvMCConfig file.
+Default: Enabled.
.SH OUTPUT CONFIGURATION
On 830M and better chipsets, the driver supports runtime configuration of
diff --cc src/i830_driver.c
index 1b0d07a,854e377..41362d9
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@@ -301,9 -298,7 +303,10 @@@ typedef enum
OPTION_INTELTEXPOOL,
#endif
OPTION_TRIPLEBUFFER,
- OPTION_FORCEENABLEPIPEA
++ OPTION_FORCEENABLEPIPEA,
+#ifdef INTEL_XVMC
+ OPTION_XVMC,
+#endif
} I830Opts;
static OptionInfoRec I830Options[] = {
@@@ -326,9 -321,7 +329,10 @@@
{OPTION_INTELTEXPOOL,"Legacy3D", OPTV_BOOLEAN, {0}, FALSE},
#endif
{OPTION_TRIPLEBUFFER, "TripleBuffer", OPTV_BOOLEAN, {0}, FALSE},
+ {OPTION_FORCEENABLEPIPEA, "ForceEnablePipeA", OPTV_BOOLEAN, {0}, FALSE},
+#ifdef INTEL_XVMC
+ {OPTION_XVMC, "XvMC", OPTV_BOOLEAN, {0}, TRUE},
+#endif
{-1, NULL, OPTV_NONE, {0}, FALSE}
};
/* *INDENT-ON* */
commit 02c0ffb1d8112a6fb03f9c8eae9ec1a1fca123ef
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Mon Mar 10 11:51:37 2008 -0700
Add pipe A force enable quirk for Dell Latitude D500
Fixes #14888.
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index c7d32cd..6720221 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -249,6 +249,8 @@ static i830_quirk i830_quirk_list[] = {
/* HP Compaq 6730s has no TV output */
{ PCI_CHIP_IGD_GM, 0x103c, 0x30e8, quirk_ignore_tv },
+ /* Dell Latitude D500 needs pipe A force quirk */
+ { PCI_CHIP_I855_GM, 0x1028, 0x0152, quirk_pipea_force },
/* Dell Inspiron 510m needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1028, 0x0164, quirk_pipea_force },
commit a1cd37f94cb8efbde84ba0a46839fb8735dd3595
Author: Dave Airlie <airlied at clockmaker.usersys.redhat.com>
Date: Mon Mar 10 14:43:24 2008 +1000
quirk: add DVO ivch quirk
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 2486e41..c7d32cd 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -238,6 +238,9 @@ static i830_quirk i830_quirk_list[] = {
/* Toshiba i830M laptop (fix bug 11148) */
{ PCI_CHIP_I830_M, 0x1179, 0xff00, quirk_ivch_dvob },
+ /* Motion Computing M1200 reported on irc */
+ { PCI_CHIP_I830_M, 0x14c0, 0x0012, quirk_ivch_dvob },
+
/* Samsung Q35 has no TV output */
{ PCI_CHIP_I945_GM, 0x144d, 0xc504, quirk_ignore_tv },
/* Samsung Q45 has no TV output */
commit f2b9f387af7f618ad083b1ec8bee513ff2157d06
Author: Matthieu Herrb <matthieu.herrb at laas.fr>
Date: Sat Mar 8 23:36:56 2008 +0100
Makefile.am: nuke RCS Id
diff --git a/man/Makefile.am b/man/Makefile.am
index b5510e8..7432d5a 100644
--- a/man/Makefile.am
+++ b/man/Makefile.am
@@ -1,4 +1,3 @@
-# $Id$
#
# Copyright 2005 Sun Microsystems, Inc. All rights reserved.
#
commit bf6d59ee98127ac6447848c4202c54d861a510d4
Author: Eric Anholt <eric at anholt.net>
Date: Fri Mar 7 14:26:22 2008 -0800
Avoid setting reserved bits in SDVOx on everything 965-class.
This will likely fix SDVO outputs on G35 hardware.
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index c7cbfac..d0c65f2 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -727,7 +727,7 @@ i830_sdvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
}
/* Set the SDVO control regs. */
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
+ if (IS_I965G(pI830)) {
sdvox = SDVO_BORDER_ENABLE;
} else {
sdvox = INREG(dev_priv->output_device);
commit 5915c75422c5277d530e7f8ecbdfe94654706efd
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Fri Mar 7 13:18:09 2008 -0800
Enable hardware overlay on 965
Based on Maxim Levitsky's patch for the same. Many thanks to Maxim for
discovering that this features still works in recent hardware!
diff --git a/src/common.h b/src/common.h
index c0af1ad..09f28f8 100644
--- a/src/common.h
+++ b/src/common.h
@@ -440,7 +440,7 @@ extern int I810_DEBUG;
#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
/* mark chipsets for using gfx VM offset for overlay */
-#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810))
+#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* chipsets require graphics mem for hardware status page */
#define HWS_NEED_GFX(pI810) (IS_G33CLASS(pI810) || IS_IGD_GM(pI810))
diff --git a/src/i830_memory.c b/src/i830_memory.c
index ad34f19..e9097ec 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1044,15 +1044,13 @@ i830_allocate_overlay(ScrnInfoPtr pScrn)
if (!OVERLAY_NOPHYSICAL(pI830))
flags |= NEED_PHYSICAL_ADDR;
- if (!IS_I965G(pI830)) {
- pI830->overlay_regs = i830_allocate_memory(pScrn, "overlay registers",
- OVERLAY_SIZE, GTT_PAGE_SIZE,
- flags);
- if (pI830->overlay_regs == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Failed to allocate Overlay register space.\n");
- /* This failure isn't fatal. */
- }
+ pI830->overlay_regs = i830_allocate_memory(pScrn, "overlay registers",
+ OVERLAY_SIZE, GTT_PAGE_SIZE,
+ flags);
+ if (pI830->overlay_regs == NULL) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Failed to allocate Overlay register space.\n");
+ /* This failure isn't fatal. */
}
return TRUE;
diff --git a/src/i830_video.c b/src/i830_video.c
index 79e0574..bf260e4 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -352,7 +352,7 @@ i830_overlay_switch_to_crtc (ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
int pipeconf_reg = intel_crtc->pipe == 0 ? PIPEACONF : PIPEBCONF;
- if (INREG(pipeconf_reg) & PIPEACONF_DOUBLE_WIDE)
+ if (!IS_I965G(pI830) && (INREG(pipeconf_reg) & PIPEACONF_DOUBLE_WIDE))
pPriv->overlayOK = FALSE;
else
pPriv->overlayOK = TRUE;
@@ -580,8 +580,7 @@ I830InitVideo(ScreenPtr pScreen)
}
/* Set up overlay video if we can do it at this depth. */
- if (!IS_I965G(pI830) && pScrn->bitsPerPixel != 8 &&
- pI830->overlay_regs != NULL)
+ if (pScrn->bitsPerPixel != 8 && pI830->overlay_regs != NULL)
{
overlayAdaptor = I830SetupImageVideoOverlay(pScreen);
if (overlayAdaptor != NULL) {
@@ -2563,10 +2562,6 @@ I830VideoBlockHandler(int i, pointer blockData, pointer pTimeout,
if (pI830->adaptor == NULL)
return;
- /* No overlay scaler on the 965. */
- if (IS_I965G(pI830))
- return;
-
pPriv = GET_PORT_PRIVATE(pScrn);
if (pPriv->videoStatus & TIMER_MASK) {
@@ -2846,10 +2841,6 @@ i830_crtc_dpms_video(xf86CrtcPtr crtc, Bool on)
if (pI830->adaptor == NULL)
return;
- /* No overlay scaler on the 965. */
- if (IS_I965G(pI830))
- return;
-
pPriv = GET_PORT_PRIVATE(pScrn);
if (crtc != pPriv->current_crtc)
commit 13ae79b415d944891cfdc2cd2d5397fec36a4e8e
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 7 08:04:37 2008 +1000
fixup pciaccess version detect
diff --git a/configure.ac b/configure.ac
index 9e7c5b9..da44018 100644
--- a/configure.ac
+++ b/configure.ac
@@ -115,9 +115,9 @@ AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
CFLAGS="$save_CFLAGS"
if test x$XSERVER_LIBPCIACCESS = xyes; then
- PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.10.0])
+ PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.10])
else
- PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.10.0],
+ PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.10],
have_libpciaccess=yes,
have_libpciaccess=no)
fi
commit be08b61540e1edbb7673f0b6add0f1e32b136b3c
Author: Jesse Barnes <jbarnes at jbarnes-t61.(none)>
Date: Thu Mar 6 13:55:13 2008 -0800
Implement new get_property feature for backlight control
This should keep the backlight value reported by xrandr --prop & xbacklight
consistent with changes by other software in the system (like the hotkey driver
or kernel backlight driver).
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index ef8fa4a..8359e39 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -851,6 +851,35 @@ i830_lvds_set_property(xf86OutputPtr output, Atom property,
}
#endif /* RANDR_12_INTERFACE */
+#ifdef RANDR_13_INTERFACE
+static Bool
+i830_lvds_get_property(xf86OutputPtr output, Atom property)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
+ I830OutputPrivatePtr intel_output = output->driver_private;
+ struct i830_lvds_priv *dev_priv = intel_output->dev_priv;
+ int ret;
+
+ /*
+ * Only need to update properties that might change out from under
+ * us. The others will be cached by the randr core code.
+ */
+ if (property == backlight_atom) {
+ int val;
+ val = dev_priv->get_backlight(output);
+ dev_priv->backlight_duty_cycle = val;
+ ret = RRChangeOutputProperty(output->randr_output, backlight_atom,
+ XA_INTEGER, 32, PropModeReplace, 1, &val,
+ FALSE, TRUE);
+ if (ret != Success)
+ return FALSE;
+ }
+
+ return TRUE;
+}
+#endif /* RANDR_13_INTERFACE */
+
static const xf86OutputFuncsRec i830_lvds_output_funcs = {
.create_resources = i830_lvds_create_resources,
.dpms = i830_lvds_dpms,
@@ -866,6 +895,9 @@ static const xf86OutputFuncsRec i830_lvds_output_funcs = {
#ifdef RANDR_12_INTERFACE
.set_property = i830_lvds_set_property,
#endif
+#ifdef RANDR_13_INTERFACE
+ .get_property = i830_lvds_get_property,
+#endif
.destroy = i830_lvds_destroy
};
commit 502e41f6dff91393cfeaf08c9ba312781d1b7267
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Mar 6 19:32:29 2008 +0800
remove extra dri checking
And directRenderingDisabled already has config check result.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 2ba69b6..854e377 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2663,11 +2663,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
}
#ifdef XF86DRI
- /* Check for appropriate bpp and module support to initialize DRI. */
- if (!I830CheckDRIAvailable(pScrn)) {
- pI830->directRenderingDisabled = TRUE;
- }
-
/* If DRI hasn't been explicitly disabled, try to initialize it.
* It will be used by the memory allocator.
*/
commit ea58d66cf778c0477c30e5bfe3142b64e8b971d5
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Mar 6 19:31:33 2008 +0800
No ring, no sync
diff --git a/src/i830_accel.c b/src/i830_accel.c
index 7501c2b..fdc713b 100644
--- a/src/i830_accel.c
+++ b/src/i830_accel.c
@@ -173,6 +173,9 @@ I830Sync(ScrnInfoPtr pScrn)
if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
ErrorF("I830Sync\n");
+ if (pI830->noAccel)
+ return;
+
#ifdef XF86DRI
/* VT switching tries to do this.
*/
commit c823fb00a20f523f50a2779c36aa1c014ba01535
Author: Jesse Barnes <jesse.barnes at intel.com>
Date: Thu Mar 6 19:29:22 2008 +0800
Pull chipset detection out of PreInit into its own function
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 9b671a2..2ba69b6 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1036,6 +1036,211 @@ i830SetHotkeyControl(ScrnInfoPtr pScrn, int mode)
pI830->writeControl(pI830, GRX, 0x18, gr18);
}
+static Bool
+i830_detect_chipset(ScrnInfoPtr pScrn)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ MessageType from = X_PROBED;
+ const char *chipname;
+ uint32_t capid;
+ int fb_bar, mmio_bar;
+
+ switch (DEVICE_ID(pI830->PciInfo)) {
+ case PCI_CHIP_I830_M:
+ chipname = "830M";
+ break;
+ case PCI_CHIP_845_G:
+ chipname = "845G";
+ break;
+ case PCI_CHIP_I855_GM:
+ /* Check capid register to find the chipset variant */
+#if XSERVER_LIBPCIACCESS
+ pci_device_cfg_read_u32 (pI830->PciInfo, &capid, I85X_CAPID);
+#else
+ capid = pciReadLong (pI830->PciTag, I85X_CAPID);
+#endif
+ pI830->variant = (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
+ switch (pI830->variant) {
+ case I855_GM:
+ chipname = "855GM";
+ break;
+ case I855_GME:
+ chipname = "855GME";
+ break;
+ case I852_GM:
+ chipname = "852GM";
+ break;
+ case I852_GME:
+ chipname = "852GME";
+ break;
+ default:
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Unknown 852GM/855GM variant: 0x%x)\n", pI830->variant);
+ chipname = "852GM/855GM (unknown variant)";
+ break;
+ }
+ break;
+ case PCI_CHIP_I865_G:
+ chipname = "865G";
+ break;
+ case PCI_CHIP_I915_G:
+ chipname = "915G";
+ break;
+ case PCI_CHIP_E7221_G:
+ chipname = "E7221 (i915)";
+ break;
+ case PCI_CHIP_I915_GM:
+ chipname = "915GM";
+ break;
+ case PCI_CHIP_I945_G:
+ chipname = "945G";
+ break;
+ case PCI_CHIP_I945_GM:
+ chipname = "945GM";
+ break;
+ case PCI_CHIP_I945_GME:
+ chipname = "945GME";
+ break;
+ case PCI_CHIP_I965_G:
+ chipname = "965G";
+ break;
+ case PCI_CHIP_G35_G:
+ chipname = "G35";
+ break;
+ case PCI_CHIP_I965_Q:
+ chipname = "965Q";
+ break;
+ case PCI_CHIP_I946_GZ:
+ chipname = "946GZ";
+ break;
+ case PCI_CHIP_I965_GM:
+ chipname = "965GM";
+ break;
+ case PCI_CHIP_I965_GME:
+ chipname = "965GME/GLE";
+ break;
+ case PCI_CHIP_G33_G:
+ chipname = "G33";
+ break;
+ case PCI_CHIP_Q35_G:
+ chipname = "Q35";
+ break;
+ case PCI_CHIP_Q33_G:
+ chipname = "Q33";
+ break;
+ case PCI_CHIP_IGD_GM:
+ chipname = "Intel Integrated Graphics Device";
+ break;
+ default:
+ chipname = "unknown chipset";
+ break;
+ }
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Integrated Graphics Chipset: Intel(R) %s\n", chipname);
+
+ /* Set the Chipset and ChipRev, allowing config file entries to override. */
+ if (pI830->pEnt->device->chipset && *pI830->pEnt->device->chipset) {
+ pScrn->chipset = pI830->pEnt->device->chipset;
+ from = X_CONFIG;
+ } else if (pI830->pEnt->device->chipID >= 0) {
+ pScrn->chipset = (char *)xf86TokenToString(I830Chipsets,
+ pI830->pEnt->device->chipID);
+ from = X_CONFIG;
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipID override: 0x%04X\n",
+ pI830->pEnt->device->chipID);
+ DEVICE_ID(pI830->PciInfo) = pI830->pEnt->device->chipID;
+ } else {
+ from = X_PROBED;
+ pScrn->chipset = (char *)xf86TokenToString(I830Chipsets,
+ DEVICE_ID(pI830->PciInfo));
+ }
+
+ if (pI830->pEnt->device->chipRev >= 0) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipRev override: %d\n",
+ pI830->pEnt->device->chipRev);
+ }
+
+ xf86DrvMsg(pScrn->scrnIndex, from, "Chipset: \"%s\"\n",
+ (pScrn->chipset != NULL) ? pScrn->chipset : "Unknown i8xx");
+
+ /* Now that we know the chipset, figure out the resource base addrs */
+ if (IS_I9XX(pI830)) {
+ fb_bar = 2;
+ mmio_bar = 0;
+ } else {
+ fb_bar = 0;
+ mmio_bar = 1;
+ }
+
+ if (pI830->pEnt->device->MemBase != 0) {
+ pI830->LinearAddr = pI830->pEnt->device->MemBase;
+ from = X_CONFIG;
+ } else {
+ pI830->LinearAddr = I810_MEMBASE (pI830->PciInfo, fb_bar);
+ if (pI830->LinearAddr == 0) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "No valid FB address in PCI config space\n");
+ PreInitCleanup(pScrn);
+ return FALSE;
+ }
+ }
+
+ xf86DrvMsg(pScrn->scrnIndex, from, "Linear framebuffer at 0x%lX\n",
+ (unsigned long)pI830->LinearAddr);
+
+ if (pI830->pEnt->device->IOBase != 0) {
+ pI830->MMIOAddr = pI830->pEnt->device->IOBase;
+ from = X_CONFIG;
+ } else {
+ pI830->MMIOAddr = I810_MEMBASE (pI830->PciInfo, mmio_bar);
+ if (pI830->MMIOAddr == 0) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "No valid MMIO address in PCI config space\n");
+ PreInitCleanup(pScrn);
+ return FALSE;
+ }
+ }
+
+ xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX\n",
+ (unsigned long)pI830->MMIOAddr);
+
+ /* Now figure out mapsize on 8xx chips */
+ if (IS_I830(pI830) || IS_845G(pI830)) {
+#if XSERVER_LIBPCIACCESS
+ uint16_t gmch_ctrl;
+ struct pci_device *bridge;
+
+ bridge = intel_host_bridge ();
+ pci_device_cfg_read_u16 (bridge, &gmch_ctrl, I830_GMCH_CTRL);
+#else
+ PCITAG bridge;
+ CARD16 gmch_ctrl;
+
+ bridge = pciTag(0, 0, 0); /* This is always the host bridge */
+ gmch_ctrl = pciReadWord(bridge, I830_GMCH_CTRL);
+#endif
+ if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
+ pI830->FbMapSize = 0x8000000;
+ } else {
+ pI830->FbMapSize = 0x4000000; /* 64MB - has this been tested ?? */
+ }
+ } else {
+ if (IS_I9XX(pI830)) {
+#if XSERVER_LIBPCIACCESS
+ pI830->FbMapSize = pI830->PciInfo->regions[fb_bar].size;
+#else
+ pI830->FbMapSize = 1UL << pciGetBaseSize(pI830->PciTag, 2, TRUE,
+ NULL);
+#endif
+ } else {
+ /* 128MB aperture for later i8xx series. */
+ pI830->FbMapSize = 0x8000000;
+ }
+ }
+
+ return TRUE;
+}
+
/**
* This is called per zaphod head (so usually just once) to do initialization
* before the Screen is created.
@@ -1057,11 +1262,8 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
int i;
char *s;
pointer pVBEModule = NULL;
- const char *chipname;
int num_pipe;
int max_width, max_height;
- uint32_t capid;
- int fb_bar, mmio_bar;
if (pScrn->numEntities != 1)
return FALSE;
@@ -1201,166 +1403,8 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
/* We have to use PIO to probe, because we haven't mapped yet. */
I830SetPIOAccess(pI830);
- switch (DEVICE_ID(pI830->PciInfo)) {
- case PCI_CHIP_I830_M:
- chipname = "830M";
- break;
- case PCI_CHIP_845_G:
- chipname = "845G";
- break;
- case PCI_CHIP_I855_GM:
- /* Check capid register to find the chipset variant */
-#if XSERVER_LIBPCIACCESS
- pci_device_cfg_read_u32 (pI830->PciInfo, &capid, I85X_CAPID);
-#else
- capid = pciReadLong (pI830->PciTag, I85X_CAPID);
-#endif
- pI830->variant = (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
- switch (pI830->variant) {
- case I855_GM:
- chipname = "855GM";
- break;
- case I855_GME:
- chipname = "855GME";
- break;
- case I852_GM:
- chipname = "852GM";
- break;
- case I852_GME:
- chipname = "852GME";
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Unknown 852GM/855GM variant: 0x%x)\n", pI830->variant);
- chipname = "852GM/855GM (unknown variant)";
- break;
- }
- break;
- case PCI_CHIP_I865_G:
- chipname = "865G";
- break;
- case PCI_CHIP_I915_G:
- chipname = "915G";
- break;
- case PCI_CHIP_E7221_G:
- chipname = "E7221 (i915)";
- break;
- case PCI_CHIP_I915_GM:
- chipname = "915GM";
- break;
- case PCI_CHIP_I945_G:
- chipname = "945G";
- break;
- case PCI_CHIP_I945_GM:
- chipname = "945GM";
- break;
- case PCI_CHIP_I945_GME:
- chipname = "945GME";
- break;
- case PCI_CHIP_I965_G:
- chipname = "965G";
- break;
- case PCI_CHIP_G35_G:
- chipname = "G35";
- break;
- case PCI_CHIP_I965_Q:
- chipname = "965Q";
- break;
- case PCI_CHIP_I946_GZ:
- chipname = "946GZ";
- break;
- case PCI_CHIP_I965_GM:
- chipname = "965GM";
- break;
- case PCI_CHIP_I965_GME:
- chipname = "965GME/GLE";
- break;
- case PCI_CHIP_G33_G:
- chipname = "G33";
- break;
- case PCI_CHIP_Q35_G:
- chipname = "Q35";
- break;
- case PCI_CHIP_Q33_G:
- chipname = "Q33";
- break;
- case PCI_CHIP_IGD_GM:
- chipname = "Intel Integrated Graphics Device";
- break;
- default:
- chipname = "unknown chipset";
- break;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Integrated Graphics Chipset: Intel(R) %s\n", chipname);
-
- /* Set the Chipset and ChipRev, allowing config file entries to override. */
- if (pI830->pEnt->device->chipset && *pI830->pEnt->device->chipset) {
- pScrn->chipset = pI830->pEnt->device->chipset;
- from = X_CONFIG;
- } else if (pI830->pEnt->device->chipID >= 0) {
- pScrn->chipset = (char *)xf86TokenToString(I830Chipsets,
- pI830->pEnt->device->chipID);
- from = X_CONFIG;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipID override: 0x%04X\n",
- pI830->pEnt->device->chipID);
- DEVICE_ID(pI830->PciInfo) = pI830->pEnt->device->chipID;
- } else {
- from = X_PROBED;
- pScrn->chipset = (char *)xf86TokenToString(I830Chipsets,
- DEVICE_ID(pI830->PciInfo));
- }
-
- if (pI830->pEnt->device->chipRev >= 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipRev override: %d\n",
- pI830->pEnt->device->chipRev);
- }
-
- xf86DrvMsg(pScrn->scrnIndex, from, "Chipset: \"%s\"\n",
- (pScrn->chipset != NULL) ? pScrn->chipset : "Unknown i8xx");
-
- if (IS_I9XX(pI830))
- {
- fb_bar = 2;
- mmio_bar = 0;
- }
- else
- {
- fb_bar = 0;
- mmio_bar = 1;
- }
-
- if (pI830->pEnt->device->MemBase != 0) {
- pI830->LinearAddr = pI830->pEnt->device->MemBase;
- from = X_CONFIG;
- } else {
- pI830->LinearAddr = I810_MEMBASE (pI830->PciInfo, fb_bar);
- if (pI830->LinearAddr == 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "No valid FB address in PCI config space\n");
- PreInitCleanup(pScrn);
- return FALSE;
- }
- }
-
- xf86DrvMsg(pScrn->scrnIndex, from, "Linear framebuffer at 0x%lX\n",
- (unsigned long)pI830->LinearAddr);
-
- if (pI830->pEnt->device->IOBase != 0) {
- pI830->MMIOAddr = pI830->pEnt->device->IOBase;
- from = X_CONFIG;
- } else {
- pI830->MMIOAddr = I810_MEMBASE (pI830->PciInfo, mmio_bar);
- if (pI830->MMIOAddr == 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "No valid MMIO address in PCI config space\n");
- PreInitCleanup(pScrn);
- return FALSE;
- }
- }
-
- xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX\n",
- (unsigned long)pI830->MMIOAddr);
+ if (!i830_detect_chipset(pScrn))
+ return FALSE;
/* check quirks */
i830_fixup_devices(pScrn);
@@ -1380,39 +1424,6 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
}
xf86CrtcSetSizeRange (pScrn, 320, 200, max_width, max_height);
- if (IS_I830(pI830) || IS_845G(pI830)) {
-#if XSERVER_LIBPCIACCESS
- uint16_t gmch_ctrl;
- struct pci_device *bridge;
-
- bridge = intel_host_bridge ();
- pci_device_cfg_read_u16 (bridge, &gmch_ctrl, I830_GMCH_CTRL);
-#else
- PCITAG bridge;
- CARD16 gmch_ctrl;
-
- bridge = pciTag(0, 0, 0); /* This is always the host bridge */
- gmch_ctrl = pciReadWord(bridge, I830_GMCH_CTRL);
-#endif
- if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
- pI830->FbMapSize = 0x8000000;
- } else {
- pI830->FbMapSize = 0x4000000; /* 64MB - has this been tested ?? */
- }
- } else {
- if (IS_I9XX(pI830)) {
-#if XSERVER_LIBPCIACCESS
- pI830->FbMapSize = pI830->PciInfo->regions[fb_bar].size;
-#else
- pI830->FbMapSize = 1UL << pciGetBaseSize(pI830->PciTag, 2, TRUE,
- NULL);
-#endif
- } else {
- /* 128MB aperture for later i8xx series. */
- pI830->FbMapSize = 0x8000000;
- }
- }
-
/* Some of the probing needs MMIO access, so map it here. */
I830MapMMIO(pScrn);
commit 6b16cee0786b636dc849826193b26e898832a73c
Author: Jesse Barnes <jesse.barnes at intel.com>
Date: Thu Mar 6 19:27:42 2008 +0800
Account for FBC LL cache in memory reservation
When we reserve memory (memory that won't be managed by the kernel) make
sure to reserve space for the FBC LL cache as well.
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 1861c64..ad34f19 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -470,7 +470,7 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
ROUND_TO(HWCURSOR_SIZE_ARGB, GTT_PAGE_SIZE));
}
if (pI830->fb_compression)
- mmsize -= MB(6);
+ mmsize -= MB(6) + ROUND_TO_PAGE(FBC_LL_SIZE + FBC_LL_PAD);
/* Can't do TTM on stolen memory */
mmsize -= pI830->stolen_size;
commit 6f04d02471f1cebc76eab637a9a78c4004fd3cc9
Author: Jesse Barnes <jesse.barnes at intel.com>
Date: Thu Mar 6 19:27:07 2008 +0800
Move MTRR fixup to its own routine
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 0aaf9df..9b671a2 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2365,6 +2365,50 @@ I830BlockHandler(int i,
I830VideoBlockHandler(i, blockData, pTimeout, pReadmask);
}
+static void
+i830_fixup_mtrrs(ScrnInfoPtr pScrn)
+{
+#ifdef HAS_MTRR_SUPPORT
+ I830Ptr pI830 = I830PTR(pScrn);
+ int fd;
+ struct mtrr_gentry gentry;
+ struct mtrr_sentry sentry;
+
+ if ( ( fd = open ("/proc/mtrr", O_RDONLY, 0) ) != -1 ) {
+ for (gentry.regnum = 0; ioctl (fd, MTRRIOC_GET_ENTRY, &gentry) == 0;
+ ++gentry.regnum) {
+
+ if (gentry.size < 1) {
+ /* DISABLED */
+ continue;
+ }
+
+ /* Check the MTRR range is one we like and if not - remove it.
+ * The Xserver common layer will then setup the right range
+ * for us.
+ */
+ if (gentry.base == pI830->LinearAddr &&
+ gentry.size < pI830->FbMapSize) {
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Removing bad MTRR range (base 0x%lx, size 0x%x)\n",
+ gentry.base, gentry.size);
+
+ sentry.base = gentry.base;
+ sentry.size = gentry.size;
+ sentry.type = gentry.type;
+
+ if (ioctl (fd, MTRRIOC_DEL_ENTRY, &sentry) == -1) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Failed to remove bad MTRR range\n");
+ }
+ }
+ }
+ close(fd);
+ }
+#endif
+}
+
static Bool
i830_try_memory_allocation(ScrnInfoPtr pScrn)
{
@@ -2707,46 +2751,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
I830UnmapMMIO(pScrn);
-#ifdef HAS_MTRR_SUPPORT
- {
- int fd;
- struct mtrr_gentry gentry;
- struct mtrr_sentry sentry;
-
- if ( ( fd = open ("/proc/mtrr", O_RDONLY, 0) ) != -1 ) {
- for (gentry.regnum = 0; ioctl (fd, MTRRIOC_GET_ENTRY, &gentry) == 0;
- ++gentry.regnum) {
-
- if (gentry.size < 1) {
- /* DISABLED */
- continue;
- }
-
- /* Check the MTRR range is one we like and if not - remove it.
- * The Xserver common layer will then setup the right range
- * for us.
- */
- if (gentry.base == pI830->LinearAddr &&
- gentry.size < pI830->FbMapSize) {
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Removing bad MTRR range (base 0x%lx, size 0x%x)\n",
- gentry.base, gentry.size);
-
- sentry.base = gentry.base;
- sentry.size = gentry.size;
- sentry.type = gentry.type;
-
- if (ioctl (fd, MTRRIOC_DEL_ENTRY, &sentry) == -1) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Failed to remove bad MTRR range\n");
- }
- }
- }
- close(fd);
- }
- }
-#endif
+ i830_fixup_mtrrs(pScrn);
pI830->starting = TRUE;
commit 750beb9232b51223d8e650878ce8dad071f0d0b3
Author: Jesse Barnes <jesse.barnes at intel.com>
Date: Thu Mar 6 19:24:47 2008 +0800
Refactor memory allocation into a separate function
This simplifies the memory allocation code and fixes a number of bugs.
Prior to this change, some flags may have been set after memory
allocation occurred, meaning they had no effect. It should also make
the allocation logic clearer.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 5cd0a34..0aaf9df 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2366,6 +2366,141 @@ I830BlockHandler(int i,
}
static Bool
+i830_try_memory_allocation(ScrnInfoPtr pScrn)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ Bool tiled = pI830->tiling;
+ Bool dri = pI830->directRenderingEnabled;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Attempting memory allocation with %stiled buffers.\n",
+ tiled ? "" : "un");
+
+ if (!i830_allocate_2d_memory(pScrn))
+ goto failed;
+
+ if (dri && !i830_allocate_3d_memory(pScrn))
+ goto failed;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%siled allocation successful.\n",
+ tiled ? "T" : "Unt");
+ return TRUE;
+
+failed:
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%siled allocation failed.\n",
+ tiled ? "T" : "Unt");
+ return FALSE;
+}
+
+/*
+ * Try to allocate memory in several ways:
+ * 1) If direct rendering is enabled, try to allocate enough memory for tiled
+ * surfaces by rounding up the display width to a tileable one.
+ * 2) If that fails or the allocations themselves fail, try again with untiled
+ * allocations (if this works DRI will stay enabled).
+ * 3) And if all else fails, disable DRI and try just 2D allocations.
+ * 4) Give up and fail ScreenInit.
+ */
+static Bool
+i830_memory_init(ScrnInfoPtr pScrn)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ int savedDisplayWidth = pScrn->displayWidth;
+ int i;
+ Bool tiled = FALSE;
+
+ /*
+ * Adjust the display width to allow for front buffer tiling if possible
+ */
+ if (pI830->tiling) {
+ if (IS_I965G(pI830)) {
+ int tile_pixels = 512 / pI830->cpp;
+ pScrn->displayWidth = (pScrn->displayWidth + tile_pixels - 1) &
+ ~(tile_pixels - 1);
+ tiled = TRUE;
+ } else {
+ /* Good pitches to allow tiling. Don't care about pitches < 1024
+ * pixels.
+ */
+ static const int pitches[] = {
+ 1024,
+ 2048,
+ 4096,
+ 8192,
+ 0
+ };
+
+ for (i = 0; pitches[i] != 0; i++) {
+ if (pitches[i] >= pScrn->displayWidth) {
+ pScrn->displayWidth = pitches[i];
+ tiled = TRUE;
+ break;
+ }
+ }
+ }
+ }
+ /* Set up our video memory allocator for the chosen videoRam */
+ if (!i830_allocator_init(pScrn, 0, pScrn->videoRam * KB(1))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Couldn't initialize video memory allocator\n");
+ PreInitCleanup(pScrn);
+ return FALSE;
+ }
+
+ xf86DrvMsg(pScrn->scrnIndex,
+ pI830->pEnt->device->videoRam ? X_CONFIG : X_DEFAULT,
+ "VideoRam: %d KB\n", pScrn->videoRam);
+
+ if (xf86GetOptValInteger(pI830->Options, OPTION_CACHE_LINES,
+ &(pI830->CacheLines))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Requested %d cache lines\n",
+ pI830->CacheLines);
+ } else {
+ pI830->CacheLines = -1;
+ }
+
+ /* Tiled first if we got a good displayWidth */
+ if (tiled) {
+ if (i830_try_memory_allocation(pScrn))
+ return TRUE;
+ else {
+ i830_reset_allocations(pScrn);
+ pI830->tiling = FALSE;
+ }
+ }
+
+ /* If tiling fails we have to disable page flipping & FBC */
+ pScrn->displayWidth = savedDisplayWidth;
+ if (pI830->allowPageFlip)
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Couldn't allocate tiled memory, page flipping "
+ "disabled\n");
+ pI830->allowPageFlip = FALSE;
+ if (pI830->fb_compression)
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Couldn't allocate tiled memory, fb compression "
+ "disabled\n");
+ pI830->fb_compression = FALSE;
+
+ /* Try again, but leave DRI enabled */
+ if (pI830->directRenderingEnabled) {
+ if (i830_try_memory_allocation(pScrn))
+ return TRUE;
+ else {
+ i830_reset_allocations(pScrn);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Couldn't allocate 3D memory, "
+ "disabling DRI.\n");
+ pI830->directRenderingEnabled = FALSE;
+ }
+ }
+
+ if (i830_try_memory_allocation(pScrn))
+ return TRUE;
+
+ return FALSE;
+}
+
+static Bool
I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
{
ScrnInfoPtr pScrn;
@@ -2374,8 +2509,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
VisualPtr visual;
I830Ptr pI8301 = NULL;
unsigned long sys_mem;
- int i, c;
- Bool allocation_done = FALSE;
+ int c;
MessageType from;
#ifdef XF86DRI
xf86CrtcConfigPtr config;
@@ -2490,26 +2624,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
pI830->directRenderingEnabled = FALSE;
#endif
- /* Set up our video memory allocator for the chosen videoRam */
- if (!i830_allocator_init(pScrn, 0, pScrn->videoRam * KB(1))) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Couldn't initialize video memory allocator\n");
- PreInitCleanup(pScrn);
- return FALSE;
- }
-
- xf86DrvMsg(pScrn->scrnIndex,
- pI830->pEnt->device->videoRam ? X_CONFIG : X_DEFAULT,
- "VideoRam: %d KB\n", pScrn->videoRam);
-
- if (xf86GetOptValInteger(pI830->Options, OPTION_CACHE_LINES,
- &(pI830->CacheLines))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Requested %d cache lines\n",
- pI830->CacheLines);
- } else {
- pI830->CacheLines = -1;
- }
-
/* Enable tiling by default */
pI830->tiling = TRUE;
@@ -2567,16 +2681,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
pI830->last_3d = pI8301->last_3d;
}
- /* Need MMIO mapped to do GTT lookups during memory allocation. */
- I830MapMMIO(pScrn);
-
-#if defined(XF86DRI)
- /*
- * If DRI is potentially usable, check if there is enough memory available
- * for it, and if there's also enough to allow tiling to be enabled.
- */
-
-
#ifdef I830_XV
/*
* Set this so that the overlay allocation is factored in when
@@ -2585,103 +2689,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
pI830->XvEnabled = !pI830->XvDisabled;
#endif
- if (pI830->directRenderingEnabled) {
- int savedDisplayWidth = pScrn->displayWidth;
- Bool tiled = FALSE;
-
- if (IS_I965G(pI830)) {
- int tile_pixels = 512 / pI830->cpp;
- pScrn->displayWidth = (pScrn->displayWidth + tile_pixels - 1) &
- ~(tile_pixels - 1);
- tiled = TRUE;
- } else {
- /* Good pitches to allow tiling. Don't care about pitches < 1024
- * pixels.
- */
- static const int pitches[] = {
- 1024,
- 2048,
- 4096,
- 8192,
- 0
- };
-
- for (i = 0; pitches[i] != 0; i++) {
- if (pitches[i] >= pScrn->displayWidth) {
- pScrn->displayWidth = pitches[i];
- tiled = TRUE;
- break;
- }
- }
- }
-
- /* Attempt two rounds of allocation to get 2d and 3d memory to fit:
- *
- * 0: untiled
- * 1: tiled
- */
-
-#define MM_TURNS 2
- for (i = 0; i < MM_TURNS; i++) {
- if (!tiled && i == 0)
- continue;
-
- if (i >= 1) {
- /* For further allocations, disable tiling */
- pI830->tiling = FALSE;
- pScrn->displayWidth = savedDisplayWidth;
- if (pI830->allowPageFlip)
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Couldn't allocate tiled memory, page flipping "
- "disabled\n");
- pI830->allowPageFlip = FALSE;
- if (pI830->fb_compression)
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Couldn't allocate tiled memory, fb compression "
- "disabled\n");
- pI830->fb_compression = FALSE;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Attempting memory allocation with %s buffers.\n",
- (i & 1) ? "untiled" : "tiled");
-
- if (i830_allocate_2d_memory(pScrn) &&
- i830_allocate_3d_memory(pScrn))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Success.\n");
- if (pScrn->displayWidth != savedDisplayWidth) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Increasing the scanline pitch to allow tiling mode "
- "(%d -> %d).\n",
- savedDisplayWidth, pScrn->displayWidth);
- }
- allocation_done = TRUE;
- break;
- }
-
- i830_reset_allocations(pScrn);
- }
-
- if (i == MM_TURNS) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Not enough video memory. Disabling DRI.\n");
- pI830->directRenderingEnabled = FALSE;
- }
- }
-#endif
-
- if (!allocation_done) {
- if (!i830_allocate_2d_memory(pScrn)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Couldn't allocate video memory\n");
- return FALSE;
- }
- allocation_done = TRUE;
- }
-
- I830UnmapMMIO(pScrn);
-
if (!IS_I965G(pI830) && pScrn->displayWidth > 2048) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Cannot support DRI with frame buffer width > 2048.\n");
@@ -2689,6 +2696,17 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
pI830->directRenderingEnabled = FALSE;
}
+ /* Need MMIO mapped to do GTT lookups during memory allocation. */
+ I830MapMMIO(pScrn);
+
+ if (!i830_memory_init(pScrn)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Couldn't allocate video memory\n");
+ return FALSE;
+ }
+
+ I830UnmapMMIO(pScrn);
+
#ifdef HAS_MTRR_SUPPORT
{
int fd;
commit d466b25d09bbe85abe84d9d7714ffb65fafe7593
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Mar 5 13:38:58 2008 +0800
Really print adjusted_mode for mode debug
diff --git a/src/i830_display.c b/src/i830_display.c
index 712a40d..ea6d067 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1276,7 +1276,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
if (!xf86ModesEqual(mode, adjusted_mode)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Adjusted mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
- xf86PrintModeline(pScrn->scrnIndex, mode);
+ xf86PrintModeline(pScrn->scrnIndex, adjusted_mode);
}
i830PrintPll("chosen", &clock);
}
commit d767eabe534be7f7bdcbf00614a8901124ac911f
Author: Hong Liu <hong.liu at intel.com>
Date: Thu Feb 28 13:51:18 2008 +0800
Fix DPLL programming in CRTC mode set
The following patch fixes the display problem on internal development machines.
The code in commit 3c22ed633be2ac96eea7bc533839e956f1f31b84 (Jesse's force pipe
A enable patch) broke DPLL programming. Moving the DPLL set back up in the
function solves the problem.
Fix for internal bug #309.
diff --git a/src/i830_display.c b/src/i830_display.c
index 86992ac..712a40d 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1281,6 +1281,14 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
i830PrintPll("chosen", &clock);
}
+ if (dpll & DPLL_VCO_ENABLE)
+ {
+ OUTREG(fp_reg, fp);
+ OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+ POSTING_READ(dpll_reg);
+ usleep(150);
+ }
+
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
* This is an exception to the general rule that mode_set doesn't turn
* things on.
@@ -1289,14 +1297,6 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
{
CARD32 lvds = INREG(LVDS);
- if (dpll & DPLL_VCO_ENABLE)
- {
- OUTREG(fp_reg, fp);
- OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
- POSTING_READ(dpll_reg);
- usleep(150);
- }
-
lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
/* Set the B0-B3 data pairs corresponding to whether we're going to
* set the DPLLs for dual-channel mode or not.
commit 4936e097028b91f4bdc2d9101dc49f6fe586e718
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Tue Mar 4 08:52:40 2008 -0800
Change FBC idle mode back to default
Use the "immediate idle" mode for FBC. Rather than waiting for the current
compression pass to finish before signalling to the CPU that it's idle, this
mode should stop any current compression pass and tell the CPU that the GPU is
idle right away.
Seems to fix #13326.
diff --git a/src/i830_display.c b/src/i830_display.c
index d5c2dea..86992ac 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -580,7 +580,7 @@ i830_enable_fb_compression_8xx(xf86CrtcPtr crtc)
i830WaitForVblank(pScrn);
OUTREG(FBC_CFB_BASE, pI830->compressed_front_buffer->bus_addr);
OUTREG(FBC_LL_BASE, pI830->compressed_ll_buffer->bus_addr + 6);
- OUTREG(FBC_CONTROL2, FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_FULL |
+ OUTREG(FBC_CONTROL2, FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
FBC_CTL_CPU_FENCE | plane);
OUTREG(FBC_FENCE_OFF, crtc->y);
commit 02a3b80ee8341968dbce5b7cb871b187db5ff805
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Fri Feb 29 11:13:34 2008 +0800
Bug 14591: comment out MI_DISPLAY_POWER_DOWN as for 965GM only
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 7d0c0a0..f589de7 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -623,7 +623,7 @@ static struct i830SnapshotRec {
DEFINEREG(TV_H_CHROMA_59),
DEFINEREG(MI_MODE),
- DEFINEREG(MI_DISPLAY_POWER_DOWN),
+ /* DEFINEREG(MI_DISPLAY_POWER_DOWN), CRL only */
DEFINEREG(MI_ARB_STATE),
DEFINEREG(MI_RDRET_STATE),
DEFINEREG(ECOSKPD),
commit ea7c7d088e0a3c3b7ab2bdd0475aa13379764bf4
Author: Peng Li <peng.li at intel.com>
Date: Wed Feb 27 11:56:55 2008 +0800
HP Compaq 6730s has no TV output
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index e957845..2486e41 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -243,6 +243,9 @@ static i830_quirk i830_quirk_list[] = {
/* Samsung Q45 has no TV output */
{ PCI_CHIP_I965_GM, 0x144d, 0xc510, quirk_ignore_tv },
+ /* HP Compaq 6730s has no TV output */
+ { PCI_CHIP_IGD_GM, 0x103c, 0x30e8, quirk_ignore_tv },
+
/* Dell Inspiron 510m needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1028, 0x0164, quirk_pipea_force },
commit fdc25cb0ca7d479051cee66a032f9ee1b68db98a
Author: Mark Kettenis <mark.kettenis at xs4all.nl>
Date: Tue Feb 26 17:26:50 2008 -0800
Bug #14649: Fix build if pciaccess headers are not with other xorg headers.
We failed to include the pciaccess header flags in our build. Even if the
server was to include those flags for us, it would leave us broken for the
tools-only case, and it's easier to just put the flags everywhere so we avoid
future copy'n'paste mistakes.
diff --git a/src/Makefile.am b/src/Makefile.am
index 118d4b1..1c0133f 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -30,8 +30,8 @@ SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 $(REGDUMPER)
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
-AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ \
- -DI830_XV -DI830_USE_XAA -DI830_USE_EXA
+AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ @PCIACCESS_CFLAGS@ \
+ @XMODES_CFLAGS@ -DI830_XV -DI830_USE_XAA -DI830_USE_EXA
intel_drv_la_LTLIBRARIES = intel_drv.la
intel_drv_la_LDFLAGS = -module -avoid-version
diff --git a/src/bios_reader/Makefile.am b/src/bios_reader/Makefile.am
index 76ad15f..c4da957 100644
--- a/src/bios_reader/Makefile.am
+++ b/src/bios_reader/Makefile.am
@@ -1,4 +1,4 @@
-AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @XMODES_CFLAGS@
+AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @XMODES_CFLAGS@ @PCIACCESS_CFLAGS@
noinst_PROGRAMS = bios_reader $(BIOS_DUMPER)
@@ -7,7 +7,6 @@ BIOS_DUMPER = bios_dumper
bios_dumper_SOURCES = bios_dumper.c
-bios_dumper_CFLAGS = $(PCIACCESS_CFLAGS)
bios_dumper_LDADD = $(PCIACCESS_LIBS)
endif
diff --git a/src/ch7017/Makefile.am b/src/ch7017/Makefile.am
index 71c5085..fef4d37 100644
--- a/src/ch7017/Makefile.am
+++ b/src/ch7017/Makefile.am
@@ -3,7 +3,8 @@
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
-AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@
+AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
+ @PCIACCESS_CFLAGS@
ch7017_la_LTLIBRARIES = ch7017.la
ch7017_la_LDFLAGS = -module -avoid-version
diff --git a/src/ch7xxx/Makefile.am b/src/ch7xxx/Makefile.am
index fdf6e9e..9f93611 100644
--- a/src/ch7xxx/Makefile.am
+++ b/src/ch7xxx/Makefile.am
@@ -3,7 +3,8 @@
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
-AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@
+AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
+ @PCIACCESS_CFLAGS@
ch7xxx_la_LTLIBRARIES = ch7xxx.la
ch7xxx_la_LDFLAGS = -module -avoid-version
diff --git a/src/ivch/Makefile.am b/src/ivch/Makefile.am
index 1dc9cb3..8b12b09 100644
--- a/src/ivch/Makefile.am
+++ b/src/ivch/Makefile.am
@@ -3,7 +3,8 @@
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
-AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@
+AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
+ @PCIACCESS_CFLAGS@
ivch_la_LTLIBRARIES = ivch.la
ivch_la_LDFLAGS = -module -avoid-version
diff --git a/src/sil164/Makefile.am b/src/sil164/Makefile.am
index 497ee9f..7b179ab 100644
--- a/src/sil164/Makefile.am
+++ b/src/sil164/Makefile.am
@@ -3,7 +3,8 @@
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
-AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@
+AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
+ @PCIACCESS_CFLAGS@
sil164_la_LTLIBRARIES = sil164.la
sil164_la_LDFLAGS = -module -avoid-version
diff --git a/src/tfp410/Makefile.am b/src/tfp410/Makefile.am
index 89a27d0..0dbc021 100644
--- a/src/tfp410/Makefile.am
+++ b/src/tfp410/Makefile.am
@@ -3,7 +3,8 @@
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
-AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@
+AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
+ @PCIACCESS_CFLAGS@
tfp410_la_LTLIBRARIES = tfp410.la
tfp410_la_LDFLAGS = -module -avoid-version
commit e55d86f654aa9dd4951b441636c8ca4b37786daf
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 12:26:23 2008 -0800
Fix SDVO I2C access on Mac Mini in EFI mode.
The GMBUS was being left in SDVO pin access mode, which blocked our bit-banging
access to those pins. Thanks to Peter Jones for quick debugging turnaround
in getting this fixed.
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 9eeddc9..d5b6805 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -290,6 +290,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define GPIO_DATA_VAL_IN (1 << 12)
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
+/* GMBus registers for hardware-assisted (non-bitbanging) I2C access */
+#define GMBUS0 0x5100
+#define GMBUS1 0x5104
+#define GMBUS2 0x5108
+#define GMBUS3 0x510c
+#define GMBUS4 0x5110
+#define GMBUS5 0x5120
+
/* p317, 319
*/
#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
diff --git a/src/i830_i2c.c b/src/i830_i2c.c
index d80229d..33a75a8 100644
--- a/src/i830_i2c.c
+++ b/src/i830_i2c.c
@@ -346,6 +346,7 @@ Bool
I830I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
{
I2CBusPtr pI2CBus;
+ I830Ptr pI830 = I830PTR(pScrn);
pI2CBus = xf86CreateI2CBusRec();
@@ -379,6 +380,12 @@ I830I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
pI2CBus->AcknTimeout = 40;
pI2CBus->RiseFallTime = 20;
+ /* Disable the GMBUS, which we won't use. If it is left enabled (for
+ * example, by Mac Mini EFI initialization), GPIO access to the pins it
+ * uses gets disabled.
+ */
+ OUTREG(GMBUS0, 0);
+
if (!xf86I2CBusInit(pI2CBus))
return FALSE;
commit 6935c732c351585f31e2094c4201a00e3d5529b3
Author: Julien Cristau <jcristau at debian.org>
Date: Mon Feb 25 14:47:02 2008 +0100
Look for src/{modes,parser} in $srcdir, not in objdir
This makes the detection work in case configure is run from another directory.
diff --git a/configure.ac b/configure.ac
index e707a1a..9e7c5b9 100644
--- a/configure.ac
+++ b/configure.ac
@@ -140,16 +140,16 @@ if test -d "$XSERVER_SOURCE"; then
XSERVER_SOURCE="`cd $XSERVER_SOURCE && pwd`"
;;
esac
- if test -f src/modes/xf86Modes.h; then
+ if test -f $srcdir/src/modes/xf86Modes.h; then
:
else
- ln -sf $XSERVER_SOURCE/hw/xfree86/modes src/modes
+ ln -sf $XSERVER_SOURCE/hw/xfree86/modes $srcdir/src/modes
fi
- if test -f src/parser/xf86Parser.h; then
+ if test -f $srcdir/src/parser/xf86Parser.h; then
:
else
- ln -sf $XSERVER_SOURCE/hw/xfree86/parser src/parser
+ ln -sf $XSERVER_SOURCE/hw/xfree86/parser $srcdir/src/parser
fi
fi
@@ -158,7 +158,7 @@ if test "x$XMODES" = xyes; then
AC_DEFINE(XMODES, 1,[X server has built-in mode code])
XMODES_CFLAGS=
else
- if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then
+ if test -f $srcdir/src/modes/xf86Modes.h -a -f $srcdir/src/parser/xf86Parser.h; then
AC_MSG_NOTICE([X server is missing new mode code, using local copy])
else
AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source])
commit 66cdccb021a4748b2af41e415c36ed58ca808df6
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Mon Feb 25 14:29:09 2008 +0800
Fix overlay rotation
Track current covered crtc rotation in port's private,
and fix overlay rotation transform to be against crtc mode
coordinate.
diff --git a/src/i830_video.c b/src/i830_video.c
index a0e40ad..79e0574 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -364,7 +364,7 @@ i830_overlay_switch_to_crtc (ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
if (i830PipeHasType(crtc, I830_OUTPUT_LVDS))
{
- int vtotal_reg = intel_crtc->pipe ? VTOTAL_A : VTOTAL_B;
+ int vtotal_reg = intel_crtc->pipe == 0 ? VTOTAL_A : VTOTAL_B;
CARD32 size = intel_crtc->pipe ? INREG(PIPEBSRC) : INREG(PIPEASRC);
CARD32 active;
CARD32 hsize, vsize;
@@ -848,6 +848,8 @@ I830SetupImageVideoOverlay(ScreenPtr pScreen)
pPriv->gamma0 = 0x080808;
pPriv->doubleBuffer = 1;
+ pPriv->rotation = RR_Rotate_0;
+
/* gotta uninit this someplace */
REGION_NULL(pScreen, &pPriv->clip);
@@ -953,6 +955,8 @@ I830SetupImageVideoTextured(ScreenPtr pScreen)
pPriv->currentBuf = 0;
pPriv->doubleBuffer = 0;
+ pPriv->rotation = RR_Rotate_0;
+
/* gotta uninit this someplace, XXX: shouldn't be necessary for textured */
REGION_NULL(pScreen, &pPriv->clip);
@@ -1208,7 +1212,7 @@ I830CopyPackedData(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
else
dst = pI830->FbBase + pPriv->YBuf1offset;
- switch (pI830->rotation) {
+ switch (pPriv->rotation) {
case RR_Rotate_0:
w <<= 1;
for (i = 0; i < h; i++) {
@@ -1370,7 +1374,7 @@ I830CopyPlanarData(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
else
dst1 = pI830->FbBase + pPriv->YBuf1offset;
- switch (pI830->rotation) {
+ switch (pPriv->rotation) {
case RR_Rotate_0:
for (i = 0; i < h; i++) {
memcpy(dst1, src1, w);
@@ -1425,7 +1429,7 @@ I830CopyPlanarData(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
dst2 = pI830->FbBase + pPriv->VBuf1offset;
}
- switch (pI830->rotation) {
+ switch (pPriv->rotation) {
case RR_Rotate_0:
for (i = 0; i < h / 2; i++) {
memcpy(dst2, src2, w / 2);
@@ -1481,7 +1485,7 @@ I830CopyPlanarData(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
dst3 = pI830->FbBase + pPriv->UBuf1offset;
}
- switch (pI830->rotation) {
+ switch (pPriv->rotation) {
case RR_Rotate_0:
for (i = 0; i < h / 2; i++) {
memcpy(dst3, src3, w / 2);
@@ -1780,6 +1784,10 @@ i830_display_video(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
return;
switch (crtc->rotation & 0xf) {
+ /* for overlay, we should take it from crtc's screen
+ * coordinate to current crtc's display mode.
+ * yeah, a bit confusing.
+ */
case RR_Rotate_0:
dstBox->x1 -= crtc->x;
dstBox->x2 -= crtc->x;
@@ -1789,10 +1797,10 @@ i830_display_video(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
case RR_Rotate_90:
tmp = dstBox->x1;
dstBox->x1 = dstBox->y1 - crtc->x;
- dstBox->y1 = pScrn->virtualY - tmp - crtc->y;
+ dstBox->y1 = pScrn->virtualX - tmp - crtc->y;
tmp = dstBox->x2;
dstBox->x2 = dstBox->y2 - crtc->x;
- dstBox->y2 = pScrn->virtualY - tmp - crtc->y;
+ dstBox->y2 = pScrn->virtualX - tmp - crtc->y;
tmp = dstBox->y1;
dstBox->y1 = dstBox->y2;
dstBox->y2 = tmp;
@@ -1807,10 +1815,10 @@ i830_display_video(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
break;
case RR_Rotate_270:
tmp = dstBox->x1;
- dstBox->x1 = pScrn->virtualX - dstBox->y1 - crtc->x;
+ dstBox->x1 = pScrn->virtualY - dstBox->y1 - crtc->x;
dstBox->y1 = tmp - crtc->y;
tmp = dstBox->x2;
- dstBox->x2 = pScrn->virtualX - dstBox->y2 - crtc->x;
+ dstBox->x2 = pScrn->virtualY - dstBox->y2 - crtc->x;
dstBox->y2 = tmp - crtc->y;
tmp = dstBox->x1;
dstBox->x1 = dstBox->x2;
@@ -2242,6 +2250,17 @@ I830PutImage(ScrnInfoPtr pScrn,
width, height))
return Success;
+ if (!pPriv->textured) {
+ /* texture video handles rotation differently. */
+ if (crtc)
+ pPriv->rotation = crtc->rotation;
+ else {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Fail to clip video to any crtc!\n");
+ return Success;
+ }
+ }
+
destId = id;
switch (id) {
case FOURCC_YV12:
@@ -2276,7 +2295,7 @@ I830PutImage(ScrnInfoPtr pScrn,
switch (destId) {
case FOURCC_YV12:
case FOURCC_I420:
- if (pI830->rotation & (RR_Rotate_90 | RR_Rotate_270)) {
+ if (pPriv->rotation & (RR_Rotate_90 | RR_Rotate_270)) {
dstPitch = ((height / 2) + pitchAlignMask) & ~pitchAlignMask;
size = dstPitch * width * 3;
} else {
@@ -2287,7 +2306,7 @@ I830PutImage(ScrnInfoPtr pScrn,
case FOURCC_UYVY:
case FOURCC_YUY2:
default:
- if (pI830->rotation & (RR_Rotate_90 | RR_Rotate_270)) {
+ if (pPriv->rotation & (RR_Rotate_90 | RR_Rotate_270)) {
dstPitch = ((height << 1) + pitchAlignMask) & ~pitchAlignMask;
size = dstPitch * width;
} else {
@@ -2337,7 +2356,7 @@ I830PutImage(ScrnInfoPtr pScrn,
/* fixup pointers */
pPriv->YBuf0offset = pPriv->buf->offset;
- if (pI830->rotation & (RR_Rotate_90 | RR_Rotate_270)) {
+ if (pPriv->rotation & (RR_Rotate_90 | RR_Rotate_270)) {
pPriv->UBuf0offset = pPriv->YBuf0offset + (dstPitch * 2 * width);
pPriv->VBuf0offset = pPriv->UBuf0offset + (dstPitch * width / 2);
if(pPriv->doubleBuffer) {
diff --git a/src/i830_video.h b/src/i830_video.h
index e67831d..1768913 100644
--- a/src/i830_video.h
+++ b/src/i830_video.h
@@ -65,6 +65,7 @@ typedef struct {
int oneLineMode;
int scaleRatio;
Bool textured;
+ Rotation rotation; /* should remove I830->rotation later*/
} I830PortPrivRec, *I830PortPrivPtr;
#define GET_PORT_PRIVATE(pScrn) \
commit 975d7833bc844485c7043538336bddcba7f7f90e
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Fri Feb 22 11:41:25 2008 -0800
Add quirk for DVO channel selection
Some machines want DVOA, some DVOB. We can use this quirk to differentiate
them until we come up with a better solution. Patch from Hong Liu.
Fixes #13722.
diff --git a/src/i830.h b/src/i830.h
index 05b0358..132f089 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -840,6 +840,7 @@ extern const int I830CopyROP[16];
#define QUIRK_IGNORE_LVDS 0x00000002
#define QUIRK_IGNORE_MACMINI_LVDS 0x00000004
#define QUIRK_PIPEA_FORCE 0x00000008
+#define QUIRK_IVCH_NEED_DVOB 0x00000010
extern void i830_fixup_devices(ScrnInfoPtr);
#endif /* _I830_H_ */
diff --git a/src/i830_dvo.c b/src/i830_dvo.c
index e7342b0..81d5601 100644
--- a/src/i830_dvo.c
+++ b/src/i830_dvo.c
@@ -83,7 +83,7 @@ struct _I830DVODriver i830_dvo_drivers[] =
.type = I830_OUTPUT_DVO_LVDS,
.modulename = "ivch",
.fntablename = "ivch_methods",
- .dvo_reg = DVOB,
+ .dvo_reg = DVOA,
.address = 0x04, /* Might also be 0x44, 0x84, 0xc4 */
.symbols = ivch_symbols
},
@@ -398,6 +398,7 @@ i830_dvo_get_current_mode (xf86OutputPtr output)
void
i830_dvo_init(ScrnInfoPtr pScrn)
{
+ I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output;
int ret;
int i;
@@ -431,6 +432,11 @@ i830_dvo_init(ScrnInfoPtr pScrn)
ret_ptr = NULL;
drv->vid_rec = LoaderSymbol(drv->fntablename);
+ if (!strcmp(drv->modulename, "ivch") &&
+ pI830->quirk_flag & QUIRK_IVCH_NEED_DVOB) {
+ drv->dvo_reg = DVOB;
+ }
+
/* Allow the I2C driver info to specify the GPIO to be used in
* special cases, but otherwise default to what's defined in the spec.
*/
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 875bf67..e957845 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -198,6 +198,11 @@ static void quirk_lenovo_tv_dmi (I830Ptr pI830)
pI830->quirk_flag |= QUIRK_IGNORE_TV;
}
+static void quirk_ivch_dvob (I830Ptr pI830)
+{
+ pI830->quirk_flag |= QUIRK_IVCH_NEED_DVOB;
+}
+
/* keep this list sorted by OEM, then by chip ID */
static i830_quirk i830_quirk_list[] = {
/* Aopen mini pc */
@@ -230,6 +235,8 @@ static i830_quirk i830_quirk_list[] = {
/* Toshiba Satellite U300 has no TV output */
{ PCI_CHIP_I965_GM, 0x1179, 0xff50, quirk_ignore_tv },
+ /* Toshiba i830M laptop (fix bug 11148) */
+ { PCI_CHIP_I830_M, 0x1179, 0xff00, quirk_ivch_dvob },
/* Samsung Q35 has no TV output */
{ PCI_CHIP_I945_GM, 0x144d, 0xc504, quirk_ignore_tv },
@@ -242,6 +249,9 @@ static i830_quirk i830_quirk_list[] = {
/* ThinkPad X40 needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1014, 0x0557, quirk_pipea_force },
+ /* Sony vaio PCG-r600HFP (fix bug 13722) */
+ { PCI_CHIP_I830_M, 0x104d, 0x8100, quirk_ivch_dvob },
+
{ 0, 0, 0, NULL },
};
commit 33802b6ee3c298bae4d2b6f464ee5cc730a58506
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Thu Feb 21 08:43:34 2008 -0800
Add pipe A force enable quirk for ThinkPad X40
ThinkPad X40s need this quirk or they'll crash frequently.
Fixes #14521.
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 27e013b..875bf67 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -239,6 +239,9 @@ static i830_quirk i830_quirk_list[] = {
/* Dell Inspiron 510m needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1028, 0x0164, quirk_pipea_force },
+ /* ThinkPad X40 needs pipe A force quirk */
+ { PCI_CHIP_I855_GM, 0x1014, 0x0557, quirk_pipea_force },
+
{ 0, 0, 0, NULL },
};
commit 444984a578aae92ff55c06da897ea1d23679e706
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Thu Feb 21 08:37:42 2008 -0800
Remove side effects from VGA debug code
The VGA register dumping code was leaving ARX in data mode rather than index
mode, which could cause problems for later software accessing AR* registers.
Fix it to make sure it's in index mode when we're done.
Fixes #14434.
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 09ec509..7d0c0a0 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -734,6 +734,7 @@ static void i830DumpAR(ScrnInfoPtr pScrn)
}
INREG8(st01);
OUTREG8(0x3c0, orig_arx);
+ INREG8(st01); /* switch back to index mode */
}
void i830DumpRegs (ScrnInfoPtr pScrn)
commit 28049540d8a9f79401fcfeb90784f5a528e7b34f
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Wed Feb 20 13:08:27 2008 -0800
Fix DSP*CNTR restoration
When checking which pipe a given plane was associated with, we weren't properly
masking the pipe selection bits. Fixes #14481 and should allow the driver to
work with vesafb again.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 290236e..5cd0a34 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2120,12 +2120,14 @@ RestoreHWState(ScrnInfoPtr pScrn)
* enabled if pipe A is actually on (otherwise we have a bug in the initial
* state).
*/
- if (pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_A) {
+ if ((pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_MASK) ==
+ DISPPLANE_SEL_PIPE_A) {
OUTREG(DSPACNTR, pI830->saveDSPACNTR);
OUTREG(DSPABASE, INREG(DSPABASE));
i830WaitForVblank(pScrn);
}
- if (pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_A) {
+ if ((pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_MASK) ==
+ DISPPLANE_SEL_PIPE_A) {
OUTREG(DSPBCNTR, pI830->saveDSPBCNTR);
OUTREG(DSPBBASE, INREG(DSPBBASE));
i830WaitForVblank(pScrn);
@@ -2177,12 +2179,14 @@ RestoreHWState(ScrnInfoPtr pScrn)
* Note that pipe B may be disabled, and in that case, the plane
* should also be disabled or we must have had a bad initial state.
*/
- if (pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_B) {
+ if ((pI830->saveDSPACNTR & DISPPLANE_SEL_PIPE_MASK) ==
+ DISPPLANE_SEL_PIPE_B) {
OUTREG(DSPACNTR, pI830->saveDSPACNTR);
OUTREG(DSPABASE, INREG(DSPABASE));
i830WaitForVblank(pScrn);
}
- if (pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_B) {
+ if ((pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_MASK) ==
+ DISPPLANE_SEL_PIPE_B) {
OUTREG(DSPBCNTR, pI830->saveDSPBCNTR);
OUTREG(DSPBBASE, INREG(DSPBBASE));
i830WaitForVblank(pScrn);
commit 293120bfc40a5b828567551954d8312639e73578
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Tue Feb 19 21:13:45 2008 +0800
Don't leak memory if no DMI info is provided by kernel
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index f1a4d00..27e013b 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -71,7 +71,10 @@ static void i830_dmi_store_##field(void) \
{\
FILE *f = NULL;\
f = fopen(DMIID_FILE(field), "r");\
- if (f == NULL) { i830_dmi_data[field] = NULL; return;}\
+ if (f == NULL) {\
+ xfree(i830_dmi_data[field]); i830_dmi_data[field] = NULL;\
+ return;\
+ }\
fread(i830_dmi_data[field], 64, 1, f);\
fclose(f);\
}
@@ -95,7 +98,7 @@ I830_DMI_FIELD_FUNC(chassis_version);
I830_DMI_FIELD_FUNC(chassis_serial);
I830_DMI_FIELD_FUNC(chassis_asset_tag);
-static int i830_dmi_scan(void)
+static void i830_dmi_scan(void)
{
int i;
@@ -103,9 +106,11 @@ static int i830_dmi_scan(void)
i830_dmi_data[i] = xcalloc(64, sizeof(char));
if (!i830_dmi_data[i]) {
int j;
- for (j = 0; j < i; j++)
+ for (j = 0; j < i; j++) {
xfree(i830_dmi_data[j]);
- return -1;
+ i830_dmi_data[i] = NULL;
+ }
+ return;
}
}
@@ -127,8 +132,6 @@ static int i830_dmi_scan(void)
i830_dmi_store_chassis_version();
i830_dmi_store_chassis_serial();
i830_dmi_store_chassis_asset_tag();
-
- return 0;
}
#define DMIID_DUMP(field) \
@@ -243,9 +246,9 @@ void i830_fixup_devices(ScrnInfoPtr scrn)
{
I830Ptr pI830 = I830PTR(scrn);
i830_quirk_ptr p = i830_quirk_list;
- int i, ret;
+ int i;
- ret = i830_dmi_scan();
+ i830_dmi_scan();
if (0)
i830_dmi_dump();
@@ -259,8 +262,7 @@ void i830_fixup_devices(ScrnInfoPtr scrn)
++p;
}
- if (!ret) {
- for (i = 0; i < dmi_data_max; i++)
+ for (i = 0; i < dmi_data_max; i++)
+ if (i830_dmi_data[i])
xfree(i830_dmi_data[i]);
- }
}
commit cdc5cb7c3d24f36a30fb931b43ec6df8294709e2
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Tue Feb 19 08:51:53 2008 +0800
Fix last 8XX clock's p2 value commit
My fault to change Hong's origin patch reversely.
diff --git a/src/i830_display.c b/src/i830_display.c
index 3fe7cda..d5c2dea 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1725,10 +1725,11 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
DPLL_FPA01_P1_POST_DIV_SHIFT);
+ /* if LVDS is dual-channel, p2 = 7 */
if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
- clock.p2 = I8XX_P2_LVDS_SLOW;
+ clock.p2 = 7;
else
- clock.p2 = I8XX_P2_LVDS_FAST;
+ clock.p2 = 14;
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
i8xx_clock(66000, &clock); /* XXX: might not be 66MHz */
commit be0591880f20bdcbae159d5ab47113b6cc6fbffe
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Mon Feb 18 14:35:06 2008 +0800
Fix Lenovo X60 TV quirk
Z61 has same subsys ids with X60, but does have one S-video
TV out. Use DMI info instead to quirk TV on X60, X60s.
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 59c30f3..f1a4d00 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -178,6 +178,23 @@ static void quirk_mac_mini (I830Ptr pI830)
pI830->quirk_flag |= QUIRK_IGNORE_MACMINI_LVDS;
}
+static void quirk_lenovo_tv_dmi (I830Ptr pI830)
+{
+ /* X60, X60s has no TV output.
+ * Z61 has S-video TV output.
+ * And they have same subsys ids...
+ *
+ * http://www-307.ibm.com/pc/support/site.wss/MIGR-45120.html
+ * http://www.thinkwiki.org/wiki/List_of_DMI_IDs
+ */
+ if (!i830_dmi_data[bios_version]) {
+ ErrorF("Failed to load DMI info, X60 TV quirk not applied.\n");
+ return;
+ }
+ if (!strncmp(i830_dmi_data[bios_version], "7B", 2))
+ pI830->quirk_flag |= QUIRK_IGNORE_TV;
+}
+
/* keep this list sorted by OEM, then by chip ID */
static i830_quirk i830_quirk_list[] = {
/* Aopen mini pc */
@@ -196,8 +213,8 @@ static i830_quirk i830_quirk_list[] = {
/* Dell XPS 1330 */
{ PCI_CHIP_I965_GM, 0x1028, 0x0209, quirk_ignore_tv },
- /* Lenovo X60s has no TV output */
- { PCI_CHIP_I945_GM, 0x17aa, 0x201a, quirk_ignore_tv },
+ /* Lenovo Napa TV (use dmi)*/
+ { PCI_CHIP_I945_GM, 0x17aa, SUBSYS_ANY, quirk_lenovo_tv_dmi },
/* Lenovo T61 has no TV output */
{ PCI_CHIP_I965_GM, 0x17aa, 0x20b5, quirk_ignore_tv },
/* Lenovo 3000 v200 */
commit d5e564c5f24b0d9320bc4908693d37e7e6d68bc6
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Mon Feb 18 14:32:32 2008 +0800
Add DMI info for i830 quirks
Linux kernel has CONFIG_DMIID to export dmi info
through sysfs.
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 853a33e..59c30f3 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -32,6 +32,9 @@
#define SUBSYS_ANY (~0)
+#define DMIID_DIR "/sys/class/dmi/id/"
+#define DMIID_FILE(x) (DMIID_DIR # x)
+
typedef struct {
int chipType;
int subsysVendor;
@@ -39,6 +42,122 @@ typedef struct {
void (*hook)(I830Ptr);
} i830_quirk, *i830_quirk_ptr;
+enum i830_dmi_data_t {
+ bios_vendor,
+ bios_version,
+ bios_date,
+ sys_vendor,
+ product_name,
+ product_version,
+ product_serial,
+ product_uuid,
+ board_vendor,
+ board_name,
+ board_version,
+ board_serial,
+ board_asset_tag,
+ chassis_vendor,
+ chassis_type,
+ chassis_version,
+ chassis_serial,
+ chassis_asset_tag,
+ dmi_data_max,
+};
+
+static char *i830_dmi_data[dmi_data_max];
+
+#define I830_DMI_FIELD_FUNC(field) \
+static void i830_dmi_store_##field(void) \
+{\
+ FILE *f = NULL;\
+ f = fopen(DMIID_FILE(field), "r");\
+ if (f == NULL) { i830_dmi_data[field] = NULL; return;}\
+ fread(i830_dmi_data[field], 64, 1, f);\
+ fclose(f);\
+}
+
+I830_DMI_FIELD_FUNC(bios_vendor);
+I830_DMI_FIELD_FUNC(bios_version);
+I830_DMI_FIELD_FUNC(bios_date);
+I830_DMI_FIELD_FUNC(sys_vendor);
+I830_DMI_FIELD_FUNC(product_name);
+I830_DMI_FIELD_FUNC(product_version);
+I830_DMI_FIELD_FUNC(product_serial);
+I830_DMI_FIELD_FUNC(product_uuid);
+I830_DMI_FIELD_FUNC(board_vendor);
+I830_DMI_FIELD_FUNC(board_name);
+I830_DMI_FIELD_FUNC(board_version);
+I830_DMI_FIELD_FUNC(board_serial);
+I830_DMI_FIELD_FUNC(board_asset_tag);
+I830_DMI_FIELD_FUNC(chassis_vendor);
+I830_DMI_FIELD_FUNC(chassis_type);
+I830_DMI_FIELD_FUNC(chassis_version);
+I830_DMI_FIELD_FUNC(chassis_serial);
+I830_DMI_FIELD_FUNC(chassis_asset_tag);
+
+static int i830_dmi_scan(void)
+{
+ int i;
+
+ for (i = 0; i < dmi_data_max; i++) {
+ i830_dmi_data[i] = xcalloc(64, sizeof(char));
+ if (!i830_dmi_data[i]) {
+ int j;
+ for (j = 0; j < i; j++)
+ xfree(i830_dmi_data[j]);
+ return -1;
+ }
+ }
+
+ i830_dmi_store_bios_vendor();
+ i830_dmi_store_bios_version();
+ i830_dmi_store_bios_date();
+ i830_dmi_store_sys_vendor();
+ i830_dmi_store_product_name();
+ i830_dmi_store_product_version();
+ i830_dmi_store_product_serial();
+ i830_dmi_store_product_uuid();
+ i830_dmi_store_board_vendor();
+ i830_dmi_store_board_name();
+ i830_dmi_store_board_version();
+ i830_dmi_store_board_serial();
+ i830_dmi_store_board_asset_tag();
+ i830_dmi_store_chassis_vendor();
+ i830_dmi_store_chassis_type();
+ i830_dmi_store_chassis_version();
+ i830_dmi_store_chassis_serial();
+ i830_dmi_store_chassis_asset_tag();
+
+ return 0;
+}
+
+#define DMIID_DUMP(field) \
+ ErrorF("\t" # field ": %s", i830_dmi_data[field] ?\
+ i830_dmi_data[field] : "unknown")
+
+static void i830_dmi_dump(void)
+{
+ ErrorF("i830_dmi_dump:\n");
+ DMIID_DUMP(bios_vendor);
+ DMIID_DUMP(bios_version);
+ DMIID_DUMP(bios_date);
+ DMIID_DUMP(sys_vendor);
+ DMIID_DUMP(product_name);
+ DMIID_DUMP(product_version);
+ DMIID_DUMP(product_serial);
+ DMIID_DUMP(product_uuid);
+ DMIID_DUMP(board_vendor);
+ DMIID_DUMP(board_name);
+ DMIID_DUMP(board_version);
+ DMIID_DUMP(board_serial);
+ DMIID_DUMP(board_asset_tag);
+ DMIID_DUMP(chassis_vendor);
+ DMIID_DUMP(chassis_type);
+ DMIID_DUMP(chassis_version);
+ DMIID_DUMP(chassis_serial);
+ DMIID_DUMP(chassis_asset_tag);
+}
+
static void quirk_pipea_force (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_PIPEA_FORCE;
@@ -107,6 +226,12 @@ void i830_fixup_devices(ScrnInfoPtr scrn)
{
I830Ptr pI830 = I830PTR(scrn);
i830_quirk_ptr p = i830_quirk_list;
+ int i, ret;
+
+ ret = i830_dmi_scan();
+
+ if (0)
+ i830_dmi_dump();
while (p && p->chipType != 0) {
if (DEVICE_ID(pI830->PciInfo) == p->chipType &&
@@ -116,4 +241,9 @@ void i830_fixup_devices(ScrnInfoPtr scrn)
p->hook(pI830);
++p;
}
+
+ if (!ret) {
+ for (i = 0; i < dmi_data_max; i++)
+ xfree(i830_dmi_data[i]);
+ }
}
commit 4a42b01f5ee5a673716d6959dfe0e693b037eb48
Author: Keith Packard <keithp at keithp.com>
Date: Sat Feb 16 18:16:12 2008 -0800
Decode DSPCLK_GATE, dump PIPE*STAT, MI_MODE, MI_DISPLAY_POWER_DOWN, MI_ARB_STATE, MI_RDRET_STATE, ECOSKPD
diff --git a/src/i810_reg.h b/src/i810_reg.h
index abe5a34..9eeddc9 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -377,7 +377,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define CACHE_MODE_0 0x2120
#define CACHE_MODE_1 0x2124
+#define MI_MODE 0x209c
+#define MI_DISPLAY_POWER_DOWN 0x20e0
#define MI_ARB_STATE 0x20e4
+#define MI_RDRET_STATE 0x20fc
/* Start addresses for each of the primary rings:
*/
@@ -988,6 +991,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define D_STATE 0x6104
#define DSPCLK_GATE_D 0x6200
+# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
@@ -1002,7 +1012,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
-# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 9)
+# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
@@ -2007,6 +2017,32 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PIPEAGCMAXGREEN 0x70014
#define PIPEAGCMAXBLUE 0x70018
#define PIPEASTAT 0x70024
+# define FIFO_UNDERRUN (1 << 31)
+# define CRC_ERROR_ENABLE (1 << 29)
+# define CRC_DONE_ENABLE (1 << 28)
+# define GMBUS_EVENT_ENABLE (1 << 27)
+# define VSYNC_INT_ENABLE (1 << 25)
+# define DLINE_COMPARE_ENABLE (1 << 24)
+# define DPST_EVENT_ENABLE (1 << 23)
+# define LBLC_EVENT_ENABLE (1 << 22)
+# define OFIELD_INT_ENABLE (1 << 21)
+# define EFIELD_INT_ENABLE (1 << 20)
+# define SVBLANK_INT_ENABLE (1 << 18)
+# define VBLANK_INT_ENABLE (1 << 17)
+# define OREG_UPDATE_ENABLE (1 << 16)
+# define CRC_ERROR_INT_STATUS (1 << 13)
+# define CRC_DONE_INT_STATUS (1 << 12)
+# define GMBUS_INT_STATUS (1 << 11)
+# define VSYNC_INT_STATUS (1 << 9)
+# define DLINE_COMPARE_STATUS (1 << 8)
+# define DPST_EVENT_STATUS (1 << 7)
+# define LBLC_EVENT_STATUS (1 << 6)
+# define OFIELD_INT_STATUS (1 << 5)
+# define EFIELD_INT_STATUS (1 << 4)
+# define SVBLANK_INT_STATUS (1 << 2)
+# define VBLANK_INT_STATUS (1 << 1)
+# define OREG_UPDATE_STATUS (1 << 0)
+
#define DSPARB 0x70030
#define DSPFW1 0x70034
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 30c8bfa..09ec509 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -88,6 +88,61 @@ DEBUGSTRING(i830_debug_pipeconf)
return XNFprintf("%s, %s", enabled, bit30);
}
+DEBUGSTRING(i830_debug_pipestat)
+{
+ char *_FIFO_UNDERRUN = val & FIFO_UNDERRUN ? " FIFO_UNDERRUN" : "";
+ char *_CRC_ERROR_ENABLE = val & CRC_ERROR_ENABLE ? " CRC_ERROR_ENABLE" : "";
+ char *_CRC_DONE_ENABLE = val & CRC_DONE_ENABLE ? " CRC_DONE_ENABLE" : "";
+ char *_GMBUS_EVENT_ENABLE = val & GMBUS_EVENT_ENABLE ? " GMBUS_EVENT_ENABLE" : "";
+ char *_VSYNC_INT_ENABLE = val & VSYNC_INT_ENABLE ? " VSYNC_INT_ENABLE" : "";
+ char *_DLINE_COMPARE_ENABLE = val & DLINE_COMPARE_ENABLE ? " DLINE_COMPARE_ENABLE" : "";
+ char *_DPST_EVENT_ENABLE = val & DPST_EVENT_ENABLE ? " DPST_EVENT_ENABLE" : "";
+ char *_LBLC_EVENT_ENABLE = val & LBLC_EVENT_ENABLE ? " LBLC_EVENT_ENABLE" : "";
+ char *_OFIELD_INT_ENABLE = val & OFIELD_INT_ENABLE ? " OFIELD_INT_ENABLE" : "";
+ char *_EFIELD_INT_ENABLE = val & EFIELD_INT_ENABLE ? " EFIELD_INT_ENABLE" : "";
+ char *_SVBLANK_INT_ENABLE = val & SVBLANK_INT_ENABLE ? " SVBLANK_INT_ENABLE" : "";
+ char *_VBLANK_INT_ENABLE = val & VBLANK_INT_ENABLE ? " VBLANK_INT_ENABLE" : "";
+ char *_OREG_UPDATE_ENABLE = val & OREG_UPDATE_ENABLE ? " OREG_UPDATE_ENABLE" : "";
+ char *_CRC_ERROR_INT_STATUS = val & CRC_ERROR_INT_STATUS ? " CRC_ERROR_INT_STATUS" : "";
+ char *_CRC_DONE_INT_STATUS = val & CRC_DONE_INT_STATUS ? " CRC_DONE_INT_STATUS" : "";
+ char *_GMBUS_INT_STATUS = val & GMBUS_INT_STATUS ? " GMBUS_INT_STATUS" : "";
+ char *_VSYNC_INT_STATUS = val & VSYNC_INT_STATUS ? " VSYNC_INT_STATUS" : "";
+ char *_DLINE_COMPARE_STATUS = val & DLINE_COMPARE_STATUS ? " DLINE_COMPARE_STATUS" : "";
+ char *_DPST_EVENT_STATUS = val & DPST_EVENT_STATUS ? " DPST_EVENT_STATUS" : "";
+ char *_LBLC_EVENT_STATUS = val & LBLC_EVENT_STATUS ? " LBLC_EVENT_STATUS" : "";
+ char *_OFIELD_INT_STATUS = val & OFIELD_INT_STATUS ? " OFIELD_INT_STATUS" : "";
+ char *_EFIELD_INT_STATUS = val & EFIELD_INT_STATUS ? " EFIELD_INT_STATUS" : "";
+ char *_SVBLANK_INT_STATUS = val & SVBLANK_INT_STATUS ? " SVBLANK_INT_STATUS" : "";
+ char *_VBLANK_INT_STATUS = val & VBLANK_INT_STATUS ? " VBLANK_INT_STATUS" : "";
+ char *_OREG_UPDATE_STATUS = val & OREG_UPDATE_STATUS ? " OREG_UPDATE_STATUS" : "";
+ return XNFprintf("status:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
+ _FIFO_UNDERRUN,
+ _CRC_ERROR_ENABLE,
+ _CRC_DONE_ENABLE,
+ _GMBUS_EVENT_ENABLE,
+ _VSYNC_INT_ENABLE,
+ _DLINE_COMPARE_ENABLE,
+ _DPST_EVENT_ENABLE,
+ _LBLC_EVENT_ENABLE,
+ _OFIELD_INT_ENABLE,
+ _EFIELD_INT_ENABLE,
+ _SVBLANK_INT_ENABLE,
+ _VBLANK_INT_ENABLE,
+ _OREG_UPDATE_ENABLE,
+ _CRC_ERROR_INT_STATUS,
+ _CRC_DONE_INT_STATUS,
+ _GMBUS_INT_STATUS,
+ _VSYNC_INT_STATUS,
+ _DLINE_COMPARE_STATUS,
+ _DPST_EVENT_STATUS,
+ _LBLC_EVENT_STATUS,
+ _OFIELD_INT_STATUS,
+ _EFIELD_INT_STATUS,
+ _SVBLANK_INT_STATUS,
+ _VBLANK_INT_STATUS,
+ _OREG_UPDATE_STATUS);
+}
+
DEBUGSTRING(i830_debug_hvtotal)
{
return XNFprintf("%d active, %d total", (val & 0xffff) + 1,
@@ -340,6 +395,76 @@ DEBUGSTRING(i830_debug_sdvo)
enable, pipe, stall, detected, sdvoextra, gang);
}
+DEBUGSTRING(i830_debug_dspclk_gate_d)
+{
+ char *DPUNIT_B = val & DPUNIT_B_CLOCK_GATE_DISABLE ? " DPUNIT_B" : "";
+ char *VSUNIT = val & VSUNIT_CLOCK_GATE_DISABLE ? " VSUNIT" : "";
+ char *VRHUNIT = val & VRHUNIT_CLOCK_GATE_DISABLE ? " VRHUNIT" : "";
+ char *VRDUNIT = val & VRDUNIT_CLOCK_GATE_DISABLE ? " VRDUNIT" : "";
+ char *AUDUNIT = val & AUDUNIT_CLOCK_GATE_DISABLE ? " AUDUNIT" : "";
+ char *DPUNIT_A = val & DPUNIT_A_CLOCK_GATE_DISABLE ? " DPUNIT_A" : "";
+ char *DPCUNIT = val & DPCUNIT_CLOCK_GATE_DISABLE ? " DPCUNIT" : "";
+ char *TVRUNIT = val & TVRUNIT_CLOCK_GATE_DISABLE ? " TVRUNIT" : "";
+ char *TVCUNIT = val & TVCUNIT_CLOCK_GATE_DISABLE ? " TVCUNIT" : "";
+ char *TVFUNIT = val & TVFUNIT_CLOCK_GATE_DISABLE ? " TVFUNIT" : "";
+ char *TVEUNIT = val & TVEUNIT_CLOCK_GATE_DISABLE ? " TVEUNIT" : "";
+ char *DVSUNIT = val & DVSUNIT_CLOCK_GATE_DISABLE ? " DVSUNIT" : "";
+ char *DSSUNIT = val & DSSUNIT_CLOCK_GATE_DISABLE ? " DSSUNIT" : "";
+ char *DDBUNIT = val & DDBUNIT_CLOCK_GATE_DISABLE ? " DDBUNIT" : "";
+ char *DPRUNIT = val & DPRUNIT_CLOCK_GATE_DISABLE ? " DPRUNIT" : "";
+ char *DPFUNIT = val & DPFUNIT_CLOCK_GATE_DISABLE ? " DPFUNIT" : "";
+ char *DPBMUNIT = val & DPBMUNIT_CLOCK_GATE_DISABLE ? " DPBMUNIT" : "";
+ char *DPLSUNIT = val & DPLSUNIT_CLOCK_GATE_DISABLE ? " DPLSUNIT" : "";
+ char *DPLUNIT = val & DPLUNIT_CLOCK_GATE_DISABLE ? " DPLUNIT" : "";
+ char *DPOUNIT = val & DPOUNIT_CLOCK_GATE_DISABLE ? " DPOUNIT" : "";
+ char *DPBUNIT = val & DPBUNIT_CLOCK_GATE_DISABLE ? " DPBUNIT" : "";
+ char *DCUNIT = val & DCUNIT_CLOCK_GATE_DISABLE ? " DCUNIT" : "";
+ char *DPUNIT = val & DPUNIT_CLOCK_GATE_DISABLE ? " DPUNIT" : "";
+ char *VRUNIT = val & VRUNIT_CLOCK_GATE_DISABLE ? " VRUNIT" : "";
+ char *OVHUNIT = val & OVHUNIT_CLOCK_GATE_DISABLE ? " OVHUNIT" : "";
+ char *DPIOUNIT = val & DPIOUNIT_CLOCK_GATE_DISABLE ? " DPIOUNIT" : "";
+ char *OVFUNIT = val & OVFUNIT_CLOCK_GATE_DISABLE ? " OVFUNIT" : "";
+ char *OVBUNIT = val & OVBUNIT_CLOCK_GATE_DISABLE ? " OVBUNIT" : "";
+ char *OVRUNIT = val & OVRUNIT_CLOCK_GATE_DISABLE ? " OVRUNIT" : "";
+ char *OVCUNIT = val & OVCUNIT_CLOCK_GATE_DISABLE ? " OVCUNIT" : "";
+ char *OVUUNIT = val & OVUUNIT_CLOCK_GATE_DISABLE ? " OVUUNIT" : "";
+ char *OVLUNIT = val & OVLUNIT_CLOCK_GATE_DISABLE ? " OVLUNIT" : "";
+
+ return XNFprintf ("clock gates disabled:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
+ DPUNIT_B,
+ VSUNIT,
+ VRHUNIT,
+ VRDUNIT,
+ AUDUNIT,
+ DPUNIT_A,
+ DPCUNIT,
+ TVRUNIT,
+ TVCUNIT,
+ TVFUNIT,
+ TVEUNIT,
+ DVSUNIT,
+ DSSUNIT,
+ DDBUNIT,
+ DPRUNIT,
+ DPFUNIT,
+ DPBMUNIT,
+ DPLSUNIT,
+ DPLUNIT,
+ DPOUNIT,
+ DPBUNIT,
+ DCUNIT,
+ DPUNIT,
+ VRUNIT,
+ OVHUNIT,
+ DPIOUNIT,
+ OVFUNIT,
+ OVBUNIT,
+ OVRUNIT,
+ OVCUNIT,
+ OVUUNIT,
+ OVLUNIT);
+}
+
#if 0
DEBUGSTRING(i810_debug_fence_new)
{
@@ -370,7 +495,7 @@ static struct i830SnapshotRec {
DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
DEFINEREG(CACHE_MODE_0),
DEFINEREG(D_STATE),
- DEFINEREG(DSPCLK_GATE_D),
+ DEFINEREG2(DSPCLK_GATE_D, i830_debug_dspclk_gate_d),
DEFINEREG(RENCLK_GATE_D1),
DEFINEREG(RENCLK_GATE_D2),
/* DEFINEREG(RAMCLK_GATE_D), CRL only */
@@ -409,6 +534,7 @@ static struct i830SnapshotRec {
DEFINEREG(DSPATILEOFF),
DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
+ DEFINEREG2(PIPEASTAT, i830_debug_pipestat),
DEFINEREG(FBC_CFB_BASE),
DEFINEREG(FBC_LL_BASE),
@@ -441,6 +567,7 @@ static struct i830SnapshotRec {
DEFINEREG(DSPBTILEOFF),
DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
+ DEFINEREG2(PIPEBSTAT, i830_debug_pipestat),
DEFINEREG2(FPB0, i830_debug_fp),
DEFINEREG2(FPB1, i830_debug_fp),
@@ -495,6 +622,11 @@ static struct i830SnapshotRec {
DEFINEREG(TV_H_CHROMA_0),
DEFINEREG(TV_H_CHROMA_59),
+ DEFINEREG(MI_MODE),
+ DEFINEREG(MI_DISPLAY_POWER_DOWN),
+ DEFINEREG(MI_ARB_STATE),
+ DEFINEREG(MI_RDRET_STATE),
+ DEFINEREG(ECOSKPD),
#if 0
DEFINEREG2(FENCE_NEW + 0, i810_debug_fence_new),
DEFINEREG2(FENCE_NEW + 8, i810_debug_fence_new),
commit 663313559873208c00c3d3748b99d837949ecdf2
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Fri Feb 15 13:20:22 2008 +0800
Bug #14440: fix stolen mem size mask on i830M
For i830M stolen mem size mask should always be 0x70.
Use 0xF0 for later chipsets should be ok, so behavior is
identical to kernel agp.
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 2893bc8..abe5a34 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -2146,7 +2146,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define I830_GMCH_MEM_64M 0x1
#define I830_GMCH_MEM_128M 0
-#define I830_GMCH_GMS_MASK 0xF0
+#define I830_GMCH_GMS_MASK 0x70
#define I830_GMCH_GMS_DISABLED 0x00
#define I830_GMCH_GMS_LOCAL 0x10
#define I830_GMCH_GMS_STOLEN_512 0x20
@@ -2157,7 +2157,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
-#define I855_GMCH_GMS_MASK (0x7 << 4)
+#define I855_GMCH_GMS_MASK (0xF << 4)
#define I855_GMCH_GMS_DISABLED 0x00
#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 01418ab..290236e 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -495,7 +495,7 @@ I830DetectMemory(ScrnInfoPtr pScrn)
range = gtt_size + 4;
if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
- switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
+ switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
case I855_GMCH_GMS_STOLEN_1M:
memsize = MB(1) - KB(range);
break;
commit 8c8ca16120927fc2d3cf8bcd5212a4227a280708
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 8 11:34:04 2008 -0800
Add a little program to output the stepping information for several chipsets.
diff --git a/src/reg_dumper/.gitignore b/src/reg_dumper/.gitignore
index 1b38d5c..f72a165 100644
--- a/src/reg_dumper/.gitignore
+++ b/src/reg_dumper/.gitignore
@@ -1 +1,3 @@
+intel_idle
intel_reg_dumper
+intel_stepping
diff --git a/src/reg_dumper/Makefile.am b/src/reg_dumper/Makefile.am
index bba388f..b840b24 100644
--- a/src/reg_dumper/Makefile.am
+++ b/src/reg_dumper/Makefile.am
@@ -1,4 +1,4 @@
-noinst_PROGRAMS = intel_reg_dumper intel_idle
+noinst_PROGRAMS = intel_reg_dumper intel_idle intel_stepping
intel_reg_dumper_SOURCES = \
main.c \
@@ -12,9 +12,12 @@ intel_idle_SOURCES = \
xprintf.c \
../i830_debug.c
-intel_reg_dumper_LDADD = $(PCIACCESS_LIBS)
+intel_stepping_SOURCES = \
+ stepping.c
+intel_reg_dumper_LDADD = $(PCIACCESS_LIBS)
intel_idle_LDADD = $(PCIACCESS_LIBS)
+intel_stepping_LDADD = $(PCIACCESS_LIBS)
AM_CFLAGS = $(PCIACCESS_CFLAGS) $(WARN_CFLAGS) \
-I$(srcdir)/.. -DREG_DUMPER
diff --git a/src/reg_dumper/stepping.c b/src/reg_dumper/stepping.c
new file mode 100644
index 0000000..dd0cb42
--- /dev/null
+++ b/src/reg_dumper/stepping.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright © 2007 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <eric at anholt.net>
+ *
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+#include <pciaccess.h>
+#include <err.h>
+#include "common.h"
+
+int main(int argc, char **argv)
+{
+ struct pci_device *dev, *bridge;
+ int err;
+ uint8_t stepping;
+ char *step_desc = "??";
+
+ err = pci_system_init();
+ if (err != 0) {
+ fprintf(stderr, "Couldn't initialize PCI system: %s\n", strerror(err));
+ exit(1);
+ }
+
+ /* Grab the graphics card */
+ dev = pci_device_find_by_slot(0, 0, 2, 0);
+ if (dev == NULL)
+ errx(1, "Couldn't find graphics card");
+
+ err = pci_device_probe(dev);
+ if (err != 0) {
+ fprintf(stderr, "Couldn't probe graphics card: %s\n", strerror(err));
+ exit(1);
+ }
+
+ if (dev->vendor_id != 0x8086)
+ errx(1, "Graphics card is non-intel");
+
+ bridge = pci_device_find_by_slot(0, 0, 0, 0);
+ if (dev == NULL)
+ errx(1, "Couldn't bridge");
+
+ err = pci_device_cfg_read_u8(bridge, &stepping, 8);
+ if (err != 0) {
+ fprintf(stderr, "Couldn't read revision ID: %s\n", strerror(err));
+ exit(1);
+ }
+
+ switch (dev->device_id) {
+ case PCI_CHIP_I915_G:
+ if (stepping < 0x04)
+ step_desc = "<B1";
+ else if (stepping == 0x04)
+ step_desc = "B1";
+ else if (stepping == 0x0e)
+ step_desc = "C2";
+ else if (stepping > 0x0e)
+ step_desc = ">C2";
+ else
+ step_desc = ">B1 <C2";
+ break;
+ case PCI_CHIP_I915_GM:
+ if (stepping < 0x03)
+ step_desc = "<B1";
+ else if (stepping == 0x03)
+ step_desc = "B1/C0";
+ else if (stepping == 0x04)
+ step_desc = "C1/C2";
+ else
+ step_desc = ">C2";
+ break;
+ case PCI_CHIP_I945_GM:
+ if (stepping < 0x03)
+ step_desc = "<A3";
+ else if (stepping == 0x03)
+ step_desc = "A3";
+ else
+ step_desc = ">A3";
+ break;
+ case PCI_CHIP_I965_G:
+ case PCI_CHIP_I965_Q:
+ if (stepping < 0x02)
+ step_desc = "<C1";
+ else if (stepping == 0x02)
+ step_desc = "C1/C2";
+ else
+ step_desc = ">C2";
+ break;
+ case PCI_CHIP_I965_GM:
+ if (stepping < 0x03)
+ step_desc = "<C0";
+ else if (stepping == 0x03)
+ step_desc = "C0";
+ else
+ step_desc = ">C0";
+ break;
+ case PCI_CHIP_G35_G:
+ if (stepping < 0x03)
+ step_desc = "<E0";
+ else if (stepping == 0x03)
+ step_desc = "E0";
+ else
+ step_desc = ">E0";
+ break;
+ }
+
+ printf("Vendor: 0x%04x, Device: 0x%04x, Revision: 0x%02x (%s)\n",
+ dev->vendor_id,
+ dev->device_id,
+ stepping,
+ step_desc);
+ return 0;
+}
commit f5896dcd1f5a964dce024ab8887ac8a79f7093a1
Author: Jesse Barnes <root at nietzche.virtuousgeek.org>
Date: Thu Feb 7 11:56:28 2008 -0800
Add CACHE_MODE_0 register to dump output
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 196fd23..30c8bfa 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -368,6 +368,7 @@ static struct i830SnapshotRec {
DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp),
DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd),
DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
+ DEFINEREG(CACHE_MODE_0),
DEFINEREG(D_STATE),
DEFINEREG(DSPCLK_GATE_D),
DEFINEREG(RENCLK_GATE_D1),
commit d59eaa8b1e6eeb9775c9d21c7a5fd28f25b2bc3a
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Wed Feb 6 09:35:43 2008 -0800
Only disable FBC if registers are available
The call to disable FBC should only occur if the FBC feature is actually
present or we may end up hanging on a read from a non-existent register.
diff --git a/src/i830_display.c b/src/i830_display.c
index 585b0e7..3fe7cda 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -722,7 +722,8 @@ i830_use_fb_compression(xf86CrtcPtr crtc)
/* Here we disable it to catch one->two pipe enabled configs */
if (count > 1) {
- i830_disable_fb_compression(crtc);
+ if (i830_fb_compression_supported(pI830))
+ i830_disable_fb_compression(crtc);
return FALSE;
}
commit 83a071e2c01eb71462273f25d86d77159ac51114
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Tue Feb 5 17:09:19 2008 -0800
Fix build warnings on 64 bit
Use PRIx32 for printing CARD32 types, and PRIx64 for portably printing uint64_t
types. Requires the addition of a new include, inttypes.h, to work. Hope C99
is ok with everybody...
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 5e9dafa..196fd23 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -25,6 +25,8 @@
*
*/
+#include <inttypes.h>
+
#ifdef REG_DUMPER
#include "reg_dumper/reg_dumper.h"
@@ -804,8 +806,8 @@ i830_dump_ring(ScrnInfoPtr pScrn)
mask = pI830->LpRing->tail_mask;
virt = pI830->LpRing->virtual_start;
- ErrorF ("Ring at virtual 0x%x head 0x%x tail 0x%x count %d\n",
- (unsigned int) virt, head, tail, (((tail + mask + 1) - head) & mask) >> 2);
+ ErrorF ("Ring at virtual %p head 0x%x tail 0x%x count %d\n",
+ virt, head, tail, (((tail + mask + 1) - head) & mask) >> 2);
for (ring = (head - 128) & mask; ring != ((head + 4) & mask);
ring = (ring + 4) & mask)
{
@@ -821,25 +823,25 @@ i830_dump_error_state(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- ErrorF("pgetbl_ctl: 0x%lx pgetbl_err: 0x%lx\n",
- (unsigned long)INREG(PGETBL_CTL), (unsigned long)INREG(PGE_ERR));
+ ErrorF("pgetbl_ctl: 0x%" PRIx32 "getbl_err: 0x%" PRIx32 "\n",
+ INREG(PGETBL_CTL), INREG(PGE_ERR));
- ErrorF("ipeir: %lx iphdr: %lx\n", (unsigned long)INREG(IPEIR),
- (unsigned long)INREG(IPEHR));
+ ErrorF("ipeir: %" PRIx32 " iphdr: %" PRIx32 "\n", INREG(IPEIR),
+ INREG(IPEHR));
- ErrorF("LP ring tail: %lx head: %lx len: %lx start %lx\n",
- (unsigned long)INREG(LP_RING + RING_TAIL),
- (unsigned long)INREG(LP_RING + RING_HEAD) & HEAD_ADDR,
- (unsigned long)INREG(LP_RING + RING_LEN),
- (unsigned long)INREG(LP_RING + RING_START));
+ ErrorF("LP ring tail: %" PRIx32 " head: %" PRIx32 " len: %" PRIx32 " start %" PRIx32 "\n",
+ INREG(LP_RING + RING_TAIL),
+ INREG(LP_RING + RING_HEAD) & HEAD_ADDR,
+ INREG(LP_RING + RING_LEN),
+ INREG(LP_RING + RING_START));
ErrorF("eir: %x esr: %x emr: %x\n",
INREG16(EIR), INREG16(ESR), INREG16(EMR));
ErrorF("instdone: %x instpm: %x\n", INREG16(INST_DONE), INREG8(INST_PM));
- ErrorF("memmode: %lx instps: %lx\n", (unsigned long)INREG(MEMMODE),
- (unsigned long)INREG(INST_PS));
+ ErrorF("memmode: %" PRIx32 " instps: %" PRIx32 "\n", INREG(MEMMODE),
+ INREG(INST_PS));
ErrorF("hwstam: %x ier: %x imr: %x iir: %x\n",
INREG16(HWSTAM), INREG16(IER), INREG16(IMR), INREG16(IIR));
@@ -851,12 +853,12 @@ i965_dump_error_state(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- ErrorF("pgetbl_ctl: 0x%lx pgetbl_err: 0x%lx\n",
+ ErrorF("pgetbl_ctl: 0x%" PRIx32 " pgetbl_err: 0x%" PRIx32 "\n",
INREG(PGETBL_CTL), INREG(PGE_ERR));
- ErrorF("ipeir: %lx iphdr: %lx\n", INREG(IPEIR_I965), INREG(IPEHR_I965));
+ ErrorF("ipeir: %" PRIx32 " iphdr: %" PRIx32 "\n", INREG(IPEIR_I965), INREG(IPEHR_I965));
- ErrorF("LP ring tail: %lx head: %lx len: %lx start %lx\n",
+ ErrorF("LP ring tail: %" PRIx32 " head: %" PRIx32 " len: %" PRIx32 " start %" PRIx32 "\n",
INREG(LP_RING + RING_TAIL),
INREG(LP_RING + RING_HEAD) & HEAD_ADDR,
INREG(LP_RING + RING_LEN), INREG(LP_RING + RING_START));
@@ -868,15 +870,15 @@ i965_dump_error_state(ScrnInfoPtr pScrn)
(int)INREG(INST_DONE_1));
ErrorF("instpm: %x\n", (int)INREG(INST_PM));
- ErrorF("memmode: %lx instps: %lx\n", INREG(MEMMODE), INREG(INST_PS_I965));
+ ErrorF("memmode: %" PRIx32 " instps: %" PRIx32 "\n", INREG(MEMMODE), INREG(INST_PS_I965));
ErrorF("HW Status mask (hwstam): %x\nIRQ enable (ier): %x "
"imr: %x iir: %x\n",
(int)INREG(HWSTAM), (int)INREG(IER), (int)INREG(IMR),
(int)INREG(IIR));
- ErrorF("acthd: %lx dma_fadd_p: %lx\n", INREG(ACTHD), INREG(DMA_FADD_P));
- ErrorF("ecoskpd: %lx excc: %lx\n", INREG(ECOSKPD), INREG(EXCC));
+ ErrorF("acthd: %" PRIx32 " dma_fadd_p: %" PRIx32 "\n", INREG(ACTHD), INREG(DMA_FADD_P));
+ ErrorF("ecoskpd: %" PRIx32 " excc: %" PRIx32 "\n", INREG(ECOSKPD), INREG(EXCC));
ErrorF("cache_mode: %x/%x\n", (int)INREG(CACHE_MODE_0),
(int)INREG(CACHE_MODE_1));
diff --git a/src/i830_memory.c b/src/i830_memory.c
index e24e526..1861c64 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -97,6 +97,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#endif
#include <assert.h>
+#include <inttypes.h>
#include <string.h>
#include <errno.h>
#include <sys/types.h>
@@ -603,8 +604,8 @@ i830_get_stolen_physical(ScrnInfoPtr pScrn, unsigned long offset,
if ((scan - offset) != (scan_physical - physical)) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Non-contiguous GTT entries: (%ld,0x16%llx) vs "
- "(%ld,0x%16llx)\n",
+ "Non-contiguous GTT entries: (%ld,0x16%" PRIx64 ") vs "
+ "(%ld,0x%" PRIx64 ")\n",
scan, scan_physical, offset, physical);
return -1;
}
@@ -952,7 +953,7 @@ i830_describe_allocations(ScrnInfoPtr pScrn, int verbosity, const char *prefix)
if (mem->bus_addr != 0)
snprintf(phys_suffix, sizeof(phys_suffix),
- ", 0x%016llx physical\n", mem->bus_addr);
+ ", 0x%016" PRIx64 " physical\n", mem->bus_addr);
if (mem->tiling == TILE_XMAJOR)
tile_suffix = " X tiled";
else if (mem->tiling == TILE_YMAJOR)
diff --git a/src/i830_video.c b/src/i830_video.c
index 9688aaa..a0e40ad 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -50,6 +50,7 @@
#include "config.h"
#endif
+#include <inttypes.h>
#include <math.h>
#include <string.h>
#include <assert.h>
@@ -462,7 +463,8 @@ i830_overlay_continue(ScrnInfoPtr pScrn, Bool update_filter)
flip_addr = pI830->overlay_regs->bus_addr;
if (update_filter)
flip_addr |= OFC_UPDATE;
- OVERLAY_DEBUG ("overlay_continue cmd 0x%08lx -> 0x%08lx sta 0x%08lx\n",
+ OVERLAY_DEBUG ("overlay_continue cmd 0x%08" PRIx32 " -> 0x%08" PRIx32
+ " sta 0x%08" PRIx32 "\n",
overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
BEGIN_LP_RING(4);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
@@ -502,7 +504,7 @@ i830_overlay_off(ScrnInfoPtr pScrn)
*/
{
overlay->OCMD &= ~OVERLAY_ENABLE;
- OVERLAY_DEBUG ("overlay_off cmd 0x%08lx -> 0x%08lx sta 0x%08lx\n",
+ OVERLAY_DEBUG ("overlay_off cmd 0x%08" PRIx32 " -> 0x%08" PRIx32 " sta 0x%08" PRIx32 "\n",
overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
BEGIN_LP_RING(6);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
@@ -674,7 +676,7 @@ I830ResetVideo(ScrnInfoPtr pScrn)
{
int i;
for (i = 0x30000; i < 0x31000; i += 4)
- ErrorF("0x%x 0x%lx\n", i, INREG(i));
+ ErrorF("0x%x 0x%" PRIx32 "\n", i, INREG(i));
}
#endif
}
@@ -1904,7 +1906,7 @@ i830_display_video(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
overlay->OBUF_1V = pPriv->VBuf1offset;
}
- OVERLAY_DEBUG("pos: 0x%lx, size: 0x%lx\n",
+ OVERLAY_DEBUG("pos: 0x%" PRIx32 ", size: 0x%" PRIx32 "\n",
overlay->DWINPOS, overlay->DWINSZ);
OVERLAY_DEBUG("dst: %d x %d, src: %d x %d\n", drw_w, drw_h, src_w, src_h);
@@ -2066,7 +2068,7 @@ i830_display_video(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
OCMD |= BUFFER1;
overlay->OCMD = OCMD;
- OVERLAY_DEBUG("OCMD is 0x%lx\n", OCMD);
+ OVERLAY_DEBUG("OCMD is 0x%" PRIx32 "\n", OCMD);
/* make sure the overlay is on */
i830_overlay_on (pScrn);
commit abf4b0cafa038e97bd7a6e5ba107b822117b9ccc
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Tue Feb 5 13:30:51 2008 -0800
Only enable FBC if one pipe is active
Some chips can't support FBC if multiple pipes are active. So if more than one
pipe is on or we're going from one->two pipes enabled, make sure FBC is
disabled.
Intended to fix 13418, 13326, 13152.
diff --git a/src/i830_display.c b/src/i830_display.c
index 274a07d..585b0e7 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -529,36 +529,6 @@ i830_display_tiled(xf86CrtcPtr crtc)
return FALSE;
}
-static Bool
-i830_use_fb_compression(xf86CrtcPtr crtc)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- I830Ptr pI830 = I830PTR(pScrn);
- I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
- int plane = (intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB);
-
- if (!pI830->fb_compression)
- return FALSE;
-
- if (!i830_display_tiled(crtc))
- return FALSE;
-
- /* Pre-965 only supports plane A */
- if (!IS_I965GM(pI830) && plane != FBC_CTL_PLANEA)
- return FALSE;
-
- /* Need 15, 16, or 32 (w/alpha) pixel format */
- if (!(pScrn->bitsPerPixel == 16 || /* covers 15 bit mode as well */
- pScrn->bitsPerPixel == 32)) /* mode_set dtrt if fbc is in use */
- return FALSE;
-
- /*
- * No checks for pixel multiply, incl. horizontal, or interlaced modes
- * since they're currently unused.
- */
- return TRUE;
-}
-
/*
* Several restrictions:
* - DSP[AB]CNTR - no line duplication && no pixel multiplier
@@ -734,6 +704,50 @@ i830_disable_fb_compression(xf86CrtcPtr crtc)
i830_disable_fb_compression_8xx(crtc);
}
+static Bool
+i830_use_fb_compression(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ I830Ptr pI830 = I830PTR(pScrn);
+ I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+ int plane = (intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB);
+ int i, count = 0;
+
+ /* Only available on one pipe at a time */
+ for (i = 0; i < xf86_config->num_crtc; i++) {
+ if (xf86_config->crtc[i]->enabled)
+ count++;
+ }
+
+ /* Here we disable it to catch one->two pipe enabled configs */
+ if (count > 1) {
+ i830_disable_fb_compression(crtc);
+ return FALSE;
+ }
+
+ if (!pI830->fb_compression)
+ return FALSE;
+
+ if (!i830_display_tiled(crtc))
+ return FALSE;
+
+ /* Pre-965 only supports plane A */
+ if (!IS_I965GM(pI830) && plane != FBC_CTL_PLANEA)
+ return FALSE;
+
+ /* Need 15, 16, or 32 (w/alpha) pixel format */
+ if (!(pScrn->bitsPerPixel == 16 || /* covers 15 bit mode as well */
+ pScrn->bitsPerPixel == 32)) /* mode_set dtrt if fbc is in use */
+ return FALSE;
+
+ /*
+ * No checks for pixel multiply, incl. horizontal, or interlaced modes
+ * since they're currently unused.
+ */
+ return TRUE;
+}
+
/**
* Sets the power management mode of the pipe and plane.
*
commit f79a585d57c61fbe9af5684a336918e1fe3e8416
Author: liuhong <liuhong at devlinux-hong.sh.intel.com>
Date: Tue Feb 5 11:04:34 2008 +0800
xf86-video-intel: fix ivch using wrong dvo register
We use the wrong DVO output register for ivch which is used for DVO LVDS.
Vbios enables DVOB and driver never touches it, so everything seems
working correctly now.
diff --git a/src/i830_dvo.c b/src/i830_dvo.c
index e6ff6af..e7342b0 100644
--- a/src/i830_dvo.c
+++ b/src/i830_dvo.c
@@ -83,7 +83,7 @@ struct _I830DVODriver i830_dvo_drivers[] =
.type = I830_OUTPUT_DVO_LVDS,
.modulename = "ivch",
.fntablename = "ivch_methods",
- .dvo_reg = DVOA,
+ .dvo_reg = DVOB,
.address = 0x04, /* Might also be 0x44, 0x84, 0xc4 */
.symbols = ivch_symbols
},
commit cabed67b6a0e4dd408eeb8d2083269100a65933c
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Tue Feb 5 11:36:24 2008 -0800
Program FBC fence offset register
Just a partial fix for some of the FBC issues people have been seeing. The
other half is to disable FBC if both pipes are running.
diff --git a/src/i830.h b/src/i830.h
index e55e110..05b0358 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -616,6 +616,7 @@ typedef struct _I830Rec {
CARD32 saveFBC_LL_BASE;
CARD32 saveFBC_CONTROL2;
CARD32 saveFBC_CONTROL;
+ CARD32 saveFBC_FENCE_OFF;
enum last_3d *last_3d;
diff --git a/src/i830_display.c b/src/i830_display.c
index a4916d0..274a07d 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -612,6 +612,7 @@ i830_enable_fb_compression_8xx(xf86CrtcPtr crtc)
OUTREG(FBC_LL_BASE, pI830->compressed_ll_buffer->bus_addr + 6);
OUTREG(FBC_CONTROL2, FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_FULL |
FBC_CTL_CPU_FENCE | plane);
+ OUTREG(FBC_FENCE_OFF, crtc->y);
/* Zero buffers */
memset(pI830->FbBase + pI830->compressed_front_buffer->offset, 0,
diff --git a/src/i830_driver.c b/src/i830_driver.c
index a3c64de..01418ab 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1932,6 +1932,7 @@ SaveHWState(ScrnInfoPtr pScrn)
pI830->saveFBC_LL_BASE = INREG(FBC_LL_BASE);
pI830->saveFBC_CONTROL2 = INREG(FBC_CONTROL2);
pI830->saveFBC_CONTROL = INREG(FBC_CONTROL);
+ pI830->saveFBC_FENCE_OFF = INREG(FBC_FENCE_OFF);
}
/* Save video mode information for native mode-setting. */
@@ -2212,6 +2213,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
if (pI830->fb_compression) {
OUTREG(FBC_CFB_BASE, pI830->saveFBC_CFB_BASE);
OUTREG(FBC_LL_BASE, pI830->saveFBC_LL_BASE);
+ OUTREG(FBC_FENCE_OFF, pI830->saveFBC_FENCE_OFF);
OUTREG(FBC_CONTROL2, pI830->saveFBC_CONTROL2);
OUTREG(FBC_CONTROL, pI830->saveFBC_CONTROL);
}
commit 332587081fb05d284864aabe608dd9988eee3d44
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Tue Feb 5 10:34:55 2008 +0800
Fix last commit on i8xx debug p2 value
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 7fc0726..5e9dafa 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -192,9 +192,9 @@ DEBUGSTRING(i830_debug_dpll)
p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
DPLL_FPA01_P1_POST_DIV_SHIFT);
if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
- p2 = I8XX_P2_LVDS_SLOW;
+ p2 = 7;
else
- p2 = I8XX_P2_LVDS_FAST;
+ p2 = 14;
} else {
mode = "DAC/serial";
commit 2d18a299cf39f2ecf9bd3ba8407f892566b2edcc
Author: Hong Liu <hong.liu at intel.com>
Date: Tue Feb 5 09:10:48 2008 +0800
Fix PLL reference clk debug dump
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 5b70cd9..7fc0726 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -693,6 +693,19 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p1 out of range\n");
break;
}
+
+ switch ((dpll >> 13) & 0x3) {
+ case 0:
+ ref = 96000;
+ break;
+ case 3:
+ ref = 100000;
+ break;
+ default:
+ ref = 0;
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "ref out of range\n");
+ break;
+ }
}
else
{
@@ -730,18 +743,19 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
else
p1 = ((dpll >> 16) & 0x3f) + 2;
}
- }
- switch ((dpll >> 13) & 0x3) {
- case 0:
- ref = 96000;
- break;
- case 3:
- ref = 100000;
- break;
- default:
- ref = 0;
- xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "ref out of range\n");
- break;
+
+ switch ((dpll >> 13) & 0x3) {
+ case 0:
+ ref = 48000;
+ break;
+ case 3:
+ ref = 66000;
+ break;
+ default:
+ ref = 0;
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "ref out of range\n");
+ break;
+ }
}
if (IS_I965G(pI830)) {
phase = (dpll >> 9) & 0xf;
commit 9536515d7717969795edc1b80d6e6a36820dd575
Author: Hong Liu <hong.liu at intel.com>
Date: Tue Feb 5 09:06:14 2008 +0800
Allow non-strict free order for bo_list
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 5dbafee..e24e526 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -274,12 +274,16 @@ i830_free_memory(ScrnInfoPtr pScrn, i830_memory *mem)
I830Ptr pI830 = I830PTR(pScrn);
drmBOUnreference(pI830->drmSubFD, &mem->bo);
- if (pI830->bo_list == mem)
+ if (pI830->bo_list == mem) {
pI830->bo_list = mem->next;
- if (mem->next)
- mem->next->prev = NULL;
- if (mem->prev)
- mem->prev->next = NULL;
+ if (mem->next)
+ mem->next->prev = NULL;
+ } else {
+ if (mem->prev)
+ mem->prev->next = mem->next;
+ if (mem->next)
+ mem->next->prev = mem->prev;
+ }
xfree(mem->name);
xfree(mem);
return;
commit 11de831cb706025c003e98fef6d666d273192bcd
Author: Hong Liu <hong.liu at intel.com>
Date: Tue Feb 5 08:58:44 2008 +0800
Bug 10584: Mac Mini EDID data assigned to TMDS output
EDID data for TMDS output got from crt should be applied
to TMDS output on mac mini.
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 4b04994..c7cbfac 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -1100,8 +1100,10 @@ i830_sdvo_get_modes(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- DisplayModePtr modes;
+ DisplayModePtr modes = NULL;
xf86OutputPtr crt;
+ I830OutputPrivatePtr intel_output;
+ xf86MonPtr edid_mon = NULL;
modes = i830_ddc_get_modes(output);
if (modes != NULL)
@@ -1113,11 +1115,17 @@ i830_sdvo_get_modes(xf86OutputPtr output)
* analog when we fail at finding it the right way.
*/
crt = xf86_config->output[0];
- if (crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
- return crt->funcs->get_modes(crt);
+ intel_output = crt->driver_private;
+ if (intel_output->type == I830_OUTPUT_ANALOG &&
+ crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
+ edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
+ }
+ if (edid_mon) {
+ xf86OutputSetEDID(output, edid_mon);
+ modes = xf86OutputGetEDIDModes(output);
}
- return NULL;
+ return modes;
}
static void
commit 95327571134d8ebb9d936d80b70c2f642393aa9f
Author: Hong Liu <hong.liu at intel.com>
Date: Mon Feb 4 17:14:23 2008 +0800
Bug 10773: fix i8xx pll p2 value in i830_crtc_clock_get()
Also fix debug dump, slightly modified to use macro instead.
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 8f8ef9b..5b70cd9 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -191,7 +191,11 @@ DEBUGSTRING(i830_debug_dpll)
mode = "LVDS";
p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
DPLL_FPA01_P1_POST_DIV_SHIFT);
- p2 = 14;
+ if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+ p2 = I8XX_P2_LVDS_SLOW;
+ else
+ p2 = I8XX_P2_LVDS_FAST;
+
} else {
mode = "DAC/serial";
if (val & PLL_P1_DIVIDE_BY_TWO) {
diff --git a/src/i830_display.c b/src/i830_display.c
index 39f3637..a4916d0 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1708,7 +1708,11 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
if (is_lvds) {
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
DPLL_FPA01_P1_POST_DIV_SHIFT);
- clock.p2 = 14;
+
+ if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+ clock.p2 = I8XX_P2_LVDS_SLOW;
+ else
+ clock.p2 = I8XX_P2_LVDS_FAST;
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
i8xx_clock(66000, &clock); /* XXX: might not be 66MHz */
commit be1b568bc2379856c3eaaed365002512bebc218c
Author: Paulo Cesar Pereira de Andrade <pcpa at mandriva.com>
Date: Thu Jan 31 22:47:18 2008 -0200
Make sure symbols used by other modules are public.
These symbols must be explicitly exported, otherwise if compiled with
hidden symbols, LoaderSymbol (and dlopen) will fail to find them.
diff --git a/src/ch7017/ch7017.c b/src/ch7017/ch7017.c
index 6fc3422..76f9cf7 100644
--- a/src/ch7017/ch7017.c
+++ b/src/ch7017/ch7017.c
@@ -313,7 +313,7 @@ ch7017_restore(I2CDevPtr d)
ch7017_write(priv, CH7017_POWER_MANAGEMENT, priv->save_power_management);
}
-I830I2CVidOutputRec ch7017_methods = {
+_X_EXPORT I830I2CVidOutputRec ch7017_methods = {
.init = ch7017_init,
.detect = ch7017_detect,
.mode_valid = ch7017_mode_valid,
diff --git a/src/ch7xxx/ch7xxx.c b/src/ch7xxx/ch7xxx.c
index da02ad2..51fa78e 100644
--- a/src/ch7xxx/ch7xxx.c
+++ b/src/ch7xxx/ch7xxx.c
@@ -306,7 +306,7 @@ ch7xxx_restore(I2CDevPtr d)
ch7xxx_write(dev_priv, CH7xxx_PM, dev_priv->save_PM);
}
-I830I2CVidOutputRec CH7xxxVidOutput = {
+_X_EXPORT I830I2CVidOutputRec CH7xxxVidOutput = {
.init = ch7xxx_init,
.detect = ch7xxx_detect,
.mode_valid = ch7xxx_mode_valid,
diff --git a/src/ivch/ivch.c b/src/ivch/ivch.c
index eb5dc21..820919f 100644
--- a/src/ivch/ivch.c
+++ b/src/ivch/ivch.c
@@ -358,7 +358,7 @@ ivch_restore(I2CDevPtr d)
}
-I830I2CVidOutputRec ivch_methods = {
+_X_EXPORT I830I2CVidOutputRec ivch_methods = {
.init = ivch_init,
.dpms = ivch_dpms,
.save = ivch_save,
diff --git a/src/sil164/sil164.c b/src/sil164/sil164.c
index 12fe8e2..f7d414a 100644
--- a/src/sil164/sil164.c
+++ b/src/sil164/sil164.c
@@ -237,7 +237,7 @@ sil164_restore(I2CDevPtr d)
}
-I830I2CVidOutputRec SIL164VidOutput = {
+_X_EXPORT I830I2CVidOutputRec SIL164VidOutput = {
.init = sil164_init,
.detect = sil164_detect,
.mode_valid = sil164_mode_valid,
diff --git a/src/tfp410/tfp410.c b/src/tfp410/tfp410.c
index b79fd2a..bb038cd 100644
--- a/src/tfp410/tfp410.c
+++ b/src/tfp410/tfp410.c
@@ -259,7 +259,7 @@ tfp410_restore(I2CDevPtr d)
tfp410WriteByte(tfp, TFP410_CTL_1, tfp->SavedReg.ctl1);
}
-I830I2CVidOutputRec TFP410VidOutput = {
+_X_EXPORT I830I2CVidOutputRec TFP410VidOutput = {
.init = tfp410_init,
.detect = tfp410_detect,
.mode_valid = tfp410_mode_valid,
commit cc1031a834b81aa6f835c282ad86deddabe229a0
Author: Mark Kettenis <mark.kettenis at xs4all.nl>
Date: Thu Jan 31 21:02:48 2008 -0800
Bug #14246: Fix biuld on OpenBSD.
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 06c21ac..5dbafee 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -99,6 +99,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include <assert.h>
#include <string.h>
#include <errno.h>
+#include <sys/types.h>
#include <sys/mman.h>
#include "xf86.h"
commit b1e1c7cd993ab4f1935d750eb8852e74be757e53
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jan 30 23:01:04 2008 -0800
Add detail on different units to intel_idle.
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 7902366..2893bc8 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -351,6 +351,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define IPEIR_I965 0x2064 /* i965 */
#define IPEHR_I965 0x2068 /* i965 */
#define INST_DONE_I965 0x206c
+# define I965_SF_DONE (1 << 23)
+# define I965_SE_DONE (1 << 22)
+# define I965_WM_DONE (1 << 21)
+# define I965_TEXTURE_FETCH_DONE (1 << 14)
+# define I965_SAMPLER_CACHE_DONE (1 << 12)
+# define I965_FILTER_DONE (1 << 11)
+# define I965_PS_DONE (1 << 9)
+# define I965_CC_DONE (1 << 8)
+# define I965_MAP_FILTER_DONE (1 << 7)
+# define I965_MAP_L2_IDLE (1 << 6)
+# define I965_CP_DONE (1 << 1)
+# define I965_RING_0_ENABLE (1 << 0)
#define INST_PS_I965 0x2070
/* Current active ring head address:
diff --git a/src/reg_dumper/idle.c b/src/reg_dumper/idle.c
index ec083fd..0077bf4 100644
--- a/src/reg_dumper/idle.c
+++ b/src/reg_dumper/idle.c
@@ -36,13 +36,52 @@
#include "reg_dumper.h"
#include "../i810_reg.h"
+struct idle_flags {
+ uint32_t instdone_flag;
+ char *name;
+ unsigned int count;
+};
+
+struct idle_flags i965_idle_flags[] = {
+ {I965_SF_DONE, "SF"},
+ {I965_SE_DONE, "SE"},
+ {I965_WM_DONE, "WM"},
+ {I965_TEXTURE_FETCH_DONE, "texture fetch"},
+ {I965_SAMPLER_CACHE_DONE, "sampler cache"},
+ {I965_FILTER_DONE, "filter"},
+ {I965_PS_DONE, "PS"},
+ {I965_CC_DONE, "CC"},
+ {I965_MAP_FILTER_DONE, "map filter"},
+ {I965_MAP_L2_IDLE, "map L2"},
+ {I965_CP_DONE, "CP"},
+ {0, "other"},
+};
+
+/* Fills in the "other" field's idle flags */
+static void
+setup_other_flags(struct idle_flags *idle_flags, int idle_flag_count)
+{
+ uint32_t other_idle_flags;
+ int i;
+
+ other_idle_flags = ~(I965_RING_0_ENABLE);
+ for (i = 0; i < idle_flag_count - 1; i++) {
+ other_idle_flags &= ~idle_flags[i].instdone_flag;
+ }
+ idle_flags[i].instdone_flag = other_idle_flags;
+
+}
+
int main(int argc, char **argv)
{
struct pci_device *dev;
I830Rec i830;
+ I830Ptr pI830 = &i830;
ScrnInfoRec scrn;
int err, mmio_bar;
void *mmio;
+ struct idle_flags *idle_flags;
+ int idle_flag_count;
err = pci_system_init();
if (err != 0) {
@@ -76,7 +115,7 @@ int main(int argc, char **argv)
dev->regions[mmio_bar].size,
PCI_DEV_MAP_FLAG_WRITABLE,
&mmio);
-
+
if (err != 0) {
fprintf(stderr, "Couldn't map MMIO region: %s\n", strerror(err));
exit(1);
@@ -86,23 +125,31 @@ int main(int argc, char **argv)
scrn.scrnIndex = 0;
scrn.pI830 = &i830;
- {
- I830Ptr pI830 = I830PTR((&scrn));
+ /* if (IS_I965) { */
+ idle_flags = i965_idle_flags;
+ idle_flag_count = sizeof(i965_idle_flags) / sizeof(i965_idle_flags[0]);
+
+ setup_other_flags(idle_flags, idle_flag_count);
- CARD32 idle_value = 0xffe5fafe;
+ for (;;) {
+ int i, j;
- for (;;)
- {
- CARD32 busy = 0;
- int i;
+ for (i = 0; i < 100; i++) {
+ uint32_t instdone = INREG(INST_DONE_I965);
- for (i = 0; i < 100; i++) {
- if (INREG (INST_DONE_I965) != idle_value)
- busy++;
- usleep (10000);
+ for (j = 0; j < idle_flag_count; j++) {
+ if ((instdone & idle_flags[j].instdone_flag) == 0)
+ idle_flags[j].count++;
}
- printf ("load: %d\n", busy);
+
+ usleep (10000);
+ }
+
+ for (j = 0; j < idle_flag_count; j++) {
+ printf("%15s: %3d\n", idle_flags[j].name, idle_flags[j].count);
+ idle_flags[j].count = 0;
}
+ printf("\n");
}
return 0;
commit aa3ac79759581b5eb05293a8cbcf89eb5b76712c
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Jan 31 18:26:46 2008 +0800
Don't crash if SW cursor
In case of device option or hw cursor allocation fails.
diff --git a/src/i830_memory.c b/src/i830_memory.c
index d97ca0b..06c21ac 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1946,7 +1946,8 @@ i830_bind_all_memory(ScrnInfoPtr pScrn)
}
#endif
}
- i830_update_cursor_offsets(pScrn);
+ if (!pI830->SWCursor)
+ i830_update_cursor_offsets(pScrn);
return TRUE;
}
commit 2e43bec8731ba1b172f7a0bf867bbb5c1adbda2d
Author: Jesse Barnes <jesse.barnes at intel.com>
Date: Wed Jan 30 18:59:12 2008 +0800
Frame buffer compression support on new chipset
diff --git a/src/i810_reg.h b/src/i810_reg.h
index bed3901..7902366 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -2634,4 +2634,28 @@ typedef enum {
#define FBC_LL_SIZE (1536)
#define FBC_LL_PAD (32)
+/* Framebuffer compression version 2 */
+#define DPFC_CB_BASE 0x3200
+#define DPFC_CONTROL 0x3208
+#define DPFC_CTL_EN (1<<31)
+#define DPFC_CTL_PLANEA (0<<30)
+#define DPFC_CTL_PLANEB (1<<30)
+#define DPFC_CTL_FENCE_EN (1<<29)
+#define DPFC_CTL_LIMIT_1X (0<<6)
+#define DPFC_CTL_LIMIT_2X (1<<6)
+#define DPFC_CTL_LIMIT_4X (2<<6)
+#define DPFC_RECOMP_CTL 0x320c
+#define DPFC_RECOMP_STALL_EN (1<<27)
+#define DPFC_RECOMP_STALL_WM_SHIFT (16)
+#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
+#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
+#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
+#define DPFC_STATUS 0x3210
+#define DPFC_INVAL_SEG_SHIFT (16)
+#define DPFC_INVAL_SEG_MASK (0x07ff0000)
+#define DPFC_COMP_SEG_SHIFT (0)
+#define DPFC_COMP_SEG_MASK (0x000003ff)
+#define DPFC_STATUS2 0x3214
+#define DPFC_FENCE_YOFF 0x3218
+
#endif /* _I810_REG_H */
diff --git a/src/i830_display.c b/src/i830_display.c
index f61d3c4..39f3637 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -571,9 +571,11 @@ i830_use_fb_compression(xf86CrtcPtr crtc)
* - SR display watermarks must be equal between 16bpp and 32bpp?
*
* FIXME: verify above conditions are true
+ *
+ * Enable 8xx style FB compression
*/
static void
-i830_enable_fb_compression(xf86CrtcPtr crtc)
+i830_enable_fb_compression_8xx(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
@@ -629,8 +631,11 @@ i830_enable_fb_compression(xf86CrtcPtr crtc)
'b' : 'a');
}
+/*
+ * Disable 8xx style FB compression
+ */
static void
-i830_disable_fb_compression(xf86CrtcPtr crtc)
+i830_disable_fb_compression_8xx(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
@@ -648,6 +653,86 @@ i830_disable_fb_compression(xf86CrtcPtr crtc)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "fbc disabled on plane %c\n", plane);
}
+static void
+i830_disable_fb_compression2(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
+ uint32_t dpfc_ctl;
+ char plane = (INREG(DPFC_CONTROL) & DPFC_CTL_PLANEB) ? 'b' : 'a';
+
+ /* Disable compression */
+ dpfc_ctl = INREG(DPFC_CONTROL);
+ dpfc_ctl &= ~DPFC_CTL_EN;
+ OUTREG(DPFC_CONTROL, dpfc_ctl);
+ i830WaitForVblank(pScrn);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "fbc2 disabled on plane %c\n", plane);
+}
+
+static void
+i830_enable_fb_compression2(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
+ I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+ int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB);
+ unsigned long stall_watermark = 200, frames = 50;
+
+ if (INREG(DPFC_CONTROL) & DPFC_CTL_EN) {
+ char cur_plane = (INREG(DPFC_CONTROL) & DPFC_CTL_PLANEB) ? 'b' : 'a';
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "fbc2 already enabled on "
+ "plane %c, not enabling on plane %c\n", cur_plane,
+ plane ? 'b' : 'a');
+ return;
+ }
+
+ /* Set it up... */
+ i830_disable_fb_compression2(crtc);
+ OUTREG(DPFC_CB_BASE, pI830->compressed_front_buffer->offset);
+ /* Update i830_memory.c too if compression ratio changes */
+ OUTREG(DPFC_CONTROL, plane | DPFC_CTL_FENCE_EN | DPFC_CTL_LIMIT_4X |
+ pI830->front_buffer->fence_nr);
+ OUTREG(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
+ (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
+ (frames << DPFC_RECOMP_TIMER_COUNT_SHIFT));
+ OUTREG(DPFC_FENCE_YOFF, crtc->y);
+
+ /* Zero buffers */
+ memset(pI830->FbBase + pI830->compressed_front_buffer->offset, 0,
+ pI830->compressed_front_buffer->size);
+
+ /* enable it... */
+ OUTREG(DPFC_CONTROL, INREG(DPFC_CONTROL) | DPFC_CTL_EN);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "fbc2 enabled on plane %c\n", plane ?
+ 'b' : 'a');
+}
+
+static void
+i830_enable_fb_compression(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
+
+ if (IS_IGD_GM(pI830))
+ return i830_enable_fb_compression2(crtc);
+
+ i830_enable_fb_compression_8xx(crtc);
+}
+
+static void
+i830_disable_fb_compression(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
+
+ if (IS_IGD_GM(pI830))
+ return i830_disable_fb_compression2(crtc);
+
+ i830_disable_fb_compression_8xx(crtc);
+}
+
/**
* Sets the power management mode of the pipe and plane.
*
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 07e4010..d97ca0b 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1274,6 +1274,13 @@ i830_allocate_cursor_buffers(ScrnInfoPtr pScrn)
static void i830_setup_fb_compression(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
+ unsigned long compressed_size;
+ unsigned long fb_height;
+
+ if (pScrn->virtualX > pScrn->virtualY)
+ fb_height = pScrn->virtualX;
+ else
+ fb_height = pScrn->virtualY;
/* Only mobile chips since 845 support this feature */
if (!IS_MOBILE(pI830)) {
@@ -1281,11 +1288,12 @@ static void i830_setup_fb_compression(ScrnInfoPtr pScrn)
goto out;
}
- /* Clear out any stale state */
- OUTREG(FBC_CFB_BASE, 0);
- OUTREG(FBC_LL_BASE, 0);
- OUTREG(FBC_CONTROL2, 0);
- OUTREG(FBC_CONTROL, 0);
+ if (IS_IGD_GM(pI830)) {
+ /* Update i830_display.c too if compression ratio changes */
+ compressed_size = fb_height * (pScrn->displayWidth / 4);
+ } else {
+ compressed_size = MB(6);
+ }
/*
* Compressed framebuffer limitations:
@@ -1300,21 +1308,23 @@ static void i830_setup_fb_compression(ScrnInfoPtr pScrn)
*/
pI830->compressed_front_buffer =
i830_allocate_memory(pScrn, "compressed frame buffer",
- MB(6), KB(4), NEED_PHYSICAL_ADDR);
+ compressed_size, KB(4), NEED_PHYSICAL_ADDR);
if (!pI830->compressed_front_buffer) {
pI830->fb_compression = FALSE;
goto out;
}
- pI830->compressed_ll_buffer =
- i830_allocate_memory(pScrn, "compressed ll buffer",
- FBC_LL_SIZE + FBC_LL_PAD, KB(4),
- NEED_PHYSICAL_ADDR);
- if (!pI830->compressed_ll_buffer) {
- i830_free_memory(pScrn, pI830->compressed_front_buffer);
- pI830->fb_compression = FALSE;
- goto out;
+ if (!IS_IGD_GM(pI830)) {
+ pI830->compressed_ll_buffer =
+ i830_allocate_memory(pScrn, "compressed ll buffer",
+ FBC_LL_SIZE + FBC_LL_PAD, KB(4),
+ NEED_PHYSICAL_ADDR);
+ if (!pI830->compressed_ll_buffer) {
+ i830_free_memory(pScrn, pI830->compressed_front_buffer);
+ pI830->fb_compression = FALSE;
+ goto out;
+ }
}
out:
commit bf629466a46c4037ec7b7cc5ee16be947618bd68
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 30 18:55:20 2008 +0800
hardware status page initialization rework
Order hardware status page setup more reasonable after
all memory bound, in case new chipset requires non-stolen
page and that could be bound then.
Also clean up drm irq handler install function, and put
first install in starting stage later than status page setup,
so we won't make device cry for uninitialized status page.
diff --git a/src/i830.h b/src/i830.h
index 9adbaf7..e55e110 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -695,7 +695,9 @@ extern Bool I830DRIFinishScreenInit(ScreenPtr pScreen);
extern void I830DRIUnlock(ScrnInfoPtr pScrn);
extern Bool I830DRILock(ScrnInfoPtr pScrn);
extern Bool I830DRISetVBlankInterrupt (ScrnInfoPtr pScrn, Bool on);
-Bool i830_update_dri_buffers(ScrnInfoPtr pScrn);
+extern Bool i830_update_dri_buffers(ScrnInfoPtr pScrn);
+extern Bool I830DRISetHWS(ScrnInfoPtr pScrn);
+extern Bool I830DRIInstIrqHandler(ScrnInfoPtr pScrn);
#endif
unsigned long intel_get_pixmap_offset(PixmapPtr pPix);
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 3400b38..141b970 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -236,18 +236,18 @@ I830SetParam(ScrnInfoPtr pScrn, int param, int value)
return TRUE;
}
-static Bool
-I830SetHWS(ScrnInfoPtr pScrn, int addr)
+Bool
+I830DRISetHWS(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
drmI830HWS hws;
- hws.addr = addr;
+ hws.addr = pI830->hw_status->offset;
if (drmCommandWrite(pI830->drmSubFD, DRM_I830_HWS_PAGE_ADDR,
&hws, sizeof(drmI830HWS))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "G33 status page initialization Failed\n");
+ "hw status page initialization Failed\n");
return FALSE;
}
return TRUE;
@@ -813,12 +813,6 @@ I830DRIDoMappings(ScreenPtr pScreen)
return FALSE;
}
- if (HWS_NEED_GFX(pI830)) {
- if (!I830SetHWS(pScrn, pI830->hw_status->offset)) {
- DRICloseScreen(pScreen);
- return FALSE;
- }
- }
/* init to zero to be safe */
sarea->front_handle = 0;
sarea->back_handle = 0;
@@ -881,18 +875,12 @@ I830DRIDoMappings(ScreenPtr pScreen)
}
Bool
-I830DRIResume(ScreenPtr pScreen)
+I830DRIInstIrqHandler(ScrnInfoPtr pScrn)
{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
I830DRIPtr pI830DRI = (I830DRIPtr) pI830->pDRIInfo->devPrivate;
- DPRINTF(PFX, "I830DRIResume\n");
-
- I830ResumeDma(pScrn);
-
- {
- pI830DRI->irq = drmGetInterruptFromBusID(pI830->drmSubFD,
+ pI830DRI->irq = drmGetInterruptFromBusID(pI830->drmSubFD,
#if XSERVER_LIBPCIACCESS
((pI830->PciInfo->domain << 8) |
pI830->PciInfo->bus),
@@ -908,19 +896,31 @@ I830DRIResume(ScreenPtr pScreen)
#endif
);
- if (drmCtlInstHandler(pI830->drmSubFD, pI830DRI->irq)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[drm] failure adding irq handler\n");
- pI830DRI->irq = 0;
- return FALSE;
- }
- else
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[drm] dma control initialized, using IRQ %d\n",
- pI830DRI->irq);
- }
+ if (drmCtlInstHandler(pI830->drmSubFD, pI830DRI->irq)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "[drm] failure adding irq handler\n");
+ pI830DRI->irq = 0;
+ return FALSE;
+ } else
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "[drm] dma control initialized, using IRQ %d\n",
+ pI830DRI->irq);
- return FALSE;
+ return TRUE;
+}
+
+Bool
+I830DRIResume(ScreenPtr pScreen)
+{
+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+
+ DPRINTF(PFX, "I830DRIResume\n");
+
+ I830ResumeDma(pScrn);
+
+ I830DRIInstIrqHandler(pScrn);
+
+ return TRUE;
}
void
@@ -976,47 +976,16 @@ I830DestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
Bool
I830DRIFinishScreenInit(ScreenPtr pScreen)
{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
-
DPRINTF(PFX, "I830DRIFinishScreenInit\n");
if (!DRIFinishScreenInit(pScreen))
return FALSE;
- /* Okay now initialize the dma engine */
- {
- I830DRIPtr pI830DRI = (I830DRIPtr) pI830->pDRIInfo->devPrivate;
-
- pI830DRI->irq = drmGetInterruptFromBusID(pI830->drmSubFD,
-#if XSERVER_LIBPCIACCESS
- ((pI830->PciInfo->domain << 8) |
- pI830->PciInfo->bus),
- pI830->PciInfo->dev,
- pI830->PciInfo->func
-#else
- ((pciConfigPtr) pI830->
- PciInfo->thisCard)->busnum,
- ((pciConfigPtr) pI830->
- PciInfo->thisCard)->devnum,
- ((pciConfigPtr) pI830->
- PciInfo->thisCard)->funcnum
-#endif
- );
-
- if (drmCtlInstHandler(pI830->drmSubFD, pI830DRI->irq)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[drm] failure adding irq handler\n");
- pI830DRI->irq = 0;
- DRICloseScreen(pScreen);
- return FALSE;
- }
- else
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[drm] dma control initialized, using IRQ %d\n",
- pI830DRI->irq);
- return TRUE;
- }
+ /* move irq initialize later in EnterVT, as then we
+ * would finish binding possible hw status page, which
+ * requires irq ctrl ioctl not be called that early.
+ */
+ return TRUE;
}
#ifdef DAMAGE
diff --git a/src/i830_driver.c b/src/i830_driver.c
index dffc630..a3c64de 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -3184,6 +3184,22 @@ I830EnterVT(int scrnIndex, int flags)
#ifdef XF86DRI
if (pI830->directRenderingEnabled) {
+ /* HW status is fixed, we need to set it up before any drm
+ * operation which accessing that page, like irq install, etc.
+ */
+ if (pI830->starting) {
+ if (HWS_NEED_GFX(pI830) && !I830DRISetHWS(pScrn)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Fail to setup hardware status page.\n");
+ I830DRICloseScreen(pScrn->pScreen);
+ return FALSE;
+ }
+ if (!I830DRIInstIrqHandler(pScrn)) {
+ I830DRICloseScreen(pScrn->pScreen);
+ return FALSE;
+ }
+ }
+
/* Update buffer offsets in sarea and mappings, since buffer offsets
* may have changed.
*/
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 8a5262f..07e4010 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -468,6 +468,9 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
/* Can't do TTM on stolen memory */
mmsize -= pI830->stolen_size;
+ if (HWS_NEED_GFX(pI830) && IS_IGD_GM(pI830))
+ mmsize -= HWSTATUS_PAGE_SIZE;
+
/* Create the aperture allocation */
pI830->memory_manager =
i830_allocate_aperture(pScrn, "DRI memory manager",
@@ -1630,13 +1633,17 @@ static Bool
i830_allocate_hwstatus(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
+ int flags;
/* The current DRM will leak the HWS mapping if we update the address
* after init (at best), so allocate it fixed for its lifetime
* (i.e. not through buffer objects).
*/
+ flags = NEED_LIFETIME_FIXED;
+ if (IS_IGD_GM(pI830))
+ flags |= NEED_NON_STOLEN;
pI830->hw_status = i830_allocate_memory(pScrn, "HW status",
- HWSTATUS_PAGE_SIZE, GTT_PAGE_SIZE, NEED_LIFETIME_FIXED);
+ HWSTATUS_PAGE_SIZE, GTT_PAGE_SIZE, flags);
if (pI830->hw_status == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Failed to allocate hw status page.\n");
commit 04032dad28baab80131edbe8fe58aade8149bb71
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 30 18:52:32 2008 +0800
Wrap up chipsets which needs graphics address for status page
Also add support on new chipset.
diff --git a/src/common.h b/src/common.h
index 3a11e59..c0af1ad 100644
--- a/src/common.h
+++ b/src/common.h
@@ -441,6 +441,8 @@ extern int I810_DEBUG;
#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810))
+/* chipsets require graphics mem for hardware status page */
+#define HWS_NEED_GFX(pI810) (IS_G33CLASS(pI810) || IS_IGD_GM(pI810))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
diff --git a/src/i830_dri.c b/src/i830_dri.c
index f52a7c3..3400b38 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -813,7 +813,7 @@ I830DRIDoMappings(ScreenPtr pScreen)
return FALSE;
}
- if (IS_G33CLASS(pI830)) {
+ if (HWS_NEED_GFX(pI830)) {
if (!I830SetHWS(pScrn, pI830->hw_status->offset)) {
DRICloseScreen(pScreen);
return FALSE;
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 85b6528..8a5262f 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1635,11 +1635,11 @@ i830_allocate_hwstatus(ScrnInfoPtr pScrn)
* after init (at best), so allocate it fixed for its lifetime
* (i.e. not through buffer objects).
*/
- pI830->hw_status = i830_allocate_memory(pScrn, "G33 hw status",
+ pI830->hw_status = i830_allocate_memory(pScrn, "HW status",
HWSTATUS_PAGE_SIZE, GTT_PAGE_SIZE, NEED_LIFETIME_FIXED);
if (pI830->hw_status == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Failed to allocate hw status page for G33.\n");
+ "Failed to allocate hw status page.\n");
return FALSE;
}
return TRUE;
@@ -1652,7 +1652,7 @@ i830_allocate_3d_memory(ScrnInfoPtr pScrn)
DPRINTF(PFX, "i830_allocate_3d_memory\n");
- if (IS_G33CLASS(pI830)) {
+ if (HWS_NEED_GFX(pI830)) {
if (!i830_allocate_hwstatus(pScrn))
return FALSE;
}
commit b9c3fa79d9fd48c34536f92e6c1c70fe3a619410
Author: Keith Packard <keithp at keithp.com>
Date: Fri Jan 11 15:51:00 2008 -0800
Add intel_idle to measure GPU load ratio.
Samples GPU idle register to detect when the GPU is busy; prints out the
number of busy samples per 100 total samples once per second.
diff --git a/src/reg_dumper/Makefile.am b/src/reg_dumper/Makefile.am
index aee26d0..bba388f 100644
--- a/src/reg_dumper/Makefile.am
+++ b/src/reg_dumper/Makefile.am
@@ -1,4 +1,4 @@
-noinst_PROGRAMS = intel_reg_dumper
+noinst_PROGRAMS = intel_reg_dumper intel_idle
intel_reg_dumper_SOURCES = \
main.c \
@@ -6,7 +6,16 @@ intel_reg_dumper_SOURCES = \
xprintf.c \
../i830_debug.c
+intel_idle_SOURCES = \
+ idle.c \
+ reg_dumper.h \
+ xprintf.c \
+ ../i830_debug.c
+
intel_reg_dumper_LDADD = $(PCIACCESS_LIBS)
-intel_reg_dumper_CFLAGS = $(PCIACCESS_CFLAGS) $(WARN_CFLAGS) \
+intel_idle_LDADD = $(PCIACCESS_LIBS)
+
+AM_CFLAGS = $(PCIACCESS_CFLAGS) $(WARN_CFLAGS) \
-I$(srcdir)/.. -DREG_DUMPER
+
diff --git a/src/reg_dumper/idle.c b/src/reg_dumper/idle.c
new file mode 100644
index 0000000..ec083fd
--- /dev/null
+++ b/src/reg_dumper/idle.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright © 2007 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <eric at anholt.net>
+ *
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+#include <pciaccess.h>
+#include <err.h>
+#include <unistd.h>
+
+#include "reg_dumper.h"
+#include "../i810_reg.h"
+
+int main(int argc, char **argv)
+{
+ struct pci_device *dev;
+ I830Rec i830;
+ ScrnInfoRec scrn;
+ int err, mmio_bar;
+ void *mmio;
+
+ err = pci_system_init();
+ if (err != 0) {
+ fprintf(stderr, "Couldn't initialize PCI system: %s\n", strerror(err));
+ exit(1);
+ }
+
+ /* Grab the graphics card */
+ dev = pci_device_find_by_slot(0, 0, 2, 0);
+ if (dev == NULL)
+ errx(1, "Couldn't find graphics card");
+
+ err = pci_device_probe(dev);
+ if (err != 0) {
+ fprintf(stderr, "Couldn't probe graphics card: %s\n", strerror(err));
+ exit(1);
+ }
+
+ if (dev->vendor_id != 0x8086)
+ errx(1, "Graphics card is non-intel");
+
+ i830.PciInfo = &i830.pci_info_rec;
+ i830.PciInfo->chipType = dev->device_id;
+
+ i830.pci_dev = dev;
+
+ mmio_bar = IS_I9XX((&i830)) ? 0 : 1;
+
+ err = pci_device_map_range (dev,
+ dev->regions[mmio_bar].base_addr,
+ dev->regions[mmio_bar].size,
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ &mmio);
+
+ if (err != 0) {
+ fprintf(stderr, "Couldn't map MMIO region: %s\n", strerror(err));
+ exit(1);
+ }
+ i830.mmio = mmio;
+
+ scrn.scrnIndex = 0;
+ scrn.pI830 = &i830;
+
+ {
+ I830Ptr pI830 = I830PTR((&scrn));
+
+ CARD32 idle_value = 0xffe5fafe;
+
+ for (;;)
+ {
+ CARD32 busy = 0;
+ int i;
+
+ for (i = 0; i < 100; i++) {
+ if (INREG (INST_DONE_I965) != idle_value)
+ busy++;
+ usleep (10000);
+ }
+ printf ("load: %d\n", busy);
+ }
+ }
+
+ return 0;
+}
+
+void xf86DrvMsg(int scrnIndex, int severity, const char *format, ...)
+{
+ va_list va;
+
+ switch (severity) {
+ case X_INFO:
+ printf("(II): ");
+ break;
+ case X_WARNING:
+ printf("(WW): ");
+ break;
+ case X_ERROR:
+ printf("(EE): ");
+ break;
+ }
+
+ va_start(va, format);
+ vprintf(format, va);
+ va_end(va);
+}
commit 5d9e67aec3ce458d22b7febd3819542abb360534
Author: Erik Andren <erik.andren at gmail.com>
Date: Fri Jan 25 11:06:01 2008 +0800
Clevo M720R has no TV-out
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index cb43603..853a33e 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -69,6 +69,9 @@ static i830_quirk i830_quirk_list[] = {
/* Apple Mac mini has no lvds, but macbook pro does */
{ PCI_CHIP_I945_GM, 0x8086, 0x7270, quirk_mac_mini },
+ /* Clevo M720R has no tv output */
+ { PCI_CHIP_I965_GM, 0x1558, 0x0721, quirk_ignore_tv },
+
/* Dell Latitude X1 */
{ PCI_CHIP_I915_GM, 0x1028, 0x01a3, quirk_ignore_tv },
/* Dell XPS 1330 */
commit 6bf53eb48f40ad0c8ea9679ee634447410821b4f
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Fri Jan 25 16:59:13 2008 +0800
Set vtSema before EnterVT
Which was missing in our ScreenInit and initial EnterVT.
This not only causes failure in initial rotation with TTM,
as we won't bind in rotate_mem alloc in this case, and hide
another bug that we call randr12 function in I830LoadPalete
before we call xf86RandR12Init.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 7077456..dffc630 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2934,9 +2934,25 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
pI830->directRenderingEnabled = I830DRIFinishScreenInit(pScreen);
#endif
+ /* Must force it before EnterVT, so we are in control of VT and
+ * later memory should be bound when allocating, e.g rotate_mem */
+ pScrn->vtSema = TRUE;
+
if (!I830EnterVT(scrnIndex, 0))
return FALSE;
+ pI830->BlockHandler = pScreen->BlockHandler;
+ pScreen->BlockHandler = I830BlockHandler;
+
+ pScreen->SaveScreen = xf86SaveScreen;
+ pI830->CloseScreen = pScreen->CloseScreen;
+ pScreen->CloseScreen = I830CloseScreen;
+ pI830->CreateScreenResources = pScreen->CreateScreenResources;
+ pScreen->CreateScreenResources = i830CreateScreenResources;
+
+ if (!xf86CrtcScreenInit (pScreen))
+ return FALSE;
+
DPRINTF(PFX, "assert( if(!miCreateDefColormap(pScreen)) )\n");
if (!miCreateDefColormap(pScreen))
return FALSE;
@@ -2973,18 +2989,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "direct rendering: Not available\n");
#endif
- pI830->BlockHandler = pScreen->BlockHandler;
- pScreen->BlockHandler = I830BlockHandler;
- pScreen->SaveScreen = xf86SaveScreen;
- pI830->CloseScreen = pScreen->CloseScreen;
- pScreen->CloseScreen = I830CloseScreen;
- pI830->CreateScreenResources = pScreen->CreateScreenResources;
- pScreen->CreateScreenResources = i830CreateScreenResources;
-
- if (!xf86CrtcScreenInit (pScreen))
- return FALSE;
-
/* Wrap pointer motion to flip touch screen around */
pI830->PointerMoved = pScrn->PointerMoved;
pScrn->PointerMoved = I830PointerMoved;
commit 94a18fa1f8141837bdab32e545da7a7aed1cc396
Author: Julien Cristau <jcristau at debian.org>
Date: Thu Jan 24 15:24:40 2008 +0100
Don't build reg_dumper if we don't have pciaccess 0.10.0
The pci_device_map_range() function was added in libpciaccess 0.10.0, and
is used by the reg_dumper tool. Don't try to build it if we have an older
libpciaccess.
Also make sure that util-macros >= 1.1.3 is available when running autoconf,
because it's required for the PACKAGE_VERSION_* macros.
diff --git a/configure.ac b/configure.ac
index 334a1f4..e707a1a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -117,7 +117,7 @@ CFLAGS="$save_CFLAGS"
if test x$XSERVER_LIBPCIACCESS = xyes; then
PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.10.0])
else
- PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.5.0],
+ PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.10.0],
have_libpciaccess=yes,
have_libpciaccess=no)
fi
@@ -216,6 +216,8 @@ AC_SUBST([moduledir])
DRIVER_NAME=intel
AC_SUBST([DRIVER_NAME])
+m4_ifndef([XORG_MACROS_VERSION], [AC_FATAL([must install xorg-macros 1.1.3 or later before running autoconf/autogen])])
+XORG_MACROS_VERSION(1.1.3)
XORG_MANPAGE_SECTIONS
XORG_RELEASE_VERSION
commit d341e41c863f1212bf2c6b84782a7e472b6612a1
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Jan 24 10:40:18 2008 +0800
Clear shadow memory after allocation
diff --git a/src/i830_display.c b/src/i830_display.c
index d16871d..f61d3c4 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1342,6 +1342,7 @@ i830_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
"Couldn't allocate shadow memory for rotated CRTC\n");
return NULL;
}
+ memset(pI830->FbBase + intel_crtc->rotate_mem->offset, 0, size);
return pI830->FbBase + intel_crtc->rotate_mem->offset;
}
commit 88a1041c5361964d37107c22d77feaa1b2160656
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Jan 24 10:36:06 2008 +0800
Fix i830 block handler wrap
which was observed in rotation crash with stack overflow.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 32cecff..7077456 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2353,6 +2353,7 @@ I830BlockHandler(int i,
(*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask);
+ pI830->BlockHandler = pScreen->BlockHandler;
pScreen->BlockHandler = I830BlockHandler;
I830VideoBlockHandler(i, blockData, pTimeout, pReadmask);
commit db0a7c569e383436a2725e1e74f35fb426da1196
Author: Andreas Stawinoga <a.stawinoga at gmx.de>
Date: Thu Jan 24 08:51:09 2008 +0800
Samsung Q45 has no TV output
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 8fbdbfe..cb43603 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -91,6 +91,8 @@ static i830_quirk i830_quirk_list[] = {
/* Samsung Q35 has no TV output */
{ PCI_CHIP_I945_GM, 0x144d, 0xc504, quirk_ignore_tv },
+ /* Samsung Q45 has no TV output */
+ { PCI_CHIP_I965_GM, 0x144d, 0xc510, quirk_ignore_tv },
/* Dell Inspiron 510m needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1028, 0x0164, quirk_pipea_force },
commit f54bba7600647c76fe3bd2d0133edc06dbea6a05
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Tue Jan 22 00:48:23 2008 +0800
Add missing i830M and 845G pci ids info
diff --git a/src/common.h b/src/common.h
index 7737194..3a11e59 100644
--- a/src/common.h
+++ b/src/common.h
@@ -298,6 +298,16 @@ extern int I810_DEBUG;
#define PCI_CHIP_I815_BRIDGE 0x1130
#endif
+#ifndef PCI_CHIP_I830_M
+#define PCI_CHIP_I830_M 0x3577
+#define PCI_CHIP_I830_M_BRIDGE 0x3575
+#endif
+
+#ifndef PCI_CHIP_845_G
+#define PCI_CHIP_845_G 0x2562
+#define PCI_CHIP_845_G_BRIDGE 0x2560
+#endif
+
#ifndef PCI_CHIP_I855_GM
#define PCI_CHIP_I855_GM 0x3582
#define PCI_CHIP_I855_GM_BRIDGE 0x3580
commit 633dbd28218fd8a746c1735fd44a14f35bd07faa
Author: Julien Cristau <jcristau at debian.org>
Date: Thu Jan 17 22:34:21 2008 +0800
Bug 14032: i810, set default depth to 16
X fails to start without an xorg.conf on i810, because the default depth set by
the server (32) is not supported by the driver. I think the driver should
default to 16 bits (it supports 24, but when I tested it that didn't seem to
work very well, and dri is disabled at 24 bits depth anyway) instead of letting
the server use 32 and failing later on.
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 1ecb04a..53121a6 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -954,7 +954,7 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
pScrn->monitor = pScrn->confScreen->monitor;
flags24 = Support24bppFb | PreferConvert32to24 | SupportConvert32to24;
- if (!xf86SetDepthBpp(pScrn, 0, 0, 0, flags24)) {
+ if (!xf86SetDepthBpp(pScrn, 16, 0, 16, flags24)) {
return FALSE;
} else {
switch (pScrn->depth) {
commit 4fec18e07f2b23306e885d63c74661ae0e4b04d9
Author: Jesse Barnes <jesse.barnes at intel.com>
Date: Fri Jan 11 10:28:59 2008 -0800
Turn on backlight when LVDS panel is powered up
In some configurations, the LVDS may be off at startup along with the
backlight. So when turning the LVDS on for the first time, we may also need to
set the backlight to a non-zero value. So try to use the saved value if
possible, but if it's zero, make the backlight full brightness when turning on
the LVDS.
Note that this is slightly sub-optimal for configurations where zero is a valid backlight brightness.
Fixes fdo bz #13958.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index 50ecb60..ef8fa4a 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -372,6 +372,17 @@ i830SetLVDSPanelPower(xf86OutputPtr output, Bool on)
CARD32 pp_status;
if (on) {
+ /*
+ * If we're going from off->on we may need to turn on the backlight.
+ * We should use the saved value whenever possible, but on some
+ * machines 0 is a valid backlight value (due to an external backlight
+ * controller for example), so on them, when turning LVDS back on,
+ * they'll always re-maximize the brightness.
+ */
+ if (!(INREG(PP_CONTROL) & POWER_TARGET_ON) &&
+ dev_priv->backlight_duty_cycle == 0)
+ dev_priv->backlight_duty_cycle = dev_priv->backlight_max;
+
OUTREG(PP_CONTROL, INREG(PP_CONTROL) | POWER_TARGET_ON);
do {
pp_status = INREG(PP_STATUS);
commit b5cf8faf8102e6313c23de87a680cc327ac95478
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Thu Jan 10 14:25:18 2008 -0800
Remove unnecessary quirk code in CRT probing
Since we return early in the CRTC DPMS code, keeping the pipes & clocks
enabled, this code is no longer necessary. As an added bonus, VGA connections
should be reported correctly even when the pipe A quirk is active.
Updates fix for fdo bz #11432.
diff --git a/src/i830_crt.c b/src/i830_crt.c
index 3f0fc46..82a774a 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -381,13 +381,6 @@ i830_crt_detect(xf86OutputPtr output)
out:
i830ReleaseLoadDetectPipe (output, dpms_mode);
- /* Needed for some machines where the BIOS pokes at pipe A */
- if (pI830->quirk_flag & QUIRK_PIPEA_FORCE) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Overriding VGA detection, "
- "forcing pipe A on.\n");
- status = XF86OutputStatusConnected;
- }
-
return status;
}
commit 3c22ed633be2ac96eea7bc533839e956f1f31b84
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Wed Jan 9 09:47:38 2008 -0800
Add pipe A force enable quirk
On some platforms, the firmware may read & write GPU registers on lid close,
suspend/resume time or during various SMM events. If one of the graphics pipes
is disabled at that time, the GPU may hang due to the programming dependencies
of the various registers.
This patch adds a quirk to force the driver to keep pipe A enabled if
necessary, through user configuration in xorg.conf or via a platform specific
quirk. Leaving the pipe enabled comes at a power cost however, so the quirk
should only be enabled when strictly necessary.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=11432.
diff --git a/man/intel.man b/man/intel.man
index d46e3f9..e5736e5 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -175,6 +175,13 @@ Default: "EXA".
.BI "Option \*qModeDebug\*q \*q" boolean \*q
Enable printing of additional debugging information about modesetting to
the server log.
+.TP
+.BI "Option \*qForceEnablePipeA\*q \*q" boolean \*q
+Force the driver to leave pipe A enabled. May be necessary in configurations
+where the BIOS accesses pipe registers during display hotswitch or lid close,
+causing a crash. If you find that your platform needs this option, please file
+a bug against xf86-video-intel at http://bugs.freedesktop.org which includes
+the output of 'lspci -v' and 'lspci -vn'.
.SH OUTPUT CONFIGURATION
On 830M and better chipsets, the driver supports runtime configuration of
diff --git a/src/i830.h b/src/i830.h
index dcb87cc..9adbaf7 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -836,6 +836,7 @@ extern const int I830CopyROP[16];
#define QUIRK_IGNORE_TV 0x00000001
#define QUIRK_IGNORE_LVDS 0x00000002
#define QUIRK_IGNORE_MACMINI_LVDS 0x00000004
+#define QUIRK_PIPEA_FORCE 0x00000008
extern void i830_fixup_devices(ScrnInfoPtr);
#endif /* _I830_H_ */
diff --git a/src/i830_crt.c b/src/i830_crt.c
index cd71dc5..3f0fc46 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -380,6 +380,14 @@ i830_crt_detect(xf86OutputPtr output)
out:
i830ReleaseLoadDetectPipe (output, dpms_mode);
+
+ /* Needed for some machines where the BIOS pokes at pipe A */
+ if (pI830->quirk_flag & QUIRK_PIPEA_FORCE) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Overriding VGA detection, "
+ "forcing pipe A on.\n");
+ status = XF86OutputStatusConnected;
+ }
+
return status;
}
diff --git a/src/i830_display.c b/src/i830_display.c
index 0e42624..d16871d 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -724,6 +724,10 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
/* Give the overlay scaler a chance to disable if it's on this pipe */
i830_crtc_dpms_video(crtc, FALSE);
+ /* May need to leave pipe A on */
+ if ((pipe == 0) && (pI830->quirk_flag & QUIRK_PIPEA_FORCE))
+ return;
+
/* Disable the VGA plane that we never use */
OUTREG(VGACNTRL, VGA_DISP_DISABLE);
@@ -1176,14 +1180,6 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
i830PrintPll("chosen", &clock);
}
- if (dpll & DPLL_VCO_ENABLE)
- {
- OUTREG(fp_reg, fp);
- OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
- POSTING_READ(dpll_reg);
- usleep(150);
- }
-
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
* This is an exception to the general rule that mode_set doesn't turn
* things on.
@@ -1192,6 +1188,14 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
{
CARD32 lvds = INREG(LVDS);
+ if (dpll & DPLL_VCO_ENABLE)
+ {
+ OUTREG(fp_reg, fp);
+ OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+ POSTING_READ(dpll_reg);
+ usleep(150);
+ }
+
lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
/* Set the B0-B3 data pairs corresponding to whether we're going to
* set the DPLLs for dual-channel mode or not.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 32d4602..32cecff 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -298,6 +298,7 @@ typedef enum {
OPTION_INTELTEXPOOL,
#endif
OPTION_TRIPLEBUFFER,
+ OPTION_FORCEENABLEPIPEA
} I830Opts;
static OptionInfoRec I830Options[] = {
@@ -320,6 +321,7 @@ static OptionInfoRec I830Options[] = {
{OPTION_INTELTEXPOOL,"Legacy3D", OPTV_BOOLEAN, {0}, FALSE},
#endif
{OPTION_TRIPLEBUFFER, "TripleBuffer", OPTV_BOOLEAN, {0}, FALSE},
+ {OPTION_FORCEENABLEPIPEA, "ForceEnablePipeA", OPTV_BOOLEAN, {0}, FALSE},
{-1, NULL, OPTV_NONE, {0}, FALSE}
};
/* *INDENT-ON* */
@@ -1193,6 +1195,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
pI830->debug_modes = FALSE;
}
+ if (xf86ReturnOptValBool(pI830->Options, OPTION_FORCEENABLEPIPEA, FALSE))
+ pI830->quirk_flag |= QUIRK_PIPEA_FORCE;
+
/* We have to use PIO to probe, because we haven't mapped yet. */
I830SetPIOAccess(pI830);
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 323962c..8fbdbfe 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -39,6 +39,11 @@ typedef struct {
void (*hook)(I830Ptr);
} i830_quirk, *i830_quirk_ptr;
+static void quirk_pipea_force (I830Ptr pI830)
+{
+ pI830->quirk_flag |= QUIRK_PIPEA_FORCE;
+}
+
static void quirk_ignore_tv (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_TV;
@@ -86,6 +91,10 @@ static i830_quirk i830_quirk_list[] = {
/* Samsung Q35 has no TV output */
{ PCI_CHIP_I945_GM, 0x144d, 0xc504, quirk_ignore_tv },
+
+ /* Dell Inspiron 510m needs pipe A force quirk */
+ { PCI_CHIP_I855_GM, 0x1028, 0x0164, quirk_pipea_force },
+
{ 0, 0, 0, NULL },
};
commit d3b41bcf231a6ffd289c128c06aa619f554a776c
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:28:25 2008 +0800
Disable frame buffer compression on new chipset now.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 2183b1d..32d4602 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2510,7 +2510,8 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
}
/* Enable FB compression if possible */
- if (i830_fb_compression_supported(pI830) && !IS_I965GM(pI830))
+ if (i830_fb_compression_supported(pI830) && !IS_I965GM(pI830)
+ && !IS_IGD_GM(pI830))
pI830->fb_compression = TRUE;
else
pI830->fb_compression = FALSE;
commit 2f0c0427dc4113bac64cda07c6365df1f0637697
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:27:42 2008 +0800
Update PIPELINE_SELECT instruction and surface state format for new chipset
diff --git a/src/brw_structs.h b/src/brw_structs.h
index 28d8e12..d4fc5c6 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
@@ -832,9 +832,8 @@ struct brw_wm_unit_state
unsigned int program_computes_depth:1;
unsigned int program_uses_killpixel:1;
unsigned int legacy_line_rast: 1;
- unsigned int pad1:1;
- unsigned int max_threads:6;
- unsigned int pad2:1;
+ unsigned int transposed_urb_read:1;
+ unsigned int max_threads:7;
} wm5;
float global_depth_offset_constant;
@@ -977,6 +976,13 @@ struct brw_surface_state
unsigned int min_array_elt:9;
unsigned int min_lod:4;
} ss4;
+
+ struct {
+ unsigned int pad:20;
+ unsigned int y_offset:4;
+ unsigned int pad2:1;
+ unsigned int x_offset:7;
+ } ss5;
};
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 26f9db4..bed3901 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -2284,6 +2284,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BRW_STATE_SIP BRW_3D(0, 1, 2)
#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4)
+#define NEW_PIPELINE_SELECT BRW_3D(1, 1, 4)
+
#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0)
#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0)
diff --git a/src/i965_render.c b/src/i965_render.c
index ad3b53e..4b1d7f3 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -907,6 +907,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
src_sampler_offset) >> 5;
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
+ wm_state->wm5.transposed_urb_read = 0;
wm_state->wm5.thread_dispatch_enable = 1;
/* just use 16-pixel dispatch (4 subspans), don't need to change kernel
* start point
@@ -933,7 +934,10 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_LP_RING(12);
/* Match Mesa driver setup */
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ if (IS_IGD_GM(pI830))
+ OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
OUT_RING(BRW_CS_URB_STATE | 0);
OUT_RING((0 << 4) | /* URB Entry Allocation Size */
diff --git a/src/i965_video.c b/src/i965_video.c
index 0357270..928b52b 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -509,7 +509,10 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_LP_RING(12);
/* Match Mesa driver setup */
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ if (IS_IGD_GM(pI830))
+ OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
/* Mesa does this. Who knows... */
OUT_RING(BRW_CS_URB_STATE | 0);
commit 139e9affdd49dcbe08e260a0a2bd001de16566e6
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:26:57 2008 +0800
GTT access change for new integrated graphics device
diff --git a/src/i810_reg.h b/src/i810_reg.h
index a6663a4..26f9db4 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -539,6 +539,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PGETBL_SIZE_512KB (0 << 1)
#define PGETBL_SIZE_256KB (1 << 1)
#define PGETBL_SIZE_128KB (2 << 1)
+#define PGETBL_SIZE_1MB (3 << 1)
+#define PGETBL_SIZE_2MB (4 << 1)
+#define PGETBL_SIZE_1_5MB (5 << 1)
#define G33_PGETBL_SIZE_MASK (3 << 8)
#define G33_PGETBL_SIZE_1M (1 << 8)
#define G33_PGETBL_SIZE_2M (2 << 8)
diff --git a/src/i830_driver.c b/src/i830_driver.c
index eeb5ed0..2183b1d 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -455,6 +455,15 @@ I830DetectMemory(ScrnInfoPtr pScrn)
case PGETBL_SIZE_128KB:
gtt_size = 128;
break;
+ case PGETBL_SIZE_1MB:
+ gtt_size = 1024;
+ break;
+ case PGETBL_SIZE_2MB:
+ gtt_size = 2048;
+ break;
+ case PGETBL_SIZE_1_5MB:
+ gtt_size = 1024 + 512;
+ break;
default:
FatalError("Unknown GTT size value: %08x\n", (int)INREG(PGETBL_CTL));
}
@@ -509,11 +518,11 @@ I830DetectMemory(ScrnInfoPtr pScrn)
memsize = MB(64) - KB(range);
break;
case G33_GMCH_GMS_STOLEN_128M:
- if (IS_G33CLASS(pI830))
+ if (IS_I9XX(pI830))
memsize = MB(128) - KB(range);
break;
case G33_GMCH_GMS_STOLEN_256M:
- if (IS_G33CLASS(pI830))
+ if (IS_I9XX(pI830))
memsize = MB(256) - KB(range);
break;
}
@@ -599,8 +608,13 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- gttaddr = pI830->MMIOAddr + (512 * 1024);
- pI830->GTTMapSize = 512 * 1024;
+ if (IS_IGD_GM(pI830)) {
+ gttaddr = pI830->MMIOAddr + MB(2);
+ pI830->GTTMapSize = MB(2);
+ } else {
+ gttaddr = pI830->MMIOAddr + KB(512);
+ pI830->GTTMapSize = KB(512);
+ }
}
else
{
commit 4f288ff2d1e7d28bf49167f073fbce21492a7c32
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Wed Jan 9 21:25:47 2008 +0800
Add new integrated graphics chipset ids
diff --git a/src/common.h b/src/common.h
index daab52c..7737194 100644
--- a/src/common.h
+++ b/src/common.h
@@ -384,6 +384,11 @@ extern int I810_DEBUG;
#define PCI_CHIP_Q33_G_BRIDGE 0x29D0
#endif
+#ifndef PCI_CHIP_IGD_GM
+#define PCI_CHIP_IGD_GM 0x2A42
+#define PCI_CHIP_IGD_GM_BRIDGE 0x2A40
+#endif
+
#if XSERVER_LIBPCIACCESS
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
#define VENDOR_ID(p) (p)->vendor_id
@@ -415,14 +420,15 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
+#define IS_IGD_GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_IGD_GM(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810))
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 8ae35b6..1ecb04a 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -152,6 +152,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
{ 0, 0, 0 },
};
@@ -204,6 +205,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
+ {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
{-1, NULL}
};
@@ -233,6 +235,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
@@ -796,6 +799,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_G33_G:
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
+ case PCI_CHIP_IGD_GM:
xf86SetEntitySharable(usedChips[i]);
/* Allocate an entity private if necessary */
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 9a59be1..eeb5ed0 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -244,6 +244,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
+ {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
{-1, NULL}
};
@@ -267,6 +268,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED}
};
@@ -1263,6 +1265,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
case PCI_CHIP_Q33_G:
chipname = "Q33";
break;
+ case PCI_CHIP_IGD_GM:
+ chipname = "Intel Integrated Graphics Device";
+ break;
default:
chipname = "unknown chipset";
break;
@@ -2783,7 +2788,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
* alone in that case.
* Also make sure the DRM can handle the swap.
*/
- if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) &&
+ if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_IGD_GM(pI830) &&
(!pI830->directRenderingEnabled ||
(pI830->directRenderingEnabled && pI830->drmMinor >= 10))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "adjusting plane->pipe mappings "
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index cf0e345..50ecb60 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -113,7 +113,7 @@ i830_set_lvds_backlight_method(xf86OutputPtr output)
if (i830_kernel_backlight_available(output)) {
method = BCM_KERNEL;
- } else if (IS_I965GM(pI830)) {
+ } else if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
blc_pwm_ctl2 = INREG(BLC_PWM_CTL2);
if (blc_pwm_ctl2 & BLM_LEGACY_MODE2)
method = BCM_LEGACY;
@@ -161,7 +161,7 @@ i830_lvds_get_backlight_max_native(xf86OutputPtr output)
CARD32 pwm_ctl = INREG(BLC_PWM_CTL);
int val;
- if (IS_I965GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
val = ((pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK2) >>
BACKLIGHT_MODULATION_FREQ_SHIFT2);
} else {
@@ -413,7 +413,7 @@ i830_lvds_save (xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830))
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
pI830->saveBLC_PWM_CTL2 = INREG(BLC_PWM_CTL2);
pI830->savePP_ON = INREG(LVDSPP_ON);
pI830->savePP_OFF = INREG(LVDSPP_OFF);
@@ -429,7 +429,7 @@ i830_lvds_restore(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830))
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
OUTREG(BLC_PWM_CTL2, pI830->saveBLC_PWM_CTL2);
OUTREG(BLC_PWM_CTL, pI830->saveBLC_PWM_CTL);
OUTREG(LVDSPP_ON, pI830->savePP_ON);
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 6b7037e..4b04994 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -727,7 +727,7 @@ i830_sdvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
}
/* Set the SDVO control regs. */
- if (IS_I965GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
sdvox = SDVO_BORDER_ENABLE;
} else {
sdvox = INREG(dev_priv->output_device);
commit f089942689df622b1af00569eade4883a84eb7a3
Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
Date: Thu Jan 3 11:28:18 2008 +0800
Change origin i965G_1 to chipset market name G35.
diff --git a/src/common.h b/src/common.h
index 40ea038..daab52c 100644
--- a/src/common.h
+++ b/src/common.h
@@ -339,9 +339,9 @@ extern int I810_DEBUG;
#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
#endif
-#ifndef PCI_CHIP_I965_G_1
-#define PCI_CHIP_I965_G_1 0x2982
-#define PCI_CHIP_I965_G_1_BRIDGE 0x2980
+#ifndef PCI_CHIP_G35_G
+#define PCI_CHIP_G35_G 0x2982
+#define PCI_CHIP_G35_G_BRIDGE 0x2980
#endif
#ifndef PCI_CHIP_I965_Q
@@ -416,7 +416,7 @@ extern int I810_DEBUG;
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G_1 || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
diff --git a/src/i810_driver.c b/src/i810_driver.c
index a6c13ed..8ae35b6 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -144,7 +144,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I965_G_1, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ),
@@ -196,7 +196,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
{PCI_CHIP_I965_G, "965G"},
- {PCI_CHIP_I965_G_1, "965G"},
+ {PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{PCI_CHIP_I965_GM, "965GM"},
@@ -225,7 +225,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
- {PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
+ {PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, RES_SHARED_VGA},
@@ -788,7 +788,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
case PCI_CHIP_I965_G:
- case PCI_CHIP_I965_G_1:
+ case PCI_CHIP_G35_G:
case PCI_CHIP_I965_Q:
case PCI_CHIP_I946_GZ:
case PCI_CHIP_I965_GM:
diff --git a/src/i830_driver.c b/src/i830_driver.c
index ca4544d..9a59be1 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -236,7 +236,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
{PCI_CHIP_I965_G, "965G"},
- {PCI_CHIP_I965_G_1, "965G"},
+ {PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{PCI_CHIP_I965_GM, "965GM"},
@@ -259,7 +259,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
- {PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
+ {PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, RES_SHARED_VGA},
@@ -1237,9 +1237,11 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
chipname = "945GME";
break;
case PCI_CHIP_I965_G:
- case PCI_CHIP_I965_G_1:
chipname = "965G";
break;
+ case PCI_CHIP_G35_G:
+ chipname = "G35";
+ break;
case PCI_CHIP_I965_Q:
chipname = "965Q";
break;
commit 71143200ed66cb9dcc1f9edf98128be80b05619c
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Fri Jan 4 15:01:25 2008 -0800
Don't modify low bit of BLC_PWM_CTL when using combo backlight control
On some platforms, the low bit of BLC_PWM_CTL is wired as a 'max brightness'
flag, rather than a regular part of the backlight duty cycle. So when in the
combo mode, divide the total number of backlight levels available by two
(tossing one bit) and adjust the programming in the set_brightness routine.
Note that platforms with this behavior may need quirks added so that they work
by default.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index c58a7e0..cf0e345 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -234,6 +234,12 @@ i830_lvds_set_backlight_combo(xf86OutputPtr output, int level)
#endif
}
+ /*
+ * Don't set the lowest bit in combo configs since it can act as a flag for
+ * max brightness.
+ */
+ level <<= 1;
+
blc_pwm_ctl = INREG(BLC_PWM_CTL);
blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
OUTREG(BLC_PWM_CTL, blc_pwm_ctl | (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
@@ -248,7 +254,17 @@ i830_lvds_get_backlight_combo(xf86OutputPtr output)
blc_pwm_ctl = INREG(BLC_PWM_CTL);
blc_pwm_ctl &= BACKLIGHT_DUTY_CYCLE_MASK;
- return blc_pwm_ctl;
+
+ /* Since we don't use the low bit when using combo, the value is halved */
+
+ return blc_pwm_ctl >> 1;
+}
+
+static int
+i830_lvds_get_backlight_max_combo(xf86OutputPtr output)
+{
+ /* Since we don't set the low bit when using combo, the range is halved */
+ return i830_lvds_get_backlight_max_native(output) >> 1;
}
/*
@@ -661,7 +677,7 @@ i830_lvds_set_backlight_control(xf86OutputPtr output)
dev_priv->set_backlight = i830_lvds_set_backlight_combo;
dev_priv->get_backlight = i830_lvds_get_backlight_combo;
dev_priv->backlight_max =
- i830_lvds_get_backlight_max_native(output);
+ i830_lvds_get_backlight_max_combo(output);
break;
case BCM_KERNEL:
dev_priv->set_backlight = i830_lvds_set_backlight_kernel;
@@ -1003,7 +1019,7 @@ i830_lvds_init(ScrnInfoPtr pScrn)
case BCM_COMBO:
dev_priv->set_backlight = i830_lvds_set_backlight_combo;
dev_priv->get_backlight = i830_lvds_get_backlight_combo;
- dev_priv->backlight_max = i830_lvds_get_backlight_max_native(output);
+ dev_priv->backlight_max = i830_lvds_get_backlight_max_combo(output);
break;
case BCM_KERNEL:
dev_priv->set_backlight = i830_lvds_set_backlight_kernel;
commit b434bf4029d1a405216454629bcea717c779ae5a
Author: hulifox008 <hulifox008 at 163.com>
Date: Fri Jan 4 02:46:54 2008 -0800
Fix copy'n'paste-o in unused airlied i2c code.
diff --git a/src/i830_i2c.c b/src/i830_i2c.c
index da8f38e..d80229d 100644
--- a/src/i830_i2c.c
+++ b/src/i830_i2c.c
@@ -88,7 +88,7 @@ static void i830_getscl(I2CBusPtr b, int *state)
OUTREG(b->DriverPrivate.uval, GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK);
OUTREG(b->DriverPrivate.uval, 0);
val = INREG(b->DriverPrivate.uval);
- *state = ((val & GPIO_DATA_VAL_IN) != 0);
+ *state = ((val & GPIO_CLOCK_VAL_IN) != 0);
}
static int i830_getsda(I2CBusPtr b)
commit f2ffc0f6e038357dda268363e52c11ada1d0b810
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date: Thu Jan 3 11:16:15 2008 -0800
Fix compilation error when not using DRI
This patch complements 88f8b688e2316ae4a1f7485f0010ce90de54783a which
added uint64_t typed variables to avoid unsigned long overflows in
32-bit architectures but didn't include <stdint.h> with the required
definition.
When XF86DRI and _XF86DRI_SERVER_ are defined this header gets
indirectly included through "i830_dri.h", thanks to "i830_common.h"
which masquerades this problem as released in 2.1.0 and that manifests
with :
In file included from i810_driver.c:88:
i830.h:137: error: expected specifier-qualifier-list before 'uint64_t'
i830.h:240: error: expected specifier-qualifier-list before 'uint64_t'
Patch from Carlo Marcelo Arenas Belon <carenas at sajinet.com.pe>
diff --git a/src/i830.h b/src/i830.h
index fe4d6c5..dcb87cc 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -40,6 +40,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define I830DEBUG
#endif
+#include <stdint.h>
+
#ifndef REMAP_RESERVED
#define REMAP_RESERVED 0
#endif
commit 83d304c61ad5fdc58b0a9309dbd1e5a3f6cd9b01
Author: Nanhai Zou <nanhai.zou at intel.com>
Date: Wed Jan 2 10:50:44 2008 +0800
TV: fix 576p refresh rate
diff --git a/src/i830_tv.c b/src/i830_tv.c
index 14f4089..9add367 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -580,7 +580,7 @@ const static tv_mode_t tv_modes[] = {
{
.name = "576p",
.clock = 107520,
- .refresh = 59.94,
+ .refresh = 50.0,
.oversample = TV_OVERSAMPLE_4X,
.component_only = 1,
commit 96246c27cb836bae8ee02c46c68a1f2102efd14b
Author: Joakim <elupus at ecce.se>
Date: Thu Dec 27 17:09:02 2007 +0800
Aopen Minipc 965GM LVDS quirk
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 87d9a8a..323962c 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -58,28 +58,29 @@ static void quirk_mac_mini (I830Ptr pI830)
static i830_quirk i830_quirk_list[] = {
/* Aopen mini pc */
{ PCI_CHIP_I945_GM, 0xa0a0, SUBSYS_ANY, quirk_ignore_lvds },
+ { PCI_CHIP_I965_GM, 0xa0a0, SUBSYS_ANY, quirk_ignore_lvds },
{ PCI_CHIP_I965_GM, 0x8086, 0x1999, quirk_ignore_lvds },
/* Apple Mac mini has no lvds, but macbook pro does */
{ PCI_CHIP_I945_GM, 0x8086, 0x7270, quirk_mac_mini },
-
+
/* Dell Latitude X1 */
{ PCI_CHIP_I915_GM, 0x1028, 0x01a3, quirk_ignore_tv },
/* Dell XPS 1330 */
{ PCI_CHIP_I965_GM, 0x1028, 0x0209, quirk_ignore_tv },
-
+
/* Lenovo X60s has no TV output */
{ PCI_CHIP_I945_GM, 0x17aa, 0x201a, quirk_ignore_tv },
/* Lenovo T61 has no TV output */
{ PCI_CHIP_I965_GM, 0x17aa, 0x20b5, quirk_ignore_tv },
/* Lenovo 3000 v200 */
{ PCI_CHIP_I965_GM, 0x17aa, 0x3c18, quirk_ignore_tv },
-
+
/* Panasonic Toughbook CF-Y4 has no TV output */
{ PCI_CHIP_I915_GM, 0x10f7, 0x8338, quirk_ignore_tv },
/* Panasonic Toughbook CF-Y7 has no TV output */
{ PCI_CHIP_I965_GM, 0x10f7, 0x8338, quirk_ignore_tv },
-
+
/* Toshiba Satellite U300 has no TV output */
{ PCI_CHIP_I965_GM, 0x1179, 0xff50, quirk_ignore_tv },
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