xf86-video-intel: Branch 'intel-kernelmode' - 5 commits - src/i830_debug.c src/i830_dri.c src/i830_driver.c src/i830.h src/i830_memory.c src/i830_video.c src/i830_video.h src/i965_video.c
Dave Airlie
airlied at kemper.freedesktop.org
Thu Mar 6 22:46:57 PST 2008
src/i830.h | 7 ++
src/i830_debug.c | 28 ++++++----
src/i830_dri.c | 3 -
src/i830_driver.c | 1
src/i830_memory.c | 11 +---
src/i830_video.c | 48 +++++++++++------
src/i830_video.h | 2
src/i965_video.c | 146 ++++++++++++++++++++++--------------------------------
8 files changed, 123 insertions(+), 123 deletions(-)
New commits:
commit 6ee8da01982f45e92d6aa54f03e41f0c73dbd8cf
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 7 17:41:28 2008 +1100
validate buffers into TTM space only.
If we validate into both VRAM and TTM here, then later one we emit a relocation
to only one of the memory types (i.e. TTM) the memory manager seems to lose
the plot and keep allocating memory blocks in the TTM space even though the
buffer is already there.
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 92f062a..405d426 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -165,13 +165,12 @@ i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
if (mem->bo.size != 0) {
I830Ptr pI830 = I830PTR(pScrn);
int ret;
- int flags = DRM_BO_FLAG_MEM_VRAM |
- DRM_BO_FLAG_MEM_TT |
- DRM_BO_FLAG_READ |
- DRM_BO_FLAG_WRITE;
+ int flags = DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE;
- if (mem->need_vram)
- flags &= ~DRM_BO_FLAG_MEM_TT;
+ if (mem->need_vram)
+ flags |= DRM_BO_FLAG_MEM_VRAM;
+ else
+ flags |= DRM_BO_FLAG_MEM_TT;
ret = drmBOSetStatus(pI830->drmSubFD, &mem->bo,
flags,
commit 4e8f1c49e347632c4883577f321edd23aef08f54
Merge: ba04fa5... ae527a3...
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 7 16:13:53 2008 +1100
Merge branch 'intel-batchbuffer' into intel-kernelmode
Conflicts:
src/i830_dri.c
src/i830_video.c
diff --cc src/i830_video.c
index 3fb702d,645e25c..7738d3d
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@@ -552,14 -458,15 +552,15 @@@ i830_overlay_continue(ScrnInfoPtr pScrn
if (!*pI830->overlayOn)
return;
- if (OVERLAY_NOPHYSICAL(pI830))
- flip_addr = pI830->overlay_regs->offset;
- else
- flip_addr = pI830->overlay_regs->bus_addr;
+ if (!pI830->use_ttm_batch) {
+ if (OVERLAY_NOPHYSICAL(pI830))
+ flip_addr = pI830->overlay_regs->offset;
+ else
+ flip_addr = pI830->overlay_regs->bus_addr;
+ }
if (update_filter)
flip_addr |= OFC_UPDATE;
- OVERLAY_DEBUG ("overlay_continue cmd 0x%08" CARD32_HEX
- " -> 0x%08" CARD32_HEX " sta 0x%08" CARD32_HEX "\n",
- overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
++
BEGIN_BATCH(4);
OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE);
OUT_BATCH(MI_NOOP);
@@@ -601,12 -504,10 +602,10 @@@ i830_overlay_off(ScrnInfoPtr pScrn
* Turn overlay off
*/
{
+ overlay = overlay_reg_prepare(pI830);
overlay->OCMD &= ~OVERLAY_ENABLE;
- // OVERLAY_DEBUG ("overlay_off cmd 0x%08lx -> 0x%08lx sta 0x%08lx\n",
- // overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
- OVERLAY_DEBUG ("overlay_off cmd 0x%08" CARD32_HEX
- " -> 0x%08" CARD32_HEX " sta 0x%08" CARD32_HEX "\n",
- overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
+ overlay_reg_finish(pI830);
+
BEGIN_BATCH(6);
OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE);
OUT_BATCH(MI_NOOP);
@@@ -2241,9 -2089,8 +2244,9 @@@ i830_display_video(ScrnInfoPtr pScrn, x
OCMD |= BUFFER1;
overlay->OCMD = OCMD;
- OVERLAY_DEBUG("OCMD is 0x%lx\n", OCMD);
+ OVERLAY_DEBUG("OCMD is 0x%" CARD32_HEX "\n", OCMD);
+ overlay_reg_finish(pI830);
/* make sure the overlay is on */
i830_overlay_on (pScrn);
/* and show this frame */
commit ae527a36c8d0b0e1c1ee6155740e3c832aab0d6f
Author: Kristian Høgsberg <krh at redhat.com>
Date: Thu Mar 6 18:30:13 2008 -0500
Cut down on warnings.
Fix printf formatting warnings, wrap a couple of long lines, nuke
unused variables.
diff --git a/src/i830.h b/src/i830.h
index c61767d..63ba9f0 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -890,4 +890,11 @@ extern void i830_fixup_devices(ScrnInfoPtr);
#include "intel_batchbuffer.h"
+/* Mirrors CARD32 definition in Xmd.h */
+#ifdef LONG64
+#define CARD32_HEX "x"
+#else
+#define CARD32_HEX "lx"
+#endif
+
#endif /* _I830_H_ */
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 7d0c0a0..17044b2 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -957,13 +957,14 @@ i830_dump_error_state(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- ErrorF("pgetbl_ctl: 0x%" PRIx32 "getbl_err: 0x%" PRIx32 "\n",
+ ErrorF("pgetbl_ctl: 0x%" CARD32_HEX "getbl_err: 0x%" CARD32_HEX "\n",
INREG(PGETBL_CTL), INREG(PGE_ERR));
- ErrorF("ipeir: %" PRIx32 " iphdr: %" PRIx32 "\n", INREG(IPEIR),
+ ErrorF("ipeir: %" CARD32_HEX " iphdr: %" CARD32_HEX "\n", INREG(IPEIR),
INREG(IPEHR));
- ErrorF("LP ring tail: %" PRIx32 " head: %" PRIx32 " len: %" PRIx32 " start %" PRIx32 "\n",
+ ErrorF("LP ring tail: %" CARD32_HEX " head: %" CARD32_HEX
+ " len: %" CARD32_HEX " start %" CARD32_HEX "\n",
INREG(LP_RING + RING_TAIL),
INREG(LP_RING + RING_HEAD) & HEAD_ADDR,
INREG(LP_RING + RING_LEN),
@@ -974,8 +975,8 @@ i830_dump_error_state(ScrnInfoPtr pScrn)
ErrorF("instdone: %x instpm: %x\n", INREG16(INST_DONE), INREG8(INST_PM));
- ErrorF("memmode: %" PRIx32 " instps: %" PRIx32 "\n", INREG(MEMMODE),
- INREG(INST_PS));
+ ErrorF("memmode: %" CARD32_HEX " instps: %" CARD32_HEX "\n",
+ INREG(MEMMODE), INREG(INST_PS));
ErrorF("hwstam: %x ier: %x imr: %x iir: %x\n",
INREG16(HWSTAM), INREG16(IER), INREG16(IMR), INREG16(IIR));
@@ -987,12 +988,14 @@ i965_dump_error_state(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- ErrorF("pgetbl_ctl: 0x%" PRIx32 " pgetbl_err: 0x%" PRIx32 "\n",
+ ErrorF("pgetbl_ctl: 0x%" CARD32_HEX " pgetbl_err: 0x%" CARD32_HEX "\n",
INREG(PGETBL_CTL), INREG(PGE_ERR));
- ErrorF("ipeir: %" PRIx32 " iphdr: %" PRIx32 "\n", INREG(IPEIR_I965), INREG(IPEHR_I965));
+ ErrorF("ipeir: %" CARD32_HEX " iphdr: %" CARD32_HEX "\n",
+ INREG(IPEIR_I965), INREG(IPEHR_I965));
- ErrorF("LP ring tail: %" PRIx32 " head: %" PRIx32 " len: %" PRIx32 " start %" PRIx32 "\n",
+ ErrorF("LP ring tail: %" CARD32_HEX " head: %" CARD32_HEX
+ " len: %" CARD32_HEX " start %" CARD32_HEX "\n",
INREG(LP_RING + RING_TAIL),
INREG(LP_RING + RING_HEAD) & HEAD_ADDR,
INREG(LP_RING + RING_LEN), INREG(LP_RING + RING_START));
@@ -1004,15 +1007,18 @@ i965_dump_error_state(ScrnInfoPtr pScrn)
(int)INREG(INST_DONE_1));
ErrorF("instpm: %x\n", (int)INREG(INST_PM));
- ErrorF("memmode: %" PRIx32 " instps: %" PRIx32 "\n", INREG(MEMMODE), INREG(INST_PS_I965));
+ ErrorF("memmode: %" CARD32_HEX " instps: %" CARD32_HEX "\n",
+ INREG(MEMMODE), INREG(INST_PS_I965));
ErrorF("HW Status mask (hwstam): %x\nIRQ enable (ier): %x "
"imr: %x iir: %x\n",
(int)INREG(HWSTAM), (int)INREG(IER), (int)INREG(IMR),
(int)INREG(IIR));
- ErrorF("acthd: %" PRIx32 " dma_fadd_p: %" PRIx32 "\n", INREG(ACTHD), INREG(DMA_FADD_P));
- ErrorF("ecoskpd: %" PRIx32 " excc: %" PRIx32 "\n", INREG(ECOSKPD), INREG(EXCC));
+ ErrorF("acthd: %" CARD32_HEX " dma_fadd_p: %" CARD32_HEX "\n",
+ INREG(ACTHD), INREG(DMA_FADD_P));
+ ErrorF("ecoskpd: %" CARD32_HEX " excc: %" CARD32_HEX "\n",
+ INREG(ECOSKPD), INREG(EXCC));
ErrorF("cache_mode: %x/%x\n", (int)INREG(CACHE_MODE_0),
(int)INREG(CACHE_MODE_1));
diff --git a/src/i830_dri.c b/src/i830_dri.c
index d95ecb2..f739b44 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -971,7 +971,6 @@ I830DRICloseScreen(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
- I830DRIPtr pI830DRI = (I830DRIPtr) pI830->pDRIInfo->devPrivate;
DPRINTF(PFX, "I830DRICloseScreen\n");
@@ -1954,7 +1953,7 @@ I830DRI2ScreenInit(ScreenPtr pScreen)
I830Ptr pI830 = I830PTR(pScrn);
I830RingBuffer *ring = pI830->LpRing;
drm_i915_init_t info;
- int fd, major, minor, patch;
+ int fd;
const char *driverName;
unsigned int sarea_handle;
void *p;
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 1556505..c4bcee0 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2317,7 +2317,6 @@ void
IntelEmitInvarientState(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- CARD32 ctx_addr;
if (pI830->noAccel)
return;
diff --git a/src/i830_video.c b/src/i830_video.c
index dea9fde..645e25c 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -464,8 +464,8 @@ i830_overlay_continue(ScrnInfoPtr pScrn, Bool update_filter)
flip_addr = pI830->overlay_regs->bus_addr;
if (update_filter)
flip_addr |= OFC_UPDATE;
- OVERLAY_DEBUG ("overlay_continue cmd 0x%08" PRIx32 " -> 0x%08" PRIx32
- " sta 0x%08" PRIx32 "\n",
+ OVERLAY_DEBUG ("overlay_continue cmd 0x%08" CARD32_HEX
+ " -> 0x%08" CARD32_HEX " sta 0x%08" CARD32_HEX "\n",
overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
BEGIN_BATCH(4);
OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE);
@@ -505,7 +505,8 @@ i830_overlay_off(ScrnInfoPtr pScrn)
*/
{
overlay->OCMD &= ~OVERLAY_ENABLE;
- OVERLAY_DEBUG ("overlay_off cmd 0x%08" PRIx32 " -> 0x%08" PRIx32 " sta 0x%08" PRIx32 "\n",
+ OVERLAY_DEBUG ("overlay_off cmd 0x%08" CARD32_HEX
+ " -> 0x%08" CARD32_HEX " sta 0x%08" CARD32_HEX "\n",
overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
BEGIN_BATCH(6);
OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE);
@@ -1202,7 +1203,6 @@ I830CopyPackedData(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
int srcPitch,
int dstPitch, int top, int left, int h, int w)
{
- I830Ptr pI830 = I830PTR(pScrn);
unsigned char *src, *dst;
int i,j;
unsigned char *s;
@@ -1303,7 +1303,6 @@ I830CopyPlanarToPackedData(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
int srcPitch2, int dstPitch, int srcH,
int top, int left, int h, int w, int id)
{
- I830Ptr pI830 = I830PTR(pScrn);
CARD8 *dst1, *srcy, *srcu, *srcv;
int y;
@@ -1928,7 +1927,7 @@ i830_display_video(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
overlay->OBUF_1V = pPriv->VBuf1offset;
}
- OVERLAY_DEBUG("pos: 0x%" PRIx32 ", size: 0x%" PRIx32 "\n",
+ OVERLAY_DEBUG("pos: 0x%" CARD32_HEX ", size: 0x%" CARD32_HEX "\n",
overlay->DWINPOS, overlay->DWINSZ);
OVERLAY_DEBUG("dst: %d x %d, src: %d x %d\n", drw_w, drw_h, src_w, src_h);
@@ -2090,7 +2089,7 @@ i830_display_video(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
OCMD |= BUFFER1;
overlay->OCMD = OCMD;
- OVERLAY_DEBUG("OCMD is 0x%" PRIx32 "\n", OCMD);
+ OVERLAY_DEBUG("OCMD is 0x%" CARD32_HEX "\n", OCMD);
/* make sure the overlay is on */
i830_overlay_on (pScrn);
commit 334becb65e726d34cdf0828fbd322cf09219913a
Author: Kristian Høgsberg <krh at redhat.com>
Date: Thu Mar 6 15:38:26 2008 -0500
xv: Make i965 textured video work with the batchbuffer branch.
Splits the state buffer allocation out into its own BO and uses the
general and surface state base addresses to reduce relocations.
diff --git a/src/i830_video.c b/src/i830_video.c
index ccde947..dea9fde 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -841,6 +841,7 @@ I830SetupImageVideoOverlay(ScreenPtr pScreen)
pPriv->current_crtc = NULL;
pPriv->desired_crtc = NULL;
pPriv->buf = NULL;
+ pPriv->state = NULL;
pPriv->currentBuf = 0;
pPriv->gamma5 = 0xc0c0c0;
pPriv->gamma4 = 0x808080;
@@ -954,6 +955,7 @@ I830SetupImageVideoTextured(ScreenPtr pScreen)
pPriv->textured = TRUE;
pPriv->videoStatus = 0;
pPriv->buf = NULL;
+ pPriv->state = NULL;
pPriv->currentBuf = 0;
pPriv->doubleBuffer = 0;
@@ -1020,6 +1022,10 @@ I830StopVideo(ScrnInfoPtr pScrn, pointer data, Bool shutdown)
I830Sync(pScrn);
dri_bo_unreference(pPriv->buf);
pPriv->buf = NULL;
+ if (pPriv->state) {
+ dri_bo_unreference(pPriv->state);
+ pPriv->state = NULL;
+ }
pPriv->videoStatus = 0;
} else {
if (pPriv->videoStatus & CLIENT_VIDEO_ON) {
@@ -2204,7 +2210,7 @@ I830PutImage(ScrnInfoPtr pScrn,
int top, left, npixels, nlines, size;
BoxRec dstBox;
int pitchAlignMask;
- int alloc_size, extraLinear;
+ int alloc_size;
xf86CrtcPtr crtc;
if (pPriv->textured)
@@ -2327,15 +2333,9 @@ I830PutImage(ScrnInfoPtr pScrn,
ErrorF("srcPitch: %d, dstPitch: %d, size: %d\n", srcPitch, dstPitch, size);
#endif
- if (IS_I965G(pI830))
- extraLinear = BRW_LINEAR_EXTRA;
- else
- extraLinear = 0;
-
alloc_size = size;
if (pPriv->doubleBuffer)
alloc_size *= 2;
- alloc_size += extraLinear;
if (pPriv->buf) {
/* Wait for any previous acceleration to the buffer to have completed.
@@ -2353,13 +2353,25 @@ I830PutImage(ScrnInfoPtr pScrn,
if (pPriv->buf == NULL) {
pPriv->buf = dri_bo_alloc(pI830->bufmgr,
- "xv buffer", alloc_size, 16, 0);
+ "xv buffer", alloc_size, 4096,
+ DRM_BO_FLAG_MEM_LOCAL |
+ DRM_BO_FLAG_CACHED |
+ DRM_BO_FLAG_CACHED_MAPPED);
}
-
if (pPriv->buf == NULL)
return BadAlloc;
- pPriv->extra_offset = (pPriv->doubleBuffer ? size * 2 : size);
+ if (pPriv->state == NULL && IS_I965G(pI830)) {
+ pPriv->state = dri_bo_alloc(pI830->bufmgr,
+ "xv buffer", BRW_LINEAR_EXTRA, 4096,
+ DRM_BO_FLAG_MEM_LOCAL |
+ DRM_BO_FLAG_CACHED |
+ DRM_BO_FLAG_CACHED_MAPPED);
+ if (pPriv->state == NULL) {
+ dri_bo_unreference(pPriv->buf);
+ return BadAlloc;
+ }
+ }
/* fixup pointers */
pPriv->YBuf0offset = 0;
@@ -2603,6 +2615,10 @@ I830VideoBlockHandler(int i, pointer blockData, pointer pTimeout,
I830Sync(pScrn);
dri_bo_unreference(pPriv->buf);
pPriv->buf = NULL;
+ if (pPriv->state) {
+ dri_bo_unreference(pPriv->state);
+ pPriv->state = NULL;
+ }
pPriv->videoStatus = 0;
}
}
@@ -2659,7 +2675,10 @@ I830AllocateSurface(ScrnInfoPtr pScrn,
fbpitch = pI830->cpp * pScrn->displayWidth;
size = pitch * h;
- pPriv->buf = dri_bo_alloc(pI830->bufmgr, "xv surface buffer", size, 16, 0);
+ pPriv->buf = dri_bo_alloc(pI830->bufmgr, "xv surface buffer", size, 4096,
+ DRM_BO_FLAG_MEM_LOCAL |
+ DRM_BO_FLAG_CACHED |
+ DRM_BO_FLAG_CACHED_MAPPED);
if (pPriv->buf == NULL) {
xfree(surface->pitches);
xfree(surface->offsets);
diff --git a/src/i830_video.h b/src/i830_video.h
index c21e5fa..b5f6a47 100644
--- a/src/i830_video.h
+++ b/src/i830_video.h
@@ -59,7 +59,7 @@ typedef struct {
Time offTime;
Time freeTime;
dri_bo *buf; /** YUV data buffer */
- unsigned int extra_offset;
+ dri_bo *state; /** State buffer */
Bool overlayOK;
int oneLineMode;
diff --git a/src/i965_video.c b/src/i965_video.c
index fc8b42c..91b9f39 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -183,7 +183,6 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
int next_offset, total_state_size;
int vb_size = (4 * 4) * 4; /* 4 DWORDS per vertex */
char *state_base;
- int state_base_offset;
#if 0
ErrorF("BroadwaterDisplayVideoTextured: %dx%d (pitch %d)\n", width, height,
@@ -241,19 +240,12 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
binding_table_offset = ALIGN(next_offset, 32);
next_offset = binding_table_offset + (WM_BINDING_TABLE_ENTRIES * 4);
- /* Allocate an area in framebuffer for our state layout we just set up */
total_state_size = next_offset;
- assert (total_state_size < BRW_LINEAR_EXTRA);
+ assert (total_state_size < pPriv->state->size);
- /*
- * Use the extra space allocated at the end of the Xv buffer
- */
- state_base_offset = pPriv->extra_offset;
- state_base_offset = ALIGN(state_base_offset, 64);
-
- dri_bo_map(pPriv->buf, TRUE);
+ dri_bo_map(pPriv->state, TRUE);
- state_base = (char *) pPriv->buf->virtual + state_base_offset;
+ state_base = (char *) pPriv->state->virtual;
/* Set up our pointers to state structures in framebuffer. It would
* probably be a good idea to fill these structures out in system memory
* and then dump them there, instead.
@@ -274,19 +266,19 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
vb = (void *)(state_base + vb_offset);
#if 0
- ErrorF("vs: 0x%08x\n", state_base_offset + vs_offset);
- ErrorF("wm: 0x%08x\n", state_base_offset + wm_offset);
- ErrorF("sf: 0x%08x\n", state_base_offset + sf_offset);
- ErrorF("cc: 0x%08x\n", state_base_offset + cc_offset);
- ErrorF("sf kernel: 0x%08x\n", state_base_offset + sf_kernel_offset);
- ErrorF("ps kernel: 0x%08x\n", state_base_offset + ps_kernel_offset);
- ErrorF("sip kernel: 0x%08x\n", state_base_offset + sip_kernel_offset);
- ErrorF("cc_vp: 0x%08x\n", state_base_offset + cc_viewport_offset);
- ErrorF("src sampler: 0x%08x\n", state_base_offset + src_sampler_offset);
- ErrorF("vb: 0x%08x\n", state_base_offset + vb_offset);
- ErrorF("dst surf: 0x%08x\n", state_base_offset + dest_surf_offset);
- ErrorF("src surf: 0x%08x\n", state_base_offset + src_surf_offset);
- ErrorF("binding table: 0x%08x\n", state_base_offset + binding_table_offset);
+ ErrorF("vs: 0x%08x\n", vs_offset);
+ ErrorF("wm: 0x%08x\n", wm_offset);
+ ErrorF("sf: 0x%08x\n", sf_offset);
+ ErrorF("cc: 0x%08x\n", cc_offset);
+ ErrorF("sf kernel: 0x%08x\n", sf_kernel_offset);
+ ErrorF("ps kernel: 0x%08x\n", ps_kernel_offset);
+ ErrorF("sip kernel: 0x%08x\n", sip_kernel_offset);
+ ErrorF("cc_vp: 0x%08x\n", cc_viewport_offset);
+ ErrorF("src sampler: 0x%08x\n", src_sampler_offset);
+ ErrorF("vb: 0x%08x\n", vb_offset);
+ ErrorF("dst surf: 0x%08x\n", dest_surf_offset);
+ ErrorF("src surf: 0x%08x\n", src_surf_offset);
+ ErrorF("binding table: 0x%08x\n", binding_table_offset);
#endif
/* For 3D, the VS must have 8, 12, 16, 24, or 32 VUEs allocated to it.
@@ -342,11 +334,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
cc_state->cc3.ia_blend_enable = 1; /* blend alpha just like colors */
cc_state->cc3.blend_enable = 0; /* disable color blend */
cc_state->cc3.alpha_test = 0; /* disable alpha test */
-
- /* FIXME: Eek! No relocation to match this... */
- cc_state->cc4.cc_viewport_state_offset = (pPriv->buf->offset +
- state_base_offset +
- cc_viewport_offset) >> 5;
+ cc_state->cc4.cc_viewport_state_offset = cc_viewport_offset >> 5;
cc_state->cc5.dither_enable = 0; /* disable dither */
cc_state->cc5.logicop_func = 0xc; /* WHITE */
cc_state->cc5.statistics_enable = 1;
@@ -382,9 +370,9 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
DRM_BO_FLAG_MEM_TT |
DRM_BO_FLAG_WRITE |
DRM_BO_FLAG_READ,
- pPriv->buf,
+ pPriv->state,
(char *) &dest_surf_state->ss1.base_addr -
- (char *) pPriv->buf->virtual,
+ state_base,
0);
else
dest_surf_state->ss1.base_addr = intel_get_pixmap_offset(pPixmap);
@@ -420,19 +408,20 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
src_surf_state->ss0.mipmap_layout_mode = 0;
src_surf_state->ss0.render_cache_read_mode = 0;
-
- if (pI830->use_ttm_batch)
+ if (pI830->use_ttm_batch) {
+ dri_emit_reloc(pPriv->state,
+ DRM_BO_FLAG_MEM_TT |
+ DRM_BO_FLAG_WRITE |
+ DRM_BO_FLAG_READ,
+ pPriv->YBuf0offset,
+ (char *) &src_surf_state->ss1.base_addr - state_base,
+ pPriv->buf);
src_surf_state->ss1.base_addr =
- intelddx_batchbuffer_emit_pixmap(pPixmap,
- DRM_BO_FLAG_MEM_TT |
- DRM_BO_FLAG_READ,
- pPriv->buf,
- (char *) &src_surf_state->ss1.base_addr -
- (char *) pPriv->buf->virtual,
- pPriv->YBuf0offset);
- else
+ pPriv->buf->offset + pPriv->YBuf0offset;
+ } else {
src_surf_state->ss1.base_addr =
pPriv->buf->offset + pPriv->YBuf0offset;
+ }
src_surf_state->ss2.width = width - 1;
src_surf_state->ss2.height = height - 1;
@@ -443,8 +432,8 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
/* Set up a binding table for our two surfaces. Only the PS will use it */
/* XXX: are these offset from the right place? */
- binding_table[0] = state_base_offset + dest_surf_offset;
- binding_table[1] = state_base_offset + src_surf_offset;
+ binding_table[0] = dest_surf_offset;
+ binding_table[1] = src_surf_offset;
/* Set up the packed YUV source sampler. Doesn't do colorspace conversion.
*/
@@ -470,10 +459,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
memcpy (sf_kernel, sf_kernel_static, sizeof (sf_kernel_static));
memset(sf_state, 0, sizeof(*sf_state));
- /* FIXME: Eek! No relocation to match this... */
- sf_state->thread0.kernel_start_pointer =
- (pPriv->buf->offset + state_base_offset + sf_kernel_offset) >> 6;
-
+ sf_state->thread0.kernel_start_pointer = sf_kernel_offset >> 6;
sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
sf_state->sf1.single_program_flow = 1; /* XXX */
sf_state->sf1.binding_table_entry_count = 0;
@@ -504,21 +490,14 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
memcpy (ps_kernel, ps_kernel_static, sizeof (ps_kernel_static));
memset (wm_state, 0, sizeof (*wm_state));
- /* FIXME: Eek! No relocation to match this... */
- wm_state->thread0.kernel_start_pointer =
- (pPriv->buf->offset + state_base_offset + ps_kernel_offset) >> 6;
-
+ wm_state->thread0.kernel_start_pointer = ps_kernel_offset >> 6;
wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
wm_state->thread1.single_program_flow = 1; /* XXX */
wm_state->thread1.binding_table_entry_count = 2;
/* Though we never use the scratch space in our WM kernel, it has to be
* set, and the minimum allocation is 1024 bytes.
*/
- /* FIXME: Eek! No relocation to match this... */
- wm_state->thread2.scratch_space_base_pointer = (pPriv->buf->offset +
- state_base_offset +
- wm_scratch_offset) >> 10;
-
+ wm_state->thread2.scratch_space_base_pointer = wm_scratch_offset >> 10;
wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
wm_state->thread3.dispatch_grf_start_reg = 3; /* XXX */
wm_state->thread3.const_urb_entry_read_length = 0;
@@ -526,12 +505,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
wm_state->thread3.urb_entry_read_length = 1; /* XXX */
wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
wm_state->wm4.stats_enable = 1;
-
- /* FIXME: Eek! No relocation to match this... */
- wm_state->wm4.sampler_state_pointer = (pPriv->buf->offset +
- state_base_offset +
- src_sampler_offset) >> 5;
-
+ wm_state->wm4.sampler_state_pointer = src_sampler_offset >> 5;
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
wm_state->wm5.thread_dispatch_enable = 1;
@@ -539,6 +513,8 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
wm_state->wm5.enable_8_pix = 0;
wm_state->wm5.early_depth_test = 1;
+ dri_bo_unmap(pPriv->state);
+
{
BEGIN_BATCH(2);
OUT_BATCH(MI_FLUSH |
@@ -563,12 +539,16 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
OUT_BATCH((0 << 4) | /* URB Entry Allocation Size */
(0 << 0)); /* Number of URB Entries */
- /* Zero out the two base address registers so all offsets are
- * absolute
+ /* Set the base addresses for general state and surface state
+ * to our buffer.
*/
OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
- OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
+ OUT_RELOC(pPriv->state, /* General state base address */
+ DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ BASE_ADDRESS_MODIFY);
+ OUT_RELOC(pPriv->state, /* Surface state base address */
+ DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ BASE_ADDRESS_MODIFY);
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
/* general state max addr, disabled */
OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
@@ -578,9 +558,9 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
/* Set system instruction pointer */
OUT_BATCH(BRW_STATE_SIP | 0);
/* system instruction pointer */
- OUT_RELOC(pPriv->buf,
+ OUT_RELOC(pPriv->state,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- state_base_offset + sip_kernel_offset);
+ sip_kernel_offset);
OUT_BATCH(MI_NOOP);
ADVANCE_BATCH();
}
@@ -608,9 +588,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
/* Only the PS uses the binding table */
- OUT_RELOC(pPriv->buf,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- state_base_offset + binding_table_offset); /* ps */
+ OUT_BATCH(binding_table_offset); /* ps */
/* Blend constant color (magenta is fun) */
OUT_BATCH(BRW_3DSTATE_CONSTANT_COLOR | 3);
@@ -635,21 +613,15 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
/* Set the pointers to the 3d pipeline state */
OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
- OUT_BATCH(state_base_offset + vs_offset); /* 32 byte aligned */
+ OUT_BATCH(vs_offset); /* 32 byte aligned */
/* disable GS, resulting in passthrough */
OUT_BATCH(BRW_GS_DISABLE);
/* disable CLIP, resulting in passthrough */
OUT_BATCH(BRW_CLIP_DISABLE);
- OUT_RELOC(pPriv->buf,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- state_base_offset + sf_offset); /* 32 byte aligned */
- OUT_RELOC(pPriv->buf,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- state_base_offset + wm_offset); /* 32 byte aligned */
- OUT_RELOC(pPriv->buf,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- state_base_offset + cc_offset); /* 64 byte aligned */
+ OUT_BATCH(sf_offset); /* 32 byte aligned */
+ OUT_BATCH(wm_offset); /* 32 byte aligned */
+ OUT_BATCH(cc_offset); /* 64 byte aligned */
/* URB fence */
OUT_BATCH(BRW_URB_FENCE |
@@ -670,16 +642,19 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
OUT_BATCH(((URB_CS_ENTRY_SIZE - 1) << 4) |
(URB_CS_ENTRIES << 0));
- /* Set up the pointer to our vertex buffer */
- OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 2);
+ /* Set up the pointer to our vertex buffer. The vertex buffer
+ * addresses aren't relative to any of the base addresses so we
+ * have to emit a relocation. */
+ OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3);
/* four 32-bit floats per vertex */
OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
VB0_VERTEXDATA |
((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
- OUT_RELOC(pPriv->buf,
+ OUT_RELOC(pPriv->state,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- state_base_offset + vb_offset);
+ vb_offset);
OUT_BATCH(3); /* four corners to our rectangle */
+ OUT_BATCH(0); /* reserved */
/* Set up our vertex elements, sourced from the single vertex buffer. */
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
@@ -704,7 +679,6 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
- OUT_BATCH(MI_NOOP); /* pad to quadword */
ADVANCE_BATCH();
}
commit 1c29de21488a2d190da6bd6d84a1ba6877366dfb
Author: Kristian Høgsberg <krh at redhat.com>
Date: Thu Mar 6 14:28:46 2008 -0500
Take out #if 0 left in i830_dri.c by accident.
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 3c439b8..d95ecb2 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -1931,9 +1931,7 @@ I830DRI2Prepare(ScreenPtr pScreen)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[DRI2] Opened DRM device successfully\n");
-#if 0
I830InitBufMgr(pScreen);
-#endif
if (!pI830->use_ttm_batch)
return;
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