xf86-video-intel: 2 commits - src/i830_display.c src/i830_dri.c

[Jesse Barnes]

 src/i830_display.c |   36 ++++++++++++++++++++++++++++++++++++
 src/i830_dri.c     |   19 ++++++++++++++-----
 2 files changed, 50 insertions(+), 5 deletions(-)

New commits:
commit 1056d79809a3765f81113f3988bd948c1f9c673a
Author: Jesse Barnes <jbarnes at jbarnes-t61.(none)>
Date:   Tue Jun 24 10:44:23 2008 -0700

    Fix back buffer damage handler for 965+ chips
    
    When page flipping is enabled, we need to make sure any changes to the front
    buffer are reflected in the back buffer(s) or corruption might occur at page
    flip time.  So make the damage handler work on 965 by adding appropriate tiling
    flags and pitch adjustments.

diff --git a/src/i830_dri.c b/src/i830_dri.c
index 4361ad0..57fb0a4 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -996,26 +996,35 @@ static void
 I830DRIDoRefreshArea (ScrnInfoPtr pScrn, int num, BoxPtr pbox, uint32_t dst)
 {
    I830Ptr pI830 = I830PTR(pScrn);
-   int i, cmd, br13 = (pScrn->displayWidth * pI830->cpp) | (0xcc << 16);
+   unsigned int i, cmd, pitch, flags;
+
+   pitch = pScrn->displayWidth * pI830->cpp;
+   flags = 0xcc << 16; /* ROP_S */
 
    if (pScrn->bitsPerPixel == 32) {
       cmd = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
 	     XY_SRC_COPY_BLT_WRITE_RGB);
-      br13 |= 3 << 24;
+      flags |= 3 << 24;
    } else {
       cmd = (XY_SRC_COPY_BLT_CMD);
-      br13 |= 1 << 24;
+      flags |= 1 << 24;
+   }
+
+   /* We can assume tiled buffers if page flipping is on */
+   if (IS_I965G(pI830)) {
+       cmd |= XY_SRC_COPY_BLT_DST_TILED | XY_SRC_COPY_BLT_SRC_TILED;
+       pitch >>= 2;
    }
 
    for (i = 0 ; i < num ; i++, pbox++) {
       BEGIN_BATCH(8);
       OUT_BATCH(cmd);
-      OUT_BATCH(br13);
+      OUT_BATCH(flags | pitch);
       OUT_BATCH((pbox->y1 << 16) | pbox->x1);
       OUT_BATCH((pbox->y2 << 16) | pbox->x2);
       OUT_BATCH(dst);
       OUT_BATCH((pbox->y1 << 16) | pbox->x1);
-      OUT_BATCH(br13 & 0xffff);
+      OUT_BATCH(pitch);
       OUT_BATCH(pI830->front_buffer->offset);
       ADVANCE_BATCH();
    }
commit 65eee25d7d2ca979205f3776d620dbb36bf68a13
Author: Jesse Barnes <jbarnes at jbarnes-t61.(none)>
Date:   Tue Jun 24 10:41:46 2008 -0700

    Add support for keeping vblank counters sane across mode setting
    
    The DRM supports disabling of vblank interrupts when not in use, but in order
    to function properly it must also be aware of mode setting, which will reset
    the frame counter to 0.  Add code to call into the DRM before and after mode
    setting, so that it can account for any lost vblank events.

diff --git a/src/i830_display.c b/src/i830_display.c
index 7857ee3..43a761c 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -35,6 +35,7 @@
 #include <assert.h>
 #include <stdlib.h>
 #include <math.h>
+#include <sys/ioctl.h>
 
 #include "xf86.h"
 #include "i830.h"
@@ -730,6 +731,39 @@ i830_use_fb_compression(xf86CrtcPtr crtc)
     return TRUE;
 }
 
+#if defined(DRM_IOCTL_MODESET_CTL) && defined(XF86DRI)
+static void i830_modeset_ctl(xf86CrtcPtr crtc, int pre)
+{
+    ScrnInfoPtr pScrn = crtc->scrn;
+    I830Ptr pI830 = I830PTR(pScrn);
+    I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+    struct drm_modeset_ctl modeset;
+
+    modeset.crtc = intel_crtc->plane;
+
+    /*
+     * DPMS will be called many times (especially off), but we only
+     * want to catch the transition from on->off and off->on.
+     */
+    if (pre && intel_crtc->dpms_mode != DPMSModeOff) {
+	/* On -> off is a pre modeset */
+	modeset.cmd = _DRM_PRE_MODESET;
+	ioctl(pI830->drmSubFD, DRM_IOCTL_MODESET_CTL, &modeset);
+	ErrorF("modeset: on -> off on plane %d\n", modeset.crtc);
+    } else if (!pre && intel_crtc->dpms_mode == DPMSModeOff) {
+	/* Off -> on means post modeset */
+	modeset.cmd = _DRM_POST_MODESET;
+	ioctl(pI830->drmSubFD, DRM_IOCTL_MODESET_CTL, &modeset);
+	ErrorF("modeset: off -> on on plane %d\n", modeset.crtc);
+    }
+}
+#else
+static void i830_modeset_ctl(xf86CrtcPtr crtc, int dpms_state)
+{
+    return;
+}
+#endif /* DRM_IOCTL_MODESET_CTL && XF86DRI */
+
 /**
  * Sets the power management mode of the pipe and plane.
  *
@@ -797,8 +831,10 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
 	/* Reenable compression if needed */
 	if (i830_use_fb_compression(crtc))
 	    i830_enable_fb_compression(crtc);
+	i830_modeset_ctl(crtc, 0);
 	break;
     case DPMSModeOff:
+	i830_modeset_ctl(crtc, 1);
 	/* Shut off compression if in use */
 	if (i830_use_fb_compression(crtc))
 	    i830_disable_fb_compression(crtc);