xf86-video-ati: Branch 'master' - 2 commits

[Alex Deucher]

 src/pcidb/ati_pciids.csv  |    4 ++--
 src/radeon_chipinfo_gen.h |    4 ++--
 src/radeon_dri.c          |   21 +++++++++++++++++----
 src/radeon_reg.h          |    5 +++++
 4 files changed, 26 insertions(+), 8 deletions(-)

New commits:
commit b80a3e85bf9dbfc8d96a745876d75d38bea97c1a
Author: Alex Deucher <alex at botchco.com>
Date:   Mon Jun 9 20:29:47 2008 -0400

    R5xx: fix RADEONSetAgpBase() for R5xx chips
    
    Is there any reason to still do this in the ddx?
    Maybe real old drms?

diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 9fdc5b6..0fc03e4 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -820,11 +820,24 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
 }
 
 /* Initialize Radeon's AGP registers */
-static void RADEONSetAgpBase(RADEONInfoPtr info)
+static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen)
 {
+    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
     unsigned char *RADEONMMIO = info->MMIO;
 
-    OUTREG(RADEON_AGP_BASE, drmAgpBase(info->drmFD));
+    /* drm already does this, so we can probably remove this.
+     * agp_base_2 ?
+     */
+    if (info->ChipFamily == CHIP_FAMILY_RV515)
+	OUTMC(pScrn, RV515_MC_AGP_BASE, drmAgpBase(info->drmFD));
+    else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
+	     (info->ChipFamily <= CHIP_FAMILY_RV570))
+	OUTMC(pScrn, R520_MC_AGP_BASE, drmAgpBase(info->drmFD));
+    else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
+	     (info->ChipFamily == CHIP_FAMILY_RS740))
+	OUTMC(pScrn, RS690_MC_AGP_BASE, drmAgpBase(info->drmFD));
+    else if (info->ChipFamily < CHIP_FAMILY_RV515)
+	OUTREG(RADEON_AGP_BASE, drmAgpBase(info->drmFD));
 }
 
 /* Initialize the AGP state.  Request memory for use in AGP space, and
@@ -940,7 +953,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
 	       "[agp] GART Texture map mapped at 0x%08lx\n",
 	       (unsigned long)info->gartTex);
 
-    RADEONSetAgpBase(info);
+    RADEONSetAgpBase(info, pScreen);
 
     return TRUE;
 }
@@ -1722,7 +1735,7 @@ void RADEONDRIResume(ScreenPtr pScreen)
 	if (!RADEONSetAgpMode(info, pScreen))
 	    return;
 
-	RADEONSetAgpBase(info);
+	RADEONSetAgpBase(info, pScreen);
     }
 
     _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME);
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 08bf858..a9f2906 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3416,6 +3416,7 @@
 #define RS690_MC_FB_LOCATION			0x100
 #define RS690_MC_AGP_LOCATION			0x101
 #define RS690_MC_AGP_BASE			0x102
+#define RS690_MC_AGP_BASE_2                     0x103
 #define RS690_MC_STATUS                         0x90
 #define RS690_MC_STATUS_IDLE                    (1 << 0)
 
@@ -3438,10 +3439,14 @@
 
 #define RV515_MC_FB_LOCATION   0x1
 #define RV515_MC_AGP_LOCATION  0x2
+#define RV515_MC_AGP_BASE      0x3
+#define RV515_MC_AGP_BASE_2    0x4
 #define RV515_MC_CNTL          0x5
 #	define RV515_MEM_NUM_CHANNELS_MASK  0x3
 #define R520_MC_FB_LOCATION    0x4
 #define R520_MC_AGP_LOCATION   0x5
+#define R520_MC_AGP_BASE       0x6
+#define R520_MC_AGP_BASE_2     0x7
 #define R520_MC_CNTL0          0x8
 #	define R520_MEM_NUM_CHANNELS_MASK  (0x3 << 24)
 #	define R520_MEM_NUM_CHANNELS_SHIFT  24
commit ab7936708dfbee4d3676262f8010e001b73a4a38
Author: Alex Deucher <alex at botchco.com>
Date:   Mon Jun 9 17:05:04 2008 -0400

    RS4xx: RC410 chips are actually RS400 based

diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 5c89b55..9e19275 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -191,8 +191,8 @@
 "0x5975","RS485_5975","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)"
 "0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)"
 "0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)"
-"0x5A61","RC410_5A61","RS480",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)"
-"0x5A62","RC410_5A62","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)"
+"0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)"
+"0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)"
 "0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)"
 "0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)"
 "0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index 3459002..fbcebae 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -110,8 +110,8 @@ RADEONCardInfo RADEONCards[] = {
  { 0x5975, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
  { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
  { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
- { 0x5A61, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 },
- { 0x5A62, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
+ { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
+ { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
  { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
  { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
  { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },